JPS6242297B2 - - Google Patents

Info

Publication number
JPS6242297B2
JPS6242297B2 JP55145849A JP14584980A JPS6242297B2 JP S6242297 B2 JPS6242297 B2 JP S6242297B2 JP 55145849 A JP55145849 A JP 55145849A JP 14584980 A JP14584980 A JP 14584980A JP S6242297 B2 JPS6242297 B2 JP S6242297B2
Authority
JP
Japan
Prior art keywords
input
output
circuit
address
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55145849A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5694432A (en
Inventor
Teiraa Deebisu Goodon
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPS5694432A publication Critical patent/JPS5694432A/ja
Publication of JPS6242297B2 publication Critical patent/JPS6242297B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/223—Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17712—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays one of the matrices at least being reprogrammable
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Logic Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
JP14584980A 1979-12-26 1980-10-20 Programmable sequenceelogic array mechanism Granted JPS5694432A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/106,824 US4357678A (en) 1979-12-26 1979-12-26 Programmable sequential logic array mechanism

Publications (2)

Publication Number Publication Date
JPS5694432A JPS5694432A (en) 1981-07-30
JPS6242297B2 true JPS6242297B2 (US20030204162A1-20031030-M00001.png) 1987-09-08

Family

ID=22313457

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14584980A Granted JPS5694432A (en) 1979-12-26 1980-10-20 Programmable sequenceelogic array mechanism

Country Status (7)

Country Link
US (1) US4357678A (US20030204162A1-20031030-M00001.png)
EP (1) EP0031431B1 (US20030204162A1-20031030-M00001.png)
JP (1) JPS5694432A (US20030204162A1-20031030-M00001.png)
AU (1) AU537696B2 (US20030204162A1-20031030-M00001.png)
CA (1) CA1156730A (US20030204162A1-20031030-M00001.png)
DE (1) DE3066868D1 (US20030204162A1-20031030-M00001.png)
ES (1) ES8202216A1 (US20030204162A1-20031030-M00001.png)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS645494U (US20030204162A1-20031030-M00001.png) * 1987-06-25 1989-01-12

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3362830D1 (en) * 1982-02-04 1986-05-15 Merck Patent Gmbh Anisotropic compounds and liquid crystal compositions
US4661901A (en) * 1982-12-23 1987-04-28 International Business Machines Corporation Microprocessor control system utilizing overlapped programmable logic arrays
DE3342354A1 (de) * 1983-04-14 1984-10-18 Control Data Corp., Minneapolis, Minn. Weich programmierbare logikanordnung
US4791602A (en) * 1983-04-14 1988-12-13 Control Data Corporation Soft programmable logic array
US5125090A (en) * 1983-11-10 1992-06-23 Sasib S.P.A. Apparatus for vitally sensing binary data for a vital processor implemented with non-vital hardware
US4831521A (en) * 1983-11-10 1989-05-16 General Signal Corporation Vital processor implemented with non-vital hardware
US4551815A (en) * 1983-12-12 1985-11-05 Aerojet-General Corporation Functionally redundant logic network architectures with logic selection means
USRE34363E (en) * 1984-03-12 1993-08-31 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US4870302A (en) * 1984-03-12 1989-09-26 Xilinx, Inc. Configurable electrical circuit having configurable logic elements and configurable interconnects
US4599721A (en) * 1984-04-02 1986-07-08 Tektronix, Inc. Programmable cross bar multiplexer
KR940001563B1 (ko) * 1985-01-21 1994-02-24 가부시끼가이샤 히다찌세이사꾸쇼 룰 베이스 시스템
US4706216A (en) * 1985-02-27 1987-11-10 Xilinx, Inc. Configurable logic element
US4766532A (en) * 1985-04-30 1988-08-23 International Business Machines Corporation Sequential array logic
EP0207487A3 (de) * 1985-07-03 1988-06-22 Siemens Aktiengesellschaft Programmierbare Schaltung zur logischen Verknüpfung von binären Signalen
US4876640A (en) * 1986-02-07 1989-10-24 Advanced Micro Devices, Inc. Logic controller having programmable logic "and" array using a programmable gray-code counter
US5477165A (en) * 1986-09-19 1995-12-19 Actel Corporation Programmable logic module and architecture for field programmable gate array device
US4786829A (en) * 1987-02-24 1988-11-22 Letcher John H Latched fedback memory finite-state-engine
US4956767A (en) * 1988-02-23 1990-09-11 Stellar Computer, Inc. Data processing system with model for status accumulating operation by simulating sequence of arithmetic steps performed by arithmetic processor
US5109353A (en) 1988-12-02 1992-04-28 Quickturn Systems, Incorporated Apparatus for emulation of electronic hardware system
US5329470A (en) * 1988-12-02 1994-07-12 Quickturn Systems, Inc. Reconfigurable hardware emulation system
US5369593A (en) * 1989-05-31 1994-11-29 Synopsys Inc. System for and method of connecting a hardware modeling element to a hardware modeling system
US5353243A (en) * 1989-05-31 1994-10-04 Synopsys Inc. Hardware modeling system and method of use
US5198705A (en) * 1990-05-11 1993-03-30 Actel Corporation Logic module with configurable combinational and sequential blocks
IT1244938B (it) * 1991-03-06 1994-09-13 Ezio Lefons Sistema di interrogazione dei dati nelle basi e banche di dati.
US5568622A (en) * 1993-04-15 1996-10-22 Bull Hn Information Systems Inc. Method and apparatus for minimizing the number of control words in a brom control store of a microprogrammed central processor
US5680583A (en) * 1994-02-16 1997-10-21 Arkos Design, Inc. Method and apparatus for a trace buffer in an emulation system
GB9403030D0 (en) * 1994-02-17 1994-04-06 Austin Kenneth Re-configurable application specific device
US5920712A (en) * 1994-05-13 1999-07-06 Quickturn Design Systems, Inc. Emulation system having multiple emulator clock cycles per emulated clock cycle
US5819065A (en) * 1995-06-28 1998-10-06 Quickturn Design Systems, Inc. System and method for emulating memory
US5923865A (en) * 1995-06-28 1999-07-13 Quickturn Design Systems, Inc. Emulation system having multiple emulated clock cycles per emulator clock cycle and improved signal routing
US5822564A (en) * 1996-06-03 1998-10-13 Quickturn Design Systems, Inc. Checkpointing in an emulation system
US5841967A (en) * 1996-10-17 1998-11-24 Quickturn Design Systems, Inc. Method and apparatus for design verification using emulation and simulation
US5936426A (en) * 1997-02-03 1999-08-10 Actel Corporation Logic function module for field programmable array
US5960191A (en) 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US5970240A (en) * 1997-06-25 1999-10-19 Quickturn Design Systems, Inc. Method and apparatus for configurable memory emulation
AU3581200A (en) * 1999-01-06 2000-07-24 Simutech Corporation Apparatus and method for verifying a multi-component electronic design
US6279146B1 (en) * 1999-01-06 2001-08-21 Simutech Corporation Apparatus and method for verifying a multi-component electronic design
CN112003603A (zh) * 2020-06-30 2020-11-27 上海美仁半导体有限公司 一种消息扩展电路、方法、芯片、家用电器以及存储介质

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3576984A (en) * 1968-08-09 1971-05-04 Bunker Ramo Multifunction logic network
US3611309A (en) * 1969-07-24 1971-10-05 Univ Iowa State Res Found Inc Logical processing system
US3983538A (en) * 1974-05-01 1976-09-28 International Business Machines Corporation Universal LSI array logic modules with integral storage array and variable autonomous sequencing
US3936812A (en) * 1974-12-30 1976-02-03 Ibm Corporation Segmented parallel rail paths for input/output signals
US3975623A (en) * 1974-12-30 1976-08-17 Ibm Corporation Logic array with multiple readout tables
FR2348543A1 (fr) * 1976-04-15 1977-11-10 Honeywell Bull Soc Ind Memoire vive associative
US4084152A (en) * 1976-06-30 1978-04-11 International Business Machines Corporation Time shared programmable logic array
US4132979A (en) * 1976-12-15 1979-01-02 Teletype Corporation Method and apparatus for controlling a programmable logic array

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS645494U (US20030204162A1-20031030-M00001.png) * 1987-06-25 1989-01-12

Also Published As

Publication number Publication date
EP0031431A3 (en) 1981-07-22
CA1156730A (en) 1983-11-08
EP0031431B1 (en) 1984-03-07
AU6435280A (en) 1981-07-02
EP0031431A2 (en) 1981-07-08
AU537696B2 (en) 1984-07-05
ES498134A0 (es) 1982-01-01
JPS5694432A (en) 1981-07-30
DE3066868D1 (en) 1984-04-12
US4357678A (en) 1982-11-02
ES8202216A1 (es) 1982-01-01

Similar Documents

Publication Publication Date Title
JPS6242297B2 (US20030204162A1-20031030-M00001.png)
US6243281B1 (en) Method and apparatus for accessing a segment of CAM cells in an intra-row configurable CAM system
US4845664A (en) On-chip bit reordering structure
EP0053665B1 (en) Testing embedded arrays in large scale integrated circuits
US4047008A (en) Pseudo-random number sequence generator
US4586181A (en) Test pattern generating apparatus
US4095283A (en) First in-first out memory array containing special bits for replacement addressing
JPH04293135A (ja) メモリアクセス方式
US5165029A (en) Cache memory with test function
US4326290A (en) Means and methods for monitoring the storage states of a memory and other storage devices in a digital data processor
EP0086992B1 (en) Microword generation mechanism utilizing separate programmable logic arrays
US4016409A (en) Longitudinal parity generator for use with a memory
US5481581A (en) Programmable binary/interleave sequence counter
JPS6364413A (ja) 逐次近似レジスタ
US4479180A (en) Digital memory system utilizing fast and slow address dependent access cycles
EP0690450A2 (en) Memory circuit sequentially accessible by arbitrary address
EP0040219A1 (en) DATA PROCESSING SYSTEM WITH COMMUNITY MEANS FOR MONITORING AND STORAGE LOADING AND CHECKING.
US4641278A (en) Memory device with a register interchange function
US5155826A (en) Memory paging method and apparatus
US5021990A (en) Output pulse generating apparatus
JP3430231B2 (ja) 論理セル及びこれを用いた半導体集積回路
GB2128383A (en) Data storage unit
US6108803A (en) Memory cell circuit for executing specific tests on memory cells that have been designated by address data
GB2272088A (en) Rom burst transfer continuous read-out method
US5524226A (en) Register file system for microcomputer including a decoding system for concurrently activating source and destination word lines