JPS6242257A - Module discriminating system - Google Patents

Abstract

PURPOSE:To check each module before an external input/output power supply of a module to be controlled is validated, by recognizing that any object is connected onto a bus through a control module after the discrimination code proper to the module to be controlled is read out. CONSTITUTION:A discrimination code generating circuit 19 consists of discrimination codes B7-B0 of 8 bits. The codes B7 and B6 show the revision numbers of a module to be controlled. While the codes B5-B2 show the types of modules respectively and 16 types of modules can be discriminated with the 4-bit signals. The codes B1 and B0 show the set contents as long as the peculiar set to the module exists. Thus four types of setting are possible with two bits. For instance, the control module sets the selection signal at 0 and also discrimination code reading signal obtained via a discrimination code reading control line is also set at 0. thus the output of a discrimination code reading gate 17 is set at 0. As a result, a bit pattern is produced from the circuit 29 as the output of a discrimination code reading buffer 18. Then the discrimination code of the module to be controlled can be read on the data bus of a mother board.

Description

[Detailed description of the invention]

(Industrial Application Field) The present invention relates to a method for identifying controlled modules in a digital control device including a plurality of controlled modules. (Prior art and its problems) In digital control equipment that uses sequence controllers and microprocessors, the controlled modules for each functional unit are composed of printed circuit boards, and multiple of these printed circuit boards are connected to a motherboard. Generally, a method is used in which devices are connected to each other and signals are sent and received. For example, when these controlled modules are used as input/output modules, a system is adopted in which signals are sent and received from the motherboard and further input and output to the outside from another connector or terminal. Such input/output modules are available for each vertebrae depending on the type of input/output, but the external input/output connectors on the front are generally of the same type as all types of input/output modules. VC<
< , and there are some that are directly connected to external wiring. In this case, if you remove the controlled module and insert it again, if you insert it in the wrong place, not only will it not work properly, but there is also a risk of destroying the controlled module. If there have been many revisions, and you have inserted an old revision number at the spare parts terminal. Even in the old version, there is one game, but the orange ability is not enough, so the fx is normal.
This may result in no axis movement. In the conventional method, it is possible to check whether there is a controlled module at that location by checking the response signal from the other module when reading the signal or reading the file, but it is possible to check whether there is a controlled module at that location by checking the response signal from the other module when reading the signal or reading the file. Information including this had to be confirmed by visual inspection. Figure 5 shows a perspective view of a conventional digital controller, in which h is a first-stream stabilized unit that supplies all power to this device, and is composed of a microprocessor, a program memory, and a data memory. control module, b
-f is an input/output wiring JR section, and controlled modules b' to f', which are composed of, for example, various input/output modules, are input/output wiring JR units that exchange external signals with the controlled module. In addition to creating programs to realize a series of digital controller operations using the g&''i programming device, we also set the layout of input/output modules and monitor input/output errors19. It is something that can be done. A conventional device 't''i1 having the above configuration, a polygonal target ff
When the tlJ Town J module is installed, it is necessary for a human to visually check if the module is inserted in the wrong position, and if there is a leak during this visual inspection, the input/output lead wires are connected and the cables are removed after the start of operation. Its discovery is often made in the movement of Itomi, Katsukubo, and Yoni Shingin? If you use it for C history, you can use all of the old versions of the revised version.

[-I have a friend who doesn't have one or uses VC without knowing it. Therefore, the present invention aims to provide a complete module identification method E2 that eliminates such problems. (Means for solving the shortcomings) The present invention reads the identification code unique to the controlled module VC, which is connected to the bus, from the 70 identification codes interest rate (goods) module, It is designed to enable the control module to detect whether an example is connected on the bus, and to determine whether the inserted controlled module is equal to the identification code of the controlled module that has been set. be. (Implementation sequence) Is the following an implementation sequence of the present invention? This will be explained with reference to the drawings. FIG. 1 is a front view of a motherboard O into which each module is inserted, and shows a connector into which a single control module is inserted. The module transmits and receives signals to and from other modules (referred to as controlled modules) through this connector and all signals on the motherboard. 2, 3, 41-j A connector into which a controlled module is inserted, and a braked module connects all of these connectors 1
- Exchanging signals with the control module 5.6
．． Connector 1 to connector 2, connector 1 to connector 3, and connector 1 to connector 4 are individually connected by 7G-t select signal lines. 9 is an address bus, which is commonly connected to all connectors, and outputs a specific bit pattern to the control module Rukeko signal 4Ht+1. Signals can be sent to and received from specific registers within specific controlled modules. B is a data bus for inputting and outputting data for transmitting and receiving signals. 10H is a control signal line. -PFi is composed of several signal lines, and control signals for the control module to control the controlled module are transmitted. 10' is the other one. In Figure 1, three controlled modules are connected to the control module. As shown in Figure 2, even if the number of controlled joules increases, the same configuration can be achieved by increasing the number of select signals by the number of controlled modules. 29 is a control module block, and 30i-1r is an IJ output module block. It shows. Reference numerals 11 and 12 denote buffer gates for outputting select signals, which are required as many as the select signals. Here, part 9, part 2
Only one is shown in full. In the control circuit of the 28 UffilJ control module, the microprocessor 1. Although it is mainly composed of memory, its composition is the same as that of the conventional technique (a), and since it is an element for explaining the present invention, the internal circuit will be described below! The details have been omitted. Reference numeral 13 indicates a bidirectional data bus buffer), and 13' indicates a signal line for switching the direction. 14 is a buffer gate for sending address signals, 15°16
Each control signal transmission buffer is a reception buffer. ' 35 is a transmission buffer for outputting the input signal of the identification control line 10, 17 is an identification code reading gate, 18 is an identification code output bag 7 gate, and 19f''i is an identification code generation circuit. 21 is a data bus double Direction expansion gate 20 is a gate circuit for all switching of the direction, 23.2
6 are filled with bread 7 agate each. Reference numeral 36 denotes a receiving buffer 7 of the identification system koji line 10', and 22 is a control circuit of a controlled module, and since this is also the same as the conventional one, the details of the internal structure of the circuit will be omitted. Reference numeral 27 denotes another input/output connector, which may protrude from the input/output connector, for example, when connecting the input/output module to the outside of the control module. In FIG. 2, the blocks that are relevant to the present invention are a buffer 11 for outputting the select signal 2, an identification code reading gate 17, and the like.
Occupational code output gate 18. Identification code generation circuit] 9 and data bus switching gate 20, and next, this section Ov
A detailed explanation will only be given regarding c. In normal operation, signals are exchanged between the control modules 29 and 30 via the select signal line 5 and the data bus signal N8.
, address bus signal line 9, control bus signal line 10
Although this operation is performed using a VC, is it possible to use a conventional microprocessor? Since this is no different from the lifting platform used, we will omit the explanation of the operation here. Using the entire select signal history is a conventional method to prevent address settings from being sent inside the module, and if there are 8 Ilvc address role rectangles in the module, the select signal g is dangerous in normal operation. You don't have to. If the select signal 5 is selected now, the select signal S2 on the select Gl'-Q4jjl5 which is applied to the motherboard O is set to "O" below the low level c. VC is set to become a member of the public. Fig. 2 shows a case where the control module recognizes the identification code of the controlled module using the select signal S2 and the identification code readout line 10'. The same applies to the modules that are installed. Is the control module 29 the identification code of the controlled module 30? Procedure to read? Write it down in your oath. (1) Control module, 29 is flilJ circuit 2
8 to the select signal Me"o" on the motherboard through the select signal 2 output buffer, at Ir11, the identification code read signal line 10' also becomes I=I k ["
(2) The controlled module 30 receives the signal “0#” output to the select signal line 5 and the output “0” of the reception buffer 36.
The logical product t and 9, the data bus switching gate 2 is
The direction of the bidirectional buffer 21 for all motherboard side signal lines is switched through the wire so as not to go into output mode. (3) At the same time, the output signal of the identification code output gate buffer 17 changes the motherboard side output terminal of the identification code output gate buffer 18 from the high impedance state to the valid state, and the self-response of the identification code generation circuit 19 is changed to the data bus signal line on the motherboard. 8&C output. (4) On the system module 29 side, the data bus switching switch 6
The direction of the data bus bidirectional amplifier 13 is determined by the switching signal @13'. Switch to receive direction from motherboard, data bus signal on motherboard +5@8
', the data bus signal is read into the control circuit 28. (5) When the reading is completed, the control circuit 28 turns off the select signal to "high level", sets the output of the identification code output gate amplifier 18 of the controlled module 30 to high impedance, and connects the identification code generation circuit 19 to the data bus. ``Normal data exchange can be performed without interruption.'' Next, a specific example of identification code generation will be explained using FIG. 3. In Fig. 3, 19 is an identification code generation circuit, and 87 to BO ke identification code? : Indicates each bit name when configured with 8 pintos. 31.32H pull-up resistor, Vcctj+5V
Power supply, 33, 34 BQ, Bl focus to 1# or '0
The setting part for fixing # is ``1#'' when open, and ``9'' when shorted. B7. B5 indicates the revision number of the controlled module, and B7
=""0', B6="0" for revision 0, Mano B7=@O
'', B6=-1' indicates revised version 1. B5-B2 are codes that indicate the type of module, and in this figure, all from B5 to B2 are 11#. With this 4-bit signal, 16 modules are identified. B1.BO displays the contents of settings when this module has unique settings, and can correspond to four types of settings with %2 bits.Figure 4-1 shows the bit configuration of the identification code and the status of the bin turn set in Figure 3. In this case, as can be seen from Figure 3, the control module sends the select signal to @O”VC.
When the identification code readout signal from the identification code readout control line 10' is set to ``0'', the output of the identification code readout gate 17 becomes ``0'' and is generated by the identification code generation circuit 19 as the output of the identification code readout back 718. It is possible to obtain a nine-pit turn and read the identification code of the controlled module from the data bus of the mother gate. Figure 4-2 is a combination of Figure 4-1 and module revision number B6.
The difference between the modules having the recognition code shown in FIG. 4-1 and the recognition code shown in FIG. 4-2 means that the revision numbers are different. The module with the mental recognition code shown in Figure 4-3 and the fourth
The ISt module is the same as the one in Figure 1, and the same revision number, but the internal settings are different.
The module shown in the figure and the module shown in FIG. 4-1 have different bits representing module types, indicating that the modules have different classes. The bit pattern configuration method is, for example, B7. The bit part representing the revision number of B6 and the module capital punishment of 85 to B2 is of a nature that is integrated with the printed circuit board. In such a case, etching is performed as a nozoturn at the time of planning the print pattern, thereby reducing the number of parts and saving the effort of setting each product. -f
Nine B1. If the BO is also different for each substrate, this can be done by etching it onto the substrate in the same way. In this embodiment, the explanation has been given in terms of turns for 8 bits, but in order to increase the number of data hint strings even when the data spans 8 bits or more, the 'FQ bit of the address line and the select line are combined to form multiple bits. It is possible to do this by dividing the pattern into multiple parts and rubbing them one time. (Effects of the Invention) The module identification code output function of the present invention is a memory module y. Because the control module VC can be loaded before
As shown in the examples of FIGS. 3 and 4, since the revision number of each module, module type, and internal settings can be known, the above-mentioned problem can be solved. Then, the VC compares and judges that information in advance to see if it matches or differs from the friend module identification code set from the programming device g, and if there is a difference, it is displayed on the screen of the programming device g, and how this module is identified. By displaying the differences between the two, it is possible to completely prevent accidents that would otherwise occur with conventional equipment. That is, each module can be checked at the time of power-on, for example, before enabling the external input/output power supply of the controlled module.9 (1) Prevention of abnormal operation due to incorrect insertion of the controlled module VC (2) Simplification of troubleshooting when a controlled module is inserted incorrectly (3) Protection from destruction of the controlled module when a controlled module is incorrectly inserted (4) Use of a module with an incorrect revision number to prevent the original It is possible to improve effects such as preventing malfunction as well as preventing danger.

[Brief explanation of drawings]

Fig. 1 is a front view of a motherboard printed circuit board according to an embodiment of the present invention, Fig. 2 is a block diagram showing the configuration of the embodiment of the present invention, Fig. 3 is a detailed circuit diagram of the main parts, and Fig. 4 is an identification code. FIG. 15, which shows the code structure, is a perspective view of a digital controller using a conventional module. 1 to 4... Connectors 5 to 7... Select signal line 8... Data bus signal line 9... Address bus signal line 10... Control bus signal line 0... Motherboard printed circuit board 10'. ...Identification side bending signal line 11...Pan-A 12 for outputting select signal 2...Pan-A 13 for outputting select signal 3...Bidirectional pan 7-A 14 for data bus...Pan fer 1 for outputting address signal
5... Control signal output buffer 16... Each signal reception buffer 17... Identification code read gate 18... Identification code output gate x 7a 19... Identification code generation circuit 20... Data bus Switching gate 21...Bidirectional bread 7a 22...system for data bus (
Circuit 23...Address signal reception buffer 24...Address signal reception pan 7a 25...Control signal reception buffer 26...Response signal output buffer 27...To other input/output Connector 28...separate circuit 29...control module 30...controlled module 13'...data bus switching signal line 17'...select signal reception buffer 35...transmission buffer 36... ... Reception buffer 11 - Buffer 12 for outputting select signal 2 - Buffer 12 for outputting select signal 3 - Bidirectional 2 x 7 a 13 for data bus - Buffer 15 for outputting ares signal - Control signal Nonotsfa 16 for output...
Response signal receiving layer ζ7A17...Identification code! ! Extrusion gate 1&...Identification code output gate non-7A 19...Identification code generation circuit 20...Data bus switching signal line 21...Bidirectional data nozzle 7A 22...Control circuit 23.・Address signal reception buffer 7a 24・Address signal reception buffer 7a 25 Control signal reception buffer 26 Response signal output horn 7a 27 Connector 28 for other input/outputs・Control circuit 29...control module 30 ...Controlled module 13'...Data bus switching signal line 17'...Select signal receiving panther 35...Transmission buffer 36/Receiving panofer Fig. 4-1 Fig. 4-2 Fig. 4-3 Figure 4-4 Figure 5

Claims (1)

[Claims] In a digital control device including a plurality of controlled modules connected by bus signal lines and a different control module, an address bus, a control bus, a data bus for mutual communication of signals, and the control A select signal line that can individually specify the location of multiple controlled modules from the module and a signal line for identification control are provided, and normally no signal is output to the signal line for identification control, and an address bus is provided. Only when multiple controlled modules and the control module exchange data using the control bus, data bus, and select signal line, and the control module outputs a signal to the identification control signal line through the select signal line. A module identification method characterized in that a controlled module connected to the select signal line outputs an identification code unique to the module, which is different from that during normal operation, to a data bus.