JPS6241430B2 - - Google Patents
Info
- Publication number
- JPS6241430B2 JPS6241430B2 JP7029780A JP7029780A JPS6241430B2 JP S6241430 B2 JPS6241430 B2 JP S6241430B2 JP 7029780 A JP7029780 A JP 7029780A JP 7029780 A JP7029780 A JP 7029780A JP S6241430 B2 JPS6241430 B2 JP S6241430B2
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- molybdenum
- electrode wiring
- nitride
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000000034 method Methods 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 238000005468 ion implantation Methods 0.000 claims description 9
- 238000002844 melting Methods 0.000 claims description 9
- 230000008018 melting Effects 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 7
- 239000002344 surface layer Substances 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 5
- 150000002739 metals Chemical class 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 19
- 229910052750 molybdenum Inorganic materials 0.000 description 19
- 239000011733 molybdenum Substances 0.000 description 19
- 239000010408 film Substances 0.000 description 13
- 239000010937 tungsten Substances 0.000 description 10
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 9
- 229910052721 tungsten Inorganic materials 0.000 description 9
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 6
- 239000007789 gas Substances 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 6
- 239000001257 hydrogen Substances 0.000 description 6
- 229910052739 hydrogen Inorganic materials 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005121 nitriding Methods 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910001182 Mo alloy Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 239000012298 atmosphere Substances 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 239000005360 phosphosilicate glass Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
- -1 tungsten nitride Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Description
本発明はMOS型半導体装置の製造方法に関す
るものである。MOS型半導体装置の高密度化に
伴い、ゲート電極配線部の配線抵抗に起因する信
号伝播遅延が大規模集積回路の高速動作に対する
主要な制限因子になつていることは周知である。
この様な従来の多結晶シリコンゲート構造にお
けるゲート配線抵抗の問題を解決する方法とし
て、モリブデン又はタングステンあるいはこれら
の金属の合金等々の高融点金属をゲート電極配線
に用いるいわゆる高融点金属ゲート技術が大規模
集積回路あるいは高周波用デユアルゲートMOS
型トランジスタにおいて検討されている。
しかしモリブデンやタングステン等々の高融点
金属薄膜をゲート配線として用いた場合には次の
様な問題があつた。チヤネル長の短かいMOS型
トランジスタにおいては、いわゆる比例縮小原理
によりソース・ドレイン領域の接合深さをも浅く
することが望ましく、この為ソース・ドレイン領
域は通常イオン注入法によつて形成される。イオ
ン注入法によるソース・ドレイン領域の形成は、
ゲート電極配線をイオン注入マスクとしたいわゆ
る自己整合法によつ通常行われる。しかしなが
ら、モリブデン又はタングステン等々の高融点金
属をゲート電極配線として用いた構造に対してイ
オン注入による自己整合法でソース・ドレイン領
域を形成すると、イオン注入によつてMOS型ダ
イオードのフラツトバンド電圧、従つてMOS型
トランジスタの閾値電圧の変動が生じるという問
題があつた。しかもこのフラツトバンド電圧や閾
値電圧の変動は、モリブデンやタングステン等々
の高融点金属薄膜の形成条件にも微妙に依存して
いるので、ロツト間、ウエハ間、あるいはウエハ
内の閾値電圧の均一性や再現性を劣化させる大き
な要因となつていた。
本発明は上記従来の高融点金属ゲートMOS型
半導体装置の製造方法における問題点を解決した
新規な高融点金属ゲートMOS型半導体装置の製
造方法を提供するものである。
本発明による方法は、モリブデン又はタングス
テン、あるいはこれらの金属の合金等々の高融点
金属からなるゲート電極配線パターンを形成する
工程と、該工程等によつて形成されたゲート電極
配線の表面層又は全体を窒化物に変換する工程
と、前記工程により表面層又は全体が窒化物に変
換されたゲート電極配線を有する構造にイオン注
入を行うことによつて自己整合的にソース・ドレ
イン領域を形成する工程、とを含むことを特徴と
するものである。
本発明による方法は、窒化モリブデン膜又は窒
化タングステン膜あるいはモリブデンとタングス
テンとの合計の窒化膜等々の場合には、イオン注
入マスクとしての膜厚は理論的に予想される程度
の膜厚以上ならソース・ドレイン領域形成のため
のイオン注入時にフラツトバンド電圧や閾値電圧
の変動が生じないという本発明者が見出した新規
な事実に基づいたものである。
次にｎチヤネルMOS型トランジスタ製造への
実施例に基づき本発明による方法を更に詳細に説
明する。周知のLOCOS形成及びゲート酸化膜形
成方法により第１図の様に断面の構造を形成す
る。ここに１はｐ型シリコン基板、２はフイール
ド酸化膜、３はゲート酸化膜である。次に第２図
の如くモリブデン膜４をたとえば周知のスパツタ
リング法によつて約0.3μｍの膜厚に形成した
後、たとえば周知のホトエツチング技術によつて
第３図の如くゲート電極配線４ａに加工する。次
に５％の水素を含む水素と窒素との混合ガス中で
600℃、５分間程度の熱処理を行うと、モリブデ
ンゲート電極配線４ａの表面層が窒化され第４図
の如く金属モリブデン部４ｂと窒化モリブデン部
４ｃとからなるゲート電極配線が形成される。次
に通常のシリコンゲート工程の如く上記工程によ
つて形成されたゲート電極配線をマスクとしてヒ
素を自己整合的にイオン注入した後、1000℃程度
の窒素雰囲気中での熱処理によつてイオン注入さ
れたヒ素を電気的に活性化することにより第５図
の如くソース・ドレイン領域５を形成する。更
に、通常のMOS工程の如く層間絶縁膜としての
リンシリケートガラス層を形成し、ソース・ドレ
イン及びゲート電極配線へのコンタクト穴開け及
びシリコン入りアルミニウム配線を形成した後保
護膜を形成することによりMOS型トランジスタ
のウエハ工程が終了する。
本発明による方法を用いて形成したMOS型ト
ランジスタと、モリブデンゲート電極配線の表面
窒化工程を経ないで従来の方法で形成したモリブ
デンゲートMOS型トランジスタとを、それぞれ
15個づつについて閾値電圧及びそのバラツキを測
定した結果、次表に示した様な結果が得られ本発
明による方法が極めて優れていることが確認され
た。
The present invention relates to a method of manufacturing a MOS type semiconductor device. It is well known that as the density of MOS semiconductor devices increases, signal propagation delays caused by wiring resistance in gate electrode wiring sections have become a major limiting factor for high-speed operation of large-scale integrated circuits. As a method to solve the problem of gate wiring resistance in conventional polycrystalline silicon gate structures, so-called high-melting point metal gate technology, in which high-melting point metals such as molybdenum, tungsten, or alloys of these metals are used for gate electrode wiring, has been widely used. Large scale integrated circuit or high frequency dual gate MOS
type transistors. However, when a thin film of a high melting point metal such as molybdenum or tungsten is used as a gate wiring, the following problems occur. In a MOS transistor with a short channel length, it is desirable to make the junction depth of the source/drain region shallow based on the so-called proportional reduction principle, and for this reason, the source/drain region is usually formed by ion implantation. The formation of source/drain regions by ion implantation is as follows:
This is usually carried out by a so-called self-alignment method using the gate electrode wiring as an ion implantation mask. However, if the source/drain regions are formed by a self-alignment method using ion implantation in a structure using a high melting point metal such as molybdenum or tungsten as the gate electrode wiring, the flat band voltage of the MOS diode, and therefore the There was a problem in that the threshold voltage of the MOS transistor varied. Furthermore, fluctuations in the flat band voltage and threshold voltage slightly depend on the formation conditions of the high melting point metal thin film such as molybdenum and tungsten, so the uniformity and reproducibility of the threshold voltage between lots, between wafers, and within a wafer can be affected. It was a major factor in deteriorating sexuality. The present invention provides a novel method for manufacturing a high melting point metal gate MOS type semiconductor device that solves the problems in the conventional method for manufacturing a high melting point metal gate MOS type semiconductor device. The method according to the present invention includes a step of forming a gate electrode wiring pattern made of a high melting point metal such as molybdenum, tungsten, or an alloy of these metals, and a process of forming a surface layer or the entire gate electrode wiring formed by this step. a step of converting into nitride, and a step of forming source/drain regions in a self-aligned manner by performing ion implantation into a structure having a gate electrode wiring whose surface layer or the entire surface layer is converted into nitride by the above step. , and. In the method according to the present invention, in the case of a molybdenum nitride film, a tungsten nitride film, a nitride film of molybdenum and tungsten, etc., the film thickness as an ion implantation mask is greater than the theoretically predicted film thickness. - This is based on the novel fact discovered by the inventor that no fluctuations in flat band voltage or threshold voltage occur during ion implantation for forming the drain region. The method according to the invention will now be explained in more detail on the basis of an example for manufacturing an n-channel MOS transistor. A cross-sectional structure as shown in FIG. 1 is formed by the well-known LOCOS formation and gate oxide film formation methods. Here, 1 is a p-type silicon substrate, 2 is a field oxide film, and 3 is a gate oxide film. Next, as shown in FIG. 2, a molybdenum film 4 is formed to a thickness of about 0.3 μm by, for example, a well-known sputtering method, and then processed into a gate electrode wiring 4a as shown in FIG. 3 by, for example, a well-known photoetching technique. . Next, in a mixed gas of hydrogen and nitrogen containing 5% hydrogen.
When heat treatment is performed at 600° C. for about 5 minutes, the surface layer of the molybdenum gate electrode wiring 4a is nitrided, and a gate electrode wiring consisting of a metal molybdenum portion 4b and a molybdenum nitride portion 4c is formed as shown in FIG. Next, as in a normal silicon gate process, arsenic is ion-implanted in a self-aligned manner using the gate electrode wiring formed in the above process as a mask, and then ion-implanted by heat treatment in a nitrogen atmosphere at about 1000°C. By electrically activating the arsenic, source/drain regions 5 are formed as shown in FIG. Furthermore, as in a normal MOS process, a phosphosilicate glass layer is formed as an interlayer insulating film, contact holes are made for the source/drain and gate electrode wirings, and silicon-containing aluminum wiring is formed, and then a protective film is formed. The wafer process for type transistors is completed. A MOS type transistor formed using the method according to the present invention and a molybdenum gate MOS type transistor formed using a conventional method without going through the surface nitriding process of the molybdenum gate electrode wiring, respectively.
As a result of measuring the threshold voltage and its dispersion for each of the 15 samples, the results shown in the following table were obtained, confirming that the method according to the present invention is extremely superior.
【表】
本実施例においては、モリブデンゲート電極配
線の表面を窒化する方法として水素と窒素との混
合ガス中での熱処理を採用したが、他の方法、例
えばアンモニアガス中での熱処理や窒素やアンモ
ニアを含むガスのプラズマによる窒化法を用いる
こともできる。
又、上記各実施例においてはモリブデンゲート
電極配線の表面層のみを窒化物に変換する例を基
に説明してきたが、モリブデンゲート電極配線全
体が窒化物に変換されるまで窒化を行つても窒化
モリブデンは従来の多結晶シリコンよりも固有抵
抗が数分の１程度区小さいため実用上殆ど支障を
きたさない。したがつてこのような態様もまた本
発明に含まれる。
更に、ソース・ドレイン領域の形成をイオン注
入によつて行つた後、窒素ガス雰囲気中での熱処
理でなく、水素又は水素と小活性ガスとの混合ガ
ス。あるいは水素と窒素との混合ガス中の熱処理
によつて窒化モリブデン層から窒素を脱離せしめ
て再び金属モリブデンに変換せしめても、本発明
による方法の効果を減小させるものではない。こ
うした態様もまた本発明の内にある。
更に又、本発明者は上記各実施例に示した様な
効果をタングステン、及びモリブデンとタングス
テンとの合金、について実験的に確認することが
できた。本発明による方法の効果が生じる理由は
現時点では充分には明らかではないが、モリブデ
ンやタングステンと比較的良く似た金属学的ある
いは化学的性質を有するチタンやタンタル等の他
の遷移金属についても本発明による方法を適用し
得るもののようである。[Table] In this example, heat treatment in a mixed gas of hydrogen and nitrogen was used as a method of nitriding the surface of the molybdenum gate electrode wiring, but other methods such as heat treatment in ammonia gas or nitrogen or A nitriding method using plasma of a gas containing ammonia can also be used. Furthermore, in each of the above embodiments, the explanation has been based on an example in which only the surface layer of the molybdenum gate electrode wiring is converted to nitride, but even if nitriding is performed until the entire molybdenum gate electrode wiring is converted to nitride, nitridation will not occur. Molybdenum has a resistivity that is several times lower than that of conventional polycrystalline silicon, so it poses virtually no problem in practice. Therefore, such embodiments are also included in the present invention. Furthermore, after the source/drain regions are formed by ion implantation, heat treatment is not performed in a nitrogen gas atmosphere, but in hydrogen or a mixed gas of hydrogen and a small active gas. Alternatively, the effect of the method of the present invention will not be reduced even if nitrogen is removed from the molybdenum nitride layer by heat treatment in a mixed gas of hydrogen and nitrogen and converted back into metallic molybdenum. Such embodiments are also within the invention. Furthermore, the present inventor was able to experimentally confirm the effects shown in the above examples for tungsten and an alloy of molybdenum and tungsten. Although the reason why the method of the present invention is effective is not fully clear at present, this study also applies to other transition metals such as titanium and tantalum, which have relatively similar metallurgical or chemical properties to molybdenum and tungsten. It appears that the method according to the invention can be applied.
第１図〜第５図は本発明による方法をMOS型
トランジスタ製造へ応用した実施例を、その主要
工程を追つて示した模式的断面図である。
１……ｐ型シリコン基板、２……フイールド酸
化膜、３……ゲート酸化膜、４……モリブデン薄
膜、４ａ，４ｂ……モリブデンゲート電極配線、
４ｃ……窒化モリブデン層、５……ソース・ドレ
イン領域。
1 to 5 are schematic cross-sectional views showing the main steps of an embodiment in which the method of the present invention is applied to the manufacture of MOS transistors. 1... p-type silicon substrate, 2... field oxide film, 3... gate oxide film, 4... molybdenum thin film, 4a, 4b... molybdenum gate electrode wiring,
4c... Molybdenum nitride layer, 5... Source/drain region.
Claims (1)
なるゲート電極配線パターンを形成する工程と、
該工程等によつて形成されたゲート電極配線の表
面層又は全体を窒化物に変換する工程と、前記工
程により表面層又は全体が窒化物に変換されたゲ
ート電極配線を有する構造にイオン注入を行うこ
とによつて自己整合的にソース・ドレイン領域を
形成する工程、とを含むことを特徴とするMOS
型半導体装置の製造方法。1. A step of forming a gate electrode wiring pattern made of a high melting point metal or an alloy of these metals,
A step of converting the surface layer or the entirety of the gate electrode wiring formed by the above steps into nitride, and ion implantation into a structure having the gate electrode wiring whose surface layer or the entirety has been converted to nitride by the step. forming source/drain regions in a self-aligned manner by performing
A method for manufacturing a type semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7029780A JPS56167365A (en) | 1980-05-27 | 1980-05-27 | Manufacture of mos type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7029780A JPS56167365A (en) | 1980-05-27 | 1980-05-27 | Manufacture of mos type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56167365A JPS56167365A (en) | 1981-12-23 |
| JPS6241430B2 true JPS6241430B2 (en) | 1987-09-02 |
Family
ID=13427376
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7029780A Granted JPS56167365A (en) | 1980-05-27 | 1980-05-27 | Manufacture of mos type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56167365A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0665213B2 (en) * | 1985-10-31 | 1994-08-22 | 日本テキサス・インスツルメンツ株式会社 | Semiconductor device and manufacturing method thereof |
-
1980
- 1980-05-27 JP JP7029780A patent/JPS56167365A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56167365A (en) | 1981-12-23 |
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