JPS6240689A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To shorten a write recovery significantly by generating an electric potential against to a bit line paired electric potential due to the write data with the electric potential inverting circuit and supplying it to a sense amplifier. CONSTITUTION:In accordance with a write data Din through a write amplifier W-AMP, the electric potential of a bit line paired BL and an inversion BL is controlled through transistors Q3 and Q4, and the data are written at the memory cell MC. Simultaneously, the data Din are inverted and generated by an electric potential inverting circuit VI, and the inverting electric potential against to the electric potential by the write data of the bit line paired BL and the inversion BL is supplied to a sense amplifier S-AMP. Consequently, the electric potential of the bit line paired BL and the inversion BL in the write cycle is flown out by an amplifier S-AMP, the write recovery to mask this in a read cycle continuous to the write cycle is not necessary or significantly shortened and the high speed of the action can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method for shortening the cycle time of a semiconductor memory device (hereinafter also simply referred to as memory). In order to shorten this cycle time, it is effective to shorten so-called t□ (ride recovery).

However, due to the structure of the memory, the potential of the bit line when writing data (“1” or 0”) to the selected memory cell during the write cycle is as follows from the perspective of the sense amplifier:
Since the potential is such that data opposite to the relevant data is read, t□ is currently indispensable in order to mask an inconvenient read output caused by the opposite data until the next read cycle. Therefore, according to the present invention, symmetrical potentials for each of the bit line pairs determined by the data written during the write cycle are generated in a pseudo manner during each write cycle, and this is manually applied to the sense amplifier. By doing so, to is made as small as possible, or the existence of tl and lll is substantially unnecessary, thereby shortening the cycle time.

[Industrial application field]

The present invention relates to a semiconductor storage device (memory).

One of the recent demands for memory is an improvement in operating speed. For this reason, efforts are being made to improve the operating speed from various angles. Among these, the present invention seeks to improve the operating speed from the viewpoint of memory cycle time.

[Problem that the invention seeks to solve]

FIG. 5A is a circuit diagram showing the configuration of a general memory.

In this figure, the memory MEM includes a word line WL, a bit line pair BL, BL, a memory cell MC (only one is shown for simplicity) provided at each intersection of these word lines and bit line pairs, It mainly includes a write amplifier W-AMP that writes data to the memory cell MC, a sense amplifier S-AMP that reads data from the memory cell MC, and the like. Sense amplifier S-AMP is connected to bit line pair BL and BL via read transistor pair RT. Further, the write amplifier W-AMP is also connected to the pins H, i, BL, and pins τ via the read/write controller R/W-CNT.

The operation is as follows.

(1) When the memory cell MC stores data "1" during reading, the memory transistor Q is on and the memory transistor Q2 is off, and this state is maintained by the holding current source IH.X address A Assuming that memory cell MC is selected by D X and Y address ADV,
Now, since the memory transistor Q1 is on, BL
becomes higher than BL, and the read transistor pair RT
Transistors Q and Q of Q6 are turned on, and current is drawn from the sense amplifier S.AMP through line a. In other words, the potential at point A in S-AMP is lowered. This drawing is performed by a constant current source CIS. Note that all the components with the same symbol as Cl5I are constant current sources.

Since current was drawn into line a, transistor Qll in the sense amplifier S-AMP turns off (transistor Q7 forming a differential pair with it turns on), turns on transistor q+o, and turns it "H" (high). The level read data Dout, that is, data "1" is obtained.

Conversely, if memory cell MC were to store data "O", a current would be drawn through line b, contrary to the above, the potential at point B in SAMP would drop and transistor Q8 would turn on. (Q7 is off), and transistor Q1
゜ is off and the data Dou is at L” (low) level.
t, that is, data "O" is obtained.

(2) When writing, select the memory cell MC using the X address ADX and Y address A D v, and when writing data therein, the write enable signal Wπ becomes “L”, and then the desired write data Din is input. do.

When writing data Din="0" to the memory cell MC, all you need to do is turn off the memory transistor Q and turn on Q2, so write the line C from the write amplifier W-AMP.
Transistor Q of the read/write controller R/W-CNT,
turns off the memory transistor Q. At the same time, a "L" level (a value lower than the base potential of the off-state transistor of the selected cell is selected) is sent from the line d, turning on the memory transistor Q2 via the transistor Q4.

Conversely, when writing data Din = ``1'' to the memory cell MC, the ``L'' level is sent to the line C, the ``H'' level is sent to the line d, and the memory transistor Ql is turned on and Q2 is turned off. .In addition, during the above reading, the "H" or "L" level of line C and the "L" level of line d are
Or the intermediate level of “I” level is transistor Q,
, Q, are given for each base.

[Problem that the invention seeks to solve]

FIG. 6 is a waveform diagram used to explain the operation of the memory MEM. fa) i to (a) M in the same figure respectively indicate changes in the address input (X address input X, Y address input Y), write data Din, write enable signal WE, and read data Dout. The cycle time corresponds to the fastest operation. What should be noted in this figure is the ride recovery t□, which is usually set at 3 ns to 15 ns by the standard. This ride recovery t□ is necessary because it is necessary to mask the unstable period of data when transitioning from a write cycle to a read cycle. However, this t
Due to the existence of the WII, switching from a write cycle to a read cycle cannot be performed immediately, resulting in a long cycle time (which makes it impossible to realize a high-speed memory).

[Means for solving problems]

FIG. 1 is a diagram showing the principle configuration of a memory according to the present invention, and the same components are indicated with the same reference symbols throughout the figures. In this figure, vr is a potential inversion circuit which is a feature of the present invention, and the input stage of the sense amplifier S-AMP,
That is, its output is connected to line a and line b. The potential inverting circuit I operates with the write enable signal WE and the output of the write amplifier W-AMP (outputs on lines C and d) as input, and only during the period in which data is written in the write cycle. The bit line pair BL is written by the write data Din.

Potentials that are symmetrical to the potentials appearing at the respective terminals τ are generated, and these generated potentials are input to the sense amplifier S・AMP.

[For production]

A detailed analysis of the operation of the memory MEM reveals that the memory cell M
For example, when writing data "1" to C, the potentials that appear on the bit line pair BL, BL are the same as the potentials that appear on the bit line pair BL, BL, respectively, when reading data "1" from the memory cell MC. The potential is symmetrical.

The appearance of symmetrical potentials in this manner also applies when writing data "0".

The reason will be explained in detail below. At the time when data "1" is being read, the memory transistor Q1.

Q2 is on and Q2 is off. Here, as shown in FIG. 5A, the base potential of Q is q1, and the base potential of Qz is q2. Assuming that data "1" is stored in the selected memory cell, the output level of the write amplifier W-AMP is as shown below.

As shown in FIG. 5B, the write amplifier W-A is in the read state.
The output potential of MP is selected to be between the base potential q1 of the transistor Q1 in the selected memory cell in the on state and the base potential q2 of the transistor Q2 in the off state in the selected memory cell. The output of the write amplifier W.AMP in this read state will hereinafter be referred to as a read level. This read level has the same value for both c and d in the read state. In the write state, the output of the write amplifier is in the "H" and "L" states, and if one of them is "H", the other is always "L". The "H" level is selected to be higher than the base potential q1 of the on-state transistor Q of the selected cell, as shown in FIG. 5B.

The “L” level is the off-state transistor Q of the selected cell.
A value lower than the base potential q2 of 2 is selected.

Now, at the time when data "1" is being read, memory transistors Q, , Q, are on, and Q2 is off. Considering the potential of the bit line BL at this time, Ql and Q3
In the emitter capsid logic composed of Q,
Since the base potential of is higher than the base potential of Q3, Q is turned off, and the potential of BL becomes a value lower than qt by one minute of Ql. In the emitter capsid logic composed of Q2 and Q4, the base potential of Q2 is lower than the base potential of Q4, so Q4 is turned on, and the potential of BL is the potential of d (read level). From Q4
The value has decreased by ■. Therefore, if Vat (on state) of QI and V□ (on state) of 04 are equal, then (
(Actually, they are almost equal), BLO is higher than 1 king by (ql-read level). Therefore, in read transistor pair RT, Q is on, Q6 is off, and point A is “
"L", the B point becomes "H", Q is turned off in the sense amplifier S-AMP, and [)out is outputted as "1".

When reading data “1”, point A is “L” and point B is “L”.
Next, consider writing data "1", keeping in mind that the point is "H".In order to turn on Ql in the emitter cabled logic composed of Ql and Q, the output C of the write amplifier must be " On the other hand, in order to turn off Q2 in the emitter cabled logic composed of Q2 and Q4, the output d of the write amplifier must be "H".Level "H" II
The value mentioned above is selected for "L". Considering the pinto line potential at the time when this write is completed ("1" has already been stored in the cell, but the write amplifier is not written to "B"), BL changes from ql to Q. , Ir is the potential of d (
The value is lower than the "H" level) by the V□ bone of Q4. Therefore, QI (7) Vo (t7 state) and Q4 (7) V
at (on state) If equal, beep) *BL potential foil amplifier output “H” level -q 1)
Bamboo BL (7) Lower potential. Therefore, this difference is detected by the readout transistor pair RT, and the A point is H'''
, the point B becomes "L", and the input of the sense amplifier is reversed to that at the time of reading.
Since t is always set to "0", it is easy to confirm that the potentials of point A and point B are reversed when reading "0" like turning and when writing "0" is completed. Then, immediately after the write enable signal WE changes to the non-write state, that is, W = “H”, the sense amplifier S・A
Reverse data is read out to MP. If we can prevent this reverse data from appearing, we will inevitably be able to dramatically shorten ride recovery and speed up memory. Therefore, by introducing a potential inversion circuit Vl, the sense amplifier S-A
Prevent MP from reading the above reverse data.

〔Example〕

FIG. 2 is a waveform diagram showing the operation of the memory according to the present invention, and corresponds to FIG. 6 described above. Focusing on column (d) in this figure, the ride recovery t'WR is shown in Figure 6 (t in dl).
It can be seen that the time is significantly shortened compared to □. In other words,
Switching from the write cycle to the read cycle is instantaneous. The reason why such a short ride recovery is possible is that the reading of reverse data that occurs at t□ in FIG. 6 (dl+1i1!) is eliminated.

First, let us analyze the meaning of the above-mentioned inverse data assuming that the potential inversion circuit Vl in FIG. 1 does not exist. To speed up understanding, refer to the table below (potential of focus line in write state).

It should be noted that the fact that the data (“0” or “1”) and potential (’H’ or “L”) at the wood surface can be obtained has already been confirmed in the fifth
This is clear from the operation of the memory MEM explained based on Figure A.

(Dout is when Q9 is turned off) Referring to the above table, when writing data "0° to memory cell MC, bit line pair BL and BL are each set to H'
and "L'. BL is "H", BL is "L".
” This means turning on transistor Q and turning off transistor Q, which draws current from line a. Drawing current from line a involves applying a low potential to point A of sense amplifier S・AMP. caused, S-AMP
This corresponds to sending data "l" to the output port out. Conversely, when writing data '1' to the memory cell MC, the output Dout of data 'O' is sent to the sense amplifier S.
- Corresponds to sending from AMP.

As shown above, the state in which data “0” is written is data “
The state is equivalent to reading data "1", and the state writing data "1" is equivalent to the state reading data "0".

In this case, an unstable period of the read data Dout occurs after the write enable signal W shown in FIG. Immediately after reaching "H", Q is turned off via the inverter, but the light amplifier W
- Since it takes time for AMP and R/W-CNT and RT to generate a potential relationship corresponding to the store data of the selected address at points A and B, A, which is opposite to the write data,
The potential relationship at point B is input to the sense amplifier, and data opposite to the write data is output.

When data “01” is written, the noise N shown in column fd) in the same figure, (when data “1” is written, N
z) will occur. This noise N + , N Z
represents reading of the above-mentioned reverse data. By convention, the read data Dout is always set to 0 during the write period (WE="L"), as shown in the columns fd) in FIGS. 6 and 2, as described above. Therefore, the sense amplifier S-AM shown in FIG. 5A and FIG.
Transistor Q9 in P receives a write enable signal (WE="L") at its base via inverter INV and turns on. is turned off and continuous data Dout = "0" is output.

The present invention provides a potential inversion rotation Vl, and bit line pairs BL,
Regardless of each potential of B, when writing '0', the input of sense amplifier S-AMP is also set to read 'O', and when writing '1', the input of sense amplifier S-AMP is also set to '1'. '' is read out, and reading of reverse data is eliminated. In other words, as shown in FIG.
prevent the formation of

FIG. 3 is a circuit diagram showing an example of the potential inverting circuit and its peripheral portion according to the present invention. The transistors QI3 and Q14 in the potential inverting circuit Vl form a so-called current switch, and during the write period, the level of the write enable signal WE (="L") is inverted and received by the inverter INV', so that Wπ is When “L”,
Transistor Q11 is turned on and transistor Q14 is turned off.

For this reason, from the “■]” level of Y address ADY,
The "H" level from the inverter INV' is set slightly higher. Transistors Q,, + must be connected during writing.
This is to turn on either one of Q, , . In addition,
The 'H' level of inverter INV' is 1H of A D v.
``It is easy to set the resistance value to be slightly higher than the level, so it will not be explained in detail.The potentials at points A and B in the sense amplifier S・AMP during writing are It is determined by the on/off state of the transistors Q++ r Q+z, regardless of the respective potentials of the line pair BL and ILL.

It is the @H” or RL1 level of lines d and C that determines whether the transistors Q, , , Q, are on or off, and when writing data “1”, the input C is “L”.
Since the L'' level d becomes H'' level, the transistor Q11 is turned on (Ql□ is turned off), and current is drawn from the line a.

This is equivalent to the sense amplifier S-AMP reading data "1'" and setting it as the readout output Dout, and coincides with the data Din="1" being written. In other words, there is no need to read reverse data.

Similarly, when writing data “0”, line C is “H”.
Since the line d is at the 1L level, the transistor Q11 is turned off (Ct+□ is turned on), and current is drawn from the line b.

This is equivalent to the sense amplifier S-AMP reading data "0" and setting it as the readout output Dout, and the data Din being written is "0". In other words, there is no need to read reverse data.

FIG. 4 is a circuit diagram showing a detailed configuration example of a memory based on the present invention. The individual components in this figure are as already described, and are a potential inverting circuit in which Vl is the key point. One potential inversion circuit Vl may be provided in common for each memory block, and there is no disadvantage in terms of implementation.

〔Effect of the invention〕

As explained above, according to the present invention, light coverage (,
, I is substantially unnecessary or can be significantly shortened,
Since the time required from a write cycle to a read cycle can be reduced accordingly, the speed of the memory can be increased.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle configuration of the memory according to the present invention, FIG. 2 is a waveform diagram showing the operation of the memory according to the present invention, and FIG. 3 is an example of the potential inverting circuit according to the present invention and its peripheral parts. 4 is a circuit diagram showing a detailed configuration example of a memory based on the present invention; FIG. 5A is a circuit diagram showing a general memory configuration; FIG. 5B is a circuit diagram showing a typical memory configuration;
The figure is a waveform diagram used to explain the operation of FIG. 5A, and FIG. 6 is a waveform diagram used to explain the operation of the memory MEM. MEM...Memory, WL...Word line, BL
, 8 bit line pair, MC... memory cell, S-AMP... sense amplifier, W-AMP... write amplifier, ■1... potential inversion circuit, Din... write data , Dout...Continuous data, RT...Read transistor pair, R/W-CNT...Read/write controller, W
Ding...Write enable signal, ADX, ADv...Address manual, t'w+t...Ride recovery.

Claims (1)

[Claims] 1. A plurality of word lines, a plurality of bit line pairs, a plurality of memory cells connected to each intersection of these word lines and bit line pairs, and one selected memory cell. A sense amplifier reads the data stored in the selected memory cell by inputting the potential appearing on the bit line pair connected to the memory cell, and writes desired data to the bit line pair connected to the selected memory cell. In a semiconductor memory device that includes at least a write amplifier that provides a potential corresponding to data, only during a period of writing the write data, a potential that is symmetrical to the potential that appears on each bit line pair due to the write data is generated. A semiconductor memory device comprising: a potential inverting circuit for inputting the voltage to the sense amplifier.