JPS6239911A - Logic level setting circuit - Google Patents

Abstract

PURPOSE:To decrease the number of pins in an integrated circuit without needing an externally mounted parts by setting independently a DC bias and a logic output amplitude. CONSTITUTION:The titled circuit consists of an input terminal IN, a switching transistor (TR)Q11, level shift resistors R11, R12, a level shift constant current source I11, a bias resistor R13, a bias constant current source I12, current switching differential pairs Q12, Q13, a logic amplitude setting constant current source I13, the 1st current mirrors Q15, Q19, the 2nd current mirrors Q14, Q16, the 3rd current mirror circuits Q17, Q18, an output bias setting constant current source I14, an output bias resistor R14 and an output terminal OUT. The characteristic of the pair TRs constituting each current mirror circuit is made identical and a common base current amplification factor of all TRs is made at 1.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a logic level setting circuit, and more particularly to a logic level setting circuit.

The present invention relates to a logic level setting circuit that can independently set the DC bias and logic output amplitude in a circuit that obtains a logic output to which a DC bias is applied.

[Conventional technology]

Conventionally, this type of circuit, as shown in FIG. 7, has a first constant current source I61. First current mirror circuit Q62. Q63
．． Switching transistor Q61. First output resistor R61, coupling capacitor 061. Second constant current source■62. Second current mirror circuit Q64, Q6
5. It was composed of a second output resistor R62.

In FIG. 8, the logic amplitude vL (p-p'') is determined by the values of the first constant current source T61 and the first output resistance R61, and the DC bias voltage value VB is determined by the values of the second constant current source I62.
and the value of the second output resistor R62. Namely.

VL(,-,) = 161, R61vB=I62
．． It becomes R62. Also, Campling capacitor C61, +7)
The value needs to be large enough so that the logic output waveform generated across the first output resistor R61 is transmitted to the output terminal OUT without changing significantly. That is, with respect to the period of the input signal applied to the input terminal IN connected to the base of the switching transistor Q61, R61
, R62, and C61 must be sufficiently large. In particular, when the data transmission rate is slow, such as in a paging reception system, it is easy to predict that the value of C61 must be increased.

Here, let us examine the value of C61 using a specific example. 7th
In Figs.

T””10m5 R61=10Ω R62 = 10Ω V L (p p) = o, 2 v Δ■≦01・VL(p-p) ,', C61: 22.24μF becomes.

[Problem to be solved by the invention 3 From the above, in the conventional example, an increase in the number of bins and external components are required for the integration of two circuits that require a large capacitor. There are drawbacks.

Furthermore, since digital signals are transmitted through a capacitor, waveform changes inevitably occur.

SUMMARY OF THE INVENTION An object of the present invention is to provide a logic level setting circuit which eliminates the above-mentioned drawbacks.

[Failure to solve the problem]

According to the present invention, as in the embodiments shown in FIGS. 4 and 6, a differential pair consisting of a first and a second transistor, and a differential pair connected to the base of the first transistor via an input circuit are provided. a first constant current source connected to a common emitter of the first and second transistors, a drive transistor and an output transistor, the drive transistor connected to the collector of the second transistor. an output terminal connected to a first current mirror circuit connected thereto and a collector of the transistor of the front starter part 1, and connected to a constant current output of the output transistor;

an output bias setting resistor connected to the output terminal;
There is obtained a logic level setting circuit characterized in that it has a second constant current source for output bias setting connected to the output terminal.

Furthermore, according to the present invention, as in the embodiments of FIGS. 1, 3, and 5, a differential pair consisting of a first and a second transistor, and a base of the first transistor It is composed of an input terminal connected via an input circuit, a first constant current source connected to a common emitter of the first and second transistors, a drive transistor and an output transistor, and the one drive transistor is a first current mirror circuit connected to the collector of the second transistor;

an output terminal connected to the constant current output of the output transistor, a second current mirror circuit connected to the collector of the first transistor, and a third current mirror circuit connected to the output of the second current mirror circuit. current mirror circuit,
6) It has a resistor for setting an output bias connected to the output terminal and a second constant current source for setting the output bias connected to the output terminal, and the output of the third current mirror circuit is A logic level setting circuit characterized in that it is connected to the output terminal is obtained.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

Referring to FIG. 1, a first embodiment of the present invention is illustrated.

Input terminals IN, N switching transistor Qll (input circuit), level shift resistors R1, 1, RI2° level shift constant current source 111. Bias resistor R13, bias constant current source ■12. Current switching differential pair Q12. Q
13 (Q12 is the first transistor Q15. Q19. Second current mirror circuit Q14゜ Q16. Third current mirror circuit Q 17. Q18゜ Constant current source for output bias setting ■ 14. Output bias resistor R14, output Terminal OUT
including. In addition, Q15゜Q14. Q17 is the drive transistor of the current mirror circuit, Q l 9 , Q
16, Q1.8 is called the output transistor of the current mirror circuit.

Note that the characteristics of the pairs of transistors constituting each current mirror circuit are the same, and βFB of all transistors is
(Base common current amplification factor) is set to 1.

In FIG. 1, Q12. The output current 12.13 of the differential pair constituted by Q13 is as follows.

Here, ■13... Output current V12 of constant current source 113
... Voltage V13 applied to the base of Q12...'
Voltage applied to the base of h3 VT=KT/q K...Boltzmann constant T...Absolute temperature q...Electronic charge Furthermore, hFB of all transistors is 1.

Since the characteristics of the pair of transistors constituting each current mirror circuit are the same, l2=I6=I8. l3-49
becomes. Therefore, the current 10 outputted from the point where the respective collectors of Q19 and Q10 are connected is as follows.

Here, if (■12-■13)≧5vTte.

■　≧■　・(-0,987) Pa・110 key 113 So, (v12-v13)<-5VT tear lever.

I≦I・0.987 ・°・Work 10 Ki 113 becomes.

Therefore, when the input signal is Low, that is, Qll is OF
When F, (v12-v13)≧5VT, input signal is H4
When gh, that is, when Qll is ON, (v12-v
, 6) R11, Ri 2 so that <-5VT
, I If you set 11, when the input signal is Low,
■Key■,6. When the input signal is High ■10 keys■
It becomes 13.

Output voltage V. UT is voUT-(ENG,.1114)・R14・・・・・・(
4), depending on the input signal applied to the input terminal IN, when the input signal is High, voUT key (113"14), R14... (
5) When the input signal is Low, VOLIT key (-■13+114)・R14'...
・(6), and the output shown in Figure 2 is the output terminal O.
Obtained at UT.

Also, the settings in ■13 and the settings in ■14 are completely independent.
The DC bias voltage 114 and R14 of the output waveform and the logic amplitude 13 and R14 can be set completely independently.

Also, the output voltage is the saturation voltage VC of Q19 as shown in Figure 2.
It has a wide setting range excluding the saturation voltage VCE818 of ES19 and Q10.

Referring to FIG. 3, in the second embodiment of the present invention, an output bias setting resistor R14 is connected between the Vcc voltage supply line and the output terminal OUT, and an output bias setting constant current source I]4 is connected between ground and the output terminal OUT. By this.

In this embodiment, the average value of the output waveform is V. It is set based on 0.

Referring to FIG. 4, the third embodiment 7 of the present invention minimizes the number of current mirror circuits used.
This circuit uses only the current mirror circuits Q151 and Q19.

Referring to FIG. 5, a fourth embodiment of the present invention is shown.

An inverting circuit INV is used instead of the switching transistor Qll as an input circuit connected to the base of the first transistor Q12 of the differential pair.

Referring to FIG. 6, a fifth embodiment of the present invention is shown.

In the embodiment of FIG. 4, an inverting circuit INV is used as the input circuit in place of the switching transistor Qll.

[Effects of the Invention] As explained above, the present invention connects a circuit composed of a current switching differential pair and a current mirror circuit directly to an output terminal, and also connects a constant current source and a constant current source for setting a DC bias. By directly connecting the resistor to the output terminal, no external components are required, and the number of pins in integrated circuits can therefore be reduced. Furthermore, in the present invention.

Causes waveform changes. Since the DC bias voltage and the logic amplitude of the output waveform can be set independently without any interference, there is an effect that any DC bias and any logic amplitude can be easily set.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention. FIG. 2 is a diagram showing output waveforms in the first embodiment. 3 to 6 are circuit diagrams showing other embodiments of the present invention, FIG. 7 is a circuit diagram showing a conventional example, and FIG. 8 is a diagram showing output waveforms in the conventional example. IN...Input terminal, OUT...Output terminal, Qll
...Switching transistor, Q12. Q13・
...Differential pair for current switching, Q15. Q19...first current mirror circuit, Q14. Q16... second current mirror circuit, Q10. Q18...Third current mirror circuit, ■11... Constant current source for level shift. 112... Constant current source for bias, 113... Constant current source for setting logic amplitude, Constant current source for setting output bias for I14, R], 1, R12... Resistor for level shift. RI3: Resistor for bias, RI4: Resistor for output bias setting, INV: Inverting circuit. Figure 6

Claims (1)

[Scope of Claims] 1. A differential pair comprising a first and a second transistor, an input terminal connected to the base of the first transistor via an input circuit, and a differential pair comprising a first transistor and a second transistor; a first current mirror circuit comprising a first constant current source connected to a common emitter of the transistors, a drive transistor and an output transistor, the drive transistor being connected to the collector of the second transistor; an output terminal connected to the collector of the first transistor and to a constant current output of the output transistor; an output bias setting resistor connected to the output terminal; and an output connected to the output terminal. A logic level setting circuit comprising a second constant current source for bias setting. 2. A differential pair consisting of a first and a second transistor, an input terminal connected to the base of the first transistor via an input circuit, and a common emitter of the first and second transistors; a first current mirror circuit configured with a connected first constant current source, a drive transistor and an output transistor, the drive transistor being connected to the collector of the second transistor; and a constant current of the output transistor. an output terminal connected to the output; a second current mirror circuit connected to the collector of the first transistor; a third current mirror circuit connected to the output of the second current mirror circuit; It has an output bias setting resistor connected to an output terminal, and a second constant current source for output bias setting connected to the output terminal, and the output of the third current mirror circuit is connected to the output terminal. A logic level setting circuit characterized in that: