JP3397526B2 - 90 degree phase shift circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for adjusting the phase of a circuit signal, and more particularly to a 90-degree phase shift circuit for obtaining an output signal having a phase difference of 90 degrees with respect to an input signal.

[0002]

2. Description of the Related Art Conventionally, as a circuit for adjusting a phase in an electric circuit, for example, as the simplest phase delay circuit, as shown in FIG. 6A, an integrating circuit including a resistor and a capacitor is used. Things are known. In the case of this circuit, if the resistance value is R and the capacitance value of the capacitor is C,
The phase difference Θ between the input voltage Vin and the output voltage Vo is Θ = −t
It is expressed as an- ¹ (ωCR). Here, ω is the angular frequency of the input voltage Vin, and is represented by ω = 2πf (f is the frequency of the input voltage Vin).

Further, as shown in FIG. 6B, a transistor 40 is used, and the base of the transistor 40 is used as an input terminal, while a capacitor (capacitance) is provided at a connection point between the collector of the transistor 40 and a collector resistor 41. Value C) 4
3, one end of a resistor (resistance value R) 44 is connected to the connection point between the emitter of the transistor 40 and the emitter resistor 42, and the other end of these capacitors 43 and the other end of the resistor 44 are connected together. A phase delay circuit is known as an output terminal. In such a circuit, the phase difference Θ between the input voltage Vin and the output voltage Vo is Θ = −2 tan ⁻¹
(ΩCR).

On the other hand, as a phase shift circuit for advancing the phase of the output signal with respect to the phase of the input signal, for example, FIG. 7A shows a simple circuit example including a resistor and a capacitor. The one using a so-called differentiating circuit is shown. In the case of this circuit, the phase advance amount Θ of the output voltage Vo with respect to the phase of the input voltage Vin is Θ = tan
^{It is} calculated as ^-1 (1 / ωCR).

Further, FIG. 1B shows a circuit example using a transistor. This circuit example is shown in FIG.
The resistor 4 of the output stage in the phase delay circuit shown in (b)
The connection position of the capacitor 4 and the capacitor 43 is just reversed. That is, one end of the resistor (resistance value R) 44 is connected to the connection point between the transistor 40 and the collector resistance 41, and one end of the capacitor (capacitance value C) 43 is connected to the connection point between the transistor 40 and the emitter resistance 42. The other end of the resistor 44 and the other end of the capacitor 43 are connected together to serve as an output terminal. And
In this circuit, the phase advance amount Θ of the output voltage Vo with respect to the phase of the input voltage Vin is Θ = 2 tan ⁻¹ (ωCR)
Is required.

[0006]

In an electric circuit, it is sometimes desired to set the phase difference between the input signal and the output signal to 90 degrees, but in any of the circuits described above, the phase difference is expressed in the formula expressing the phase difference. It is mathematically impossible to obtain a phase difference of 90 degrees, since is the inverse of the tangent function tan ^-1 . That is, because tan 90 ° = ∞, there is no value of ωCR that realizes this. Therefore, even if the phase difference Θ is compromised in the vicinity of about 90 degrees, if the value of the capacitor or the resistance varies, the phase difference Θ also varies, so that a stable phase difference is obtained. If so, there is no variation and high precision C, R
However, there is a problem that the conventional circuit is unsuitable especially when the phase shift circuit is to be realized by an IC circuit.

In addition, in the conventional circuit,
Since the phase of the output voltage changes with respect to the phase of the input voltage depending on the frequency of the input voltage, it is not possible to meet the demand for making the phase difference between the input signal and the output signal 90 degrees regardless of the frequency of the input signal. There was a problem.

The present invention has been made in view of the above circumstances, and provides a stable and highly accurate 90-degree phase shift circuit. Another object of the present invention is to provide a 90-degree phase shift circuit that is not affected by variations in the electrical characteristics of each component. Another object of the present invention is to provide a 90-degree phase shift circuit suitable for implementation in an IC circuit. Still another object of the present invention is to provide a 90-degree phase shift circuit capable of keeping the phase difference between the input signal and the output signal at 90 degrees regardless of the frequency of the input signal.

[0009]

According to another aspect of the present invention, there is provided a 90-degree phase shift circuit, wherein a constant current flows in a non-input state, and when an input voltage is applied, the constant current and the The first current generating means for generating a current having a difference from the current having a phase advanced by 90 degrees with respect to the input voltage, and the constant current flowing in the non-input state, while the constant current flows when the input voltage is applied. Second current generating means for generating a current that is the sum of a current and a current that is 90 degrees out of phase with the input voltage; and a current generated by the first current generating means,
Voltage conversion means for generating a voltage according to a current difference from the current generated by the second current generation means.

Particularly, it is preferable that the voltage converting means converts a current obtained by subtracting a current generated by the second current generating means from a current generated by the first current generating means into a voltage. Further, it is also preferable that the voltage converting means converts a current obtained by subtracting the current generated by the first current generating means from the current generated by the second current generating means into a voltage.

According to a fourth aspect of the present invention, a 90-degree phase shift circuit has an input stage configured so that an AC voltage as an input signal is applied via a capacitor, and is fixed in the absence of the input signal. When a current is applied while the input signal is applied, a constant current and a first current generating circuit that generates a difference current between the constant current and a current flowing through the capacitor in response to the input signal are passed through the capacitor and the capacitor. Having an input stage configured to be applied with an AC voltage as an input signal, while a constant current is made to flow in the absence of the input signal, when the input signal is applied, the constant current,
A second current generating circuit that generates a current that is the sum of the current flowing through the capacitor according to the input signal, and a current that is generated by the second current generating circuit from a current that is generated by the first current generating circuit. And a voltage conversion circuit for converting the voltage into a voltage according to the result of the subtraction.

According to a fifth aspect of the present invention, a 90-degree phase shift circuit has an input stage configured to apply an AC voltage as an input signal via a capacitor, and has a constant value in the absence of the input signal. When a current is applied while the input signal is applied, a constant current and a first current generating circuit that generates a difference current between the constant current and a current flowing through the capacitor in response to the input signal are passed through the capacitor and the capacitor. Having an input stage configured to be applied with an AC voltage as an input signal, while a constant current is made to flow in the absence of the input signal, when the input signal is applied, the constant current,
A second current generating circuit that generates a current that is the sum of the current flowing through the capacitor according to the input signal, and a current that is generated by the first current generating circuit from a current that is generated by the second current generating circuit. And a voltage conversion circuit for converting the voltage into a voltage according to the result of the subtraction.

[0013]

According to the first aspect of the invention, in the first current generating means, the constant current is 90% with respect to the input voltage.
While a current (for example, I _E −K · sin (ωt + π / 2)) corresponding to the subtraction of the phase advanced current is generated, the second current generating means generates a constant current and an input voltage. A current (for example, I _E + K · sin (ωt + π / 2)) corresponding to the addition of the current advanced by 90 degrees is generated.
Here, ω is the angular frequency of the input voltage, and K is a constant determined from the input voltage, the angular frequency, and the like.

Then, the difference between these currents is taken in the voltage converting means. That is, for example, when the current of the second current generating means is subtracted from the current of the first current generating means, the constant current is canceled out, and the currents having a 90-degree phase advance caused by the input voltage are subtracted from each other. For example, using the above character formula, −2K · sin (ωt + π /
A current expressed as 2) is obtained. Furthermore, this current is 2
Since it is expressed as K · sin (ωt−π / 2), by converting this current into a voltage, an output voltage whose phase is delayed by 90 degrees with respect to the input signal can be obtained. It will be.

Further, the subtraction in the voltage conversion means is the second
In the case where the current generated by the first current generating means is subtracted from the current generated by the current generating means of 2K · sin (ωt
Since a current represented by −π / 2) is obtained, in the end,
This makes it possible to obtain an output voltage that is 90 degrees in phase with respect to the input signal.

In the invention according to claim 4, when an input signal is applied, a current represented by, for example, I _E -K · sin (ωt + π / 2) is generated in the first current generating circuit. Here, I _E is a constant current, and K · sin (ωt +
π / 2) is the current flowing from the capacitor when the input voltage is applied. Similarly, in the second current generating circuit, for example, a current represented by I _E + K · sin (ωt + π / 2) is generated.

In the voltage conversion circuit, the current generated in the second current generation circuit is subtracted from the current generated in the first current generation circuit, so that only the current generated according to the input voltage is generated. -2K ・ si
A current represented by n (ωt + π / 2) is obtained. This current is a current represented by 2K · sin (ωt−π / 2). Therefore, as a result of voltage conversion, the input voltage is As a result, an output voltage with a 90 ° phase delay will be obtained.

In the fifth aspect of the invention, when an input signal is applied, a current represented by, for example, _IE -K.sin (ωt + π / 2) is generated in the first current generating circuit. Here, I _E is a constant current, and K · sin (ωt +
π / 2) is the current flowing from the capacitor when the input voltage is applied. Similarly, in the second current generating circuit, for example, a current represented by I _E + K · sin (ωt + π / 2) is generated.

In the voltage conversion circuit, the current generated in the first current generating circuit is subtracted from the current generated in the second current generating circuit, so that only the current generated according to the input voltage is generated. 2K ・ sin
A current represented by (ωt + π / 2) is obtained, and as a result of this current being subjected to voltage conversion, an output voltage having a phase advanced by 90 degrees with respect to the input voltage is obtained.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a 90-degree phase shift circuit according to the present invention will be described below with reference to FIGS. In addition,
The members, arrangements, and the like described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.

First, the circuit configuration of the 90-degree phase shift circuit in the first embodiment shown in FIG. 1 will be described. The 90-degree phase shift circuit in the first embodiment is configured to delay the phase of the output voltage Vo by 90 degrees with respect to the input voltage vin, and is configured by using a plurality of so-called current mirror circuits. ing.

That is, first, between the power supply line 20 to which the power supply voltage Vcc is applied and the ground line 21 which is grounded, a second pnp transistor (denoted as "Q2" in FIG. 1) 2, An npn-type first transistor (denoted as "Q1" in FIG. 1) 1 and an npn-type fifth transistor (denoted as "Q5" in FIG. 1)
5, the emitter of the second transistor 2 is the power supply line 2
0, the emitter of the fifth transistor 5 is connected in series to the ground line 21 via the emitter resistor 22.

One end of a capacitor (capacitance value C) 23 is connected to the connection point between the emitter of the first transistor 1 and the collector of the fifth transistor 5, and the other end of this capacitor 23 is connected to the input terminal. 24, and the input voltage vin is applied. The base and collector of the second transistor 2 are connected so as to function as a diode, and the base and collector of the second transistor 2 are a pair of pnp type transistors forming a current mirror circuit (see FIG. 1). In the above, it is connected to the base of "Q14").

The emitter of the fourteenth transistor 14 is connected to the power supply line 20, while the collector thereof is n.
The pn-type fifteenth transistor (in FIG. 1, “Q1
5 ”) 15 and the emitter of this fifteenth transistor 15 is grounded.
Furthermore, the fourteenth and fifteenth transistors 14, 15
The output terminal 25 is connected to the connection point between the collectors of the two, and one end of the output resistance (resistance value R) 26 is connected to the other end of the output resistance 26. Vr2 is applied.

On the other hand, a pnp-type sixth transistor (denoted as "Q6" in FIG. 1) 6, a pnp-type third transistor (denoted as "Q3" in FIG. 1) 3, and npn.
Type fourth transistor (denoted as "Q4" in FIG. 1) 4 is connected in series with the configuration in which the connection of Q2, Q1 and Q5 just before is reversed between the power supply line 20 and the ground line 21. It is connected.

That is, the emitter of the sixth transistor 6 is connected to the power supply line 20 via the emitter resistor 28, while the emitter of the fourth transistor 4 is connected to the ground line 21, and its base and collector are connected. Are connected to the base of the fifteenth transistor 15 described above. Also, the connection point between the emitter of the third transistor 3 and the collector of the sixth transistor 6 is connected to one end of the capacitor 23 together with the connection point of the first and fifth transistors 1 and 5 described above. Has become. Therefore, the capacitor 23 is connected to a circuit having a low input impedance. The fourth transistor 15 and the fifteenth transistor 15 are
It is a pair of transistors forming a so-called current mirror circuit.

Further, the above-mentioned fifth transistor 5 is np
n-type tenth transistor (“Q10” in FIG. 1)
10), a twelfth transistor (denoted as “Q12” in FIG. 1) 12, and a thirteenth transistor (denoted as “Q13” in FIG. 1) 13 constitute a so-called current mirror circuit. .

Further, the above sixth transistor 6 has p
An np type seventh transistor (denoted as “Q7” in FIG. 1) 7 and an eleventh transistor (“Q7” in FIG. 1)
11)) and a so-called current mirror circuit.

That is, the thirteenth transistor 13 is
A base and a collector are connected so as to function as a diode, and the base is connected to the bases of the fifth transistor 5, the tenth transistor 10, and the twelfth transistor 12, respectively. A constant current source 29 is connected to the collector of the thirteenth transistor 13, while the emitter is grounded via an emitter resistor 30.

The collector of the twelfth transistor 12 is
While connected to the collector of the eleventh transistor 11, the emitter is grounded via the emitter resistor 31. The eleventh transistor 11 has a base and a collector connected to each other so as to function as a diode, and has an emitter connected to the power supply line 2 via an emitter resistor 32.
It is connected to 0. And the eleventh transistor 1
The base of No. 1 is connected to the bases of the sixth transistor 6 and the seventh transistor 7, respectively.

The emitter of the tenth transistor 10 is
The collector is grounded through the emitter resistor 33, while the collector is an npn-type ninth transistor (in FIG. 1, "Q").
9 ”) and the base of the third transistor 3 described above. On the other hand, the collector of the ninth transistor 9 is the power supply line 20.
A constant voltage source 34 is connected to the base together with the base of an pnp type eighth transistor (denoted as “Q8” in FIG. 1) 8 so that the bias voltage Vr1 is applied. ing.

The collector of the eighth transistor 8 is grounded, while the emitter is connected to the collector of the seventh transistor 7 and the base of the first transistor 1. The emitter of the seventh transistor 7 is connected to the power supply line 20 via the emitter resistor 35.

Next, the operation of this circuit in such a configuration will be described. First, when there is no input voltage,
Each of the first, second and fifth transistors 1, 2, 5 includes:
If the collector current and the emitter current are substantially equal to each other, the constant current I _E flows. Since the second transistor 2 and the fourteenth transistor 14 are a so-called current pair forming a so-called current mirror circuit, the second transistor 2 and the fourteenth transistor 14 also have a second collector.
The constant current I _{E, which} is the same as the constant current I _E flowing through the transistor 2 in FIG.

The constant current I _E also flows through the third, fourth and sixth transistors 3, 4, 6 in the same manner. Then, the same current flows into the collector of the fifteenth transistor 15, which is a so-called current pair with the fourth transistor 4. Therefore, the constant current I _E does not flow into the output resistor 26 and the output terminal 2
The bias voltage Vr2 only appears at 5.

Further, the sixth, seventh and eleventh transistors 6, 7, 11 together constitute a current mirror circuit, and the collector of the eleventh transistor 11 is the fifth, tenth and eleventh transistors. Since it is connected to the collector of the twelfth transistor 12 that forms the current mirror circuit together with 13, the seventh, eleventh and twelfth
A constant current I _E also flows through each of the transistors 7, 11 and 12.

The emitter potential of the first transistor 1 and the emitter potential of the third transistor 3 are biased to the same voltage Vr1 as described below. First, since the bases of the ninth and eighth transistors 9 and 8 are biased to the voltage Vr1, assuming that the voltage VBE between the base and emitter of each transistor is substantially the same, the base of the third transistor 3 will be described. The potential has a value obtained by subtracting VBE from the voltage Vr1, while the base potential of the first transistor 1 has a value obtained by adding VBE to the voltage Vr1.

The emitter potential of the third transistor 3 has a value obtained by adding VBE to its base potential.
Eventually, while the voltage becomes Vr1, the first emitter potential becomes a value obtained by subtracting VBE from its base potential, and eventually becomes the voltage Vr1, and the first and third transistors 1, 1.
The emitter potentials of 3 are both biased to the voltage Vr1. The output current Ir of the constant current source 29 is the same as the output current Ir of the fifth, tenth, and twelfth transistors 5, 10, 1.
It is equal to the sum of the currents flowing through the two collectors.

Next, consider the case where the input voltage vin is applied to the input terminal 24. Here, the input voltage is vin
= E · sinωt
The current i flowing through the capacitor 23 is a time change of the electric charge accumulated in the capacitor 23, and is obtained as follows. That is, i = dq / dt = d (CE · sinω
t) / dt = ω · C · E · cos ωt = ω · C · E · s
in (ωt + π / 2).

At this time, assuming that the current flowing through the first transistor 1 is i1 and the current flowing through the third transistor 3 is i2, the respective currents are constant currents I _{E in} the first and third transistors 1 and 3. Considering that it is biased in, it becomes as follows. _{That, i1 = I E -i = I} E -
ω · C · E · sin (ωt + π / 2). Also, i
2 = _IE + i = _IE + ω · C · E · sin (ωt + π /
2).

The i1 flowing through the first transistor 1 passes through the second transistor 2 and the fourteenth transistor 14
Current flowing through the third transistor 3 as well as the current i
2 also flows to the fifteenth transistor 15 via the fourth transistor 4 (see FIG. 1).

Therefore, if the polarity of the output current io flowing through the output resistor 26 is positive in the direction of flowing into the constant voltage source 27 (see FIG. 1), this output current io is obtained as follows. That is, io = i1−i2 = −2ω · C ·
It becomes E · sin (ωt + π / 2). Letting the voltage generated across the output resistor 26 by this output current be the output voltage vo, this vo is expressed as follows. vo ＝ R ・ io ＝
-2R ・ ω ・ CE ・ sin (ωt + π / 2) = 2R ・
ω · C · E · sin (ωt−π / 2).

Therefore, the phase of the output voltage vo is always delayed by π / 2 = 90 degrees with respect to the input voltage vin. FIG. 3 shows an example of the simulation result. That is, in the figure, the input voltage vin is represented by a solid line, the output voltage vo is represented by a two-dot chain line, and the output current io is represented by a one-dot chain line. It is confirmed that the output voltage vo has a negative maximum value at the time point of, and the input voltage vin has a positive maximum value at the time of 850 ns when the output voltage vo passes zero. It was confirmed that vo has a delay phase of π / 2 with respect to the input voltage vin.

FIG. 4 is a characteristic diagram showing the test result of the change of the output phase when the frequency of the input voltage vin is changed.
It was possible to secure a phase difference of 90 degrees up to around a little over MHZ.

In the circuit of this embodiment, the phase of the output signal with respect to the input signal is theoretically always 90 degrees delayed irrespective of the frequency of the input signal, as can be understood from the above expression representing the output voltage. . However, in reality, due to the deterioration of the characteristics due to the frequency of each element including the capacitor 23, the phase difference of 90 degrees cannot be maintained above a certain frequency as shown in FIG. By using a transistor having a small phase difference, a circuit capable of ensuring a 90-degree phase difference can be realized.

Next, a second embodiment will be described with reference to FIG. The same components as those of the circuit shown in FIG. 1 are designated by the same reference numerals, detailed description thereof will be omitted, and different points will be mainly described below. In this second embodiment, the output phase is advanced 90 degrees with respect to the phase of the input signal, and most of the circuit configuration is the same as that shown in FIG. In order to proceed, the latter part of the circuit of FIG. 1 is constructed as described below.

That is, the fifteenth transistor 15 is
The collector and the base are connected to each other so that the base functions as a diode, and the base is an npn-type 16th
Transistor (denoted as “Q16” in FIG. 2) 1
6 and the fifteenth transistor 15 and the sixteenth transistor 16 form a so-called current pair. The emitters of the fifteenth and sixteenth transistors 15 and 16 are both connected to the ground line 21.

The collector of the 16th transistor 16 is connected to the collector of a 17th pnp type transistor (denoted as "Q17" in FIG. 2).
The seventeenth transistor 17 forms a current pair with a pnp-type eighteenth transistor (denoted as “Q18” in FIG. 2) 18, whose emitter is connected to the power supply line 20 and whose base is the eighteenth transistor. It is connected to the base of the transistor.

The eighteenth transistor 18 has its base and collector connected to each other so as to function as a diode. The emitter is connected to the power supply line 20, while the collector is an npn-type nineteenth transistor ( In FIG. 2, it is connected to the collector of "Q19"). Then, the nineteenth transistor 19 is
It forms a so-called current pair with the fourth transistor 4, the bases thereof are connected to each other, and the emitter of the 19th transistor 19 is connected to the power supply line 20.

The collectors of the seventeenth and sixteenth transistors 17 and 16 are connected to the output terminal 25 and one end of the output resistance (resistance value R) 26. A bias voltage Vr2 from a constant voltage source 27 is applied to the other end of 26.

Next, the operation of this configuration will be described. First, the flow of current when the input voltage vin is zero is basically the same as in the case of the first embodiment shown in FIG. That is, to explain roughly, a constant current I _E flows through the first, second and fifth transistors 1, 2, 5 and the same current is generated by the current mirror circuit formed by the second and 14th transistors 2, 14. Will also flow into the fourteenth transistor 14.

Similarly, the constant current I _E also flows through the third, fourth and sixth transistors 3, 4, 6 to cause the fourth and first transistors to flow.
The same current also flows through the nineteenth transistor 19 by the current mirror circuit formed by the nine transistors 4 and 19. The constant current I _E flowing through the 14th transistor 14 is the 15th and 16th transistors 15 and 1
The constant current I _E flowing through the nineteenth transistor 19 while flowing through the sixteenth transistor 16 by the current mirror circuit formed by
The current mirror circuit composed of 7 and 18 also flows into the 17th transistor 17. As a result, the constant current I _E does not flow through the output resistor 26 and the output terminal 25
Therefore, only the bias voltage Vr2 appears.

Next, at the input terminal 24, vin = E.sin
Assuming that an AC voltage represented by ωt is applied, i1 = I _E −ω · C · E · in the first transistor 1 as in the case of the first embodiment shown in FIG. sin (ωt +
A current represented by π / 2) and a current represented by i2 = I _E + ω · C · E · sin (ωt + π / 2) flow in the third transistor 3, respectively.

The current i1 flowing through the first transistor 1 is transmitted to the fourteenth transistor 14, the fifteenth transistor 15 and the sixteenth transistor 16 by the current mirror circuit, and the sixteenth transistor 1
A collector current of 6 is obtained. On the other hand, the third transistor 3
Similarly, the current i2 flowing through the current mirror circuit is generated by the current mirror circuit.
And to the seventeenth transistor 17,
Is the collector current of the transistor 17.

Now, comparing the flow directions of the currents i1 and i2 with the output terminal 25 as the center, as compared with the case of the circuit of the first embodiment shown in FIG. In the case of, the current i1 flows from the seventeenth transistor 17 toward the connection point of the output terminal 25, while the output terminal 25
The current i2 flows out from the connection point to the sixteenth transistor 16 and has a relationship just opposite to the directions of the currents i1 and i2 in the circuit shown in FIG.

Therefore, if the polarity of the output current io is positive in the direction of flowing into the constant voltage power source 27 (see FIG. 2), the output current io is io = i2-i1 = 2ω · C · E ·
sin (ωt + π / 2). If the voltage generated across the output resistor 26 by the output current io is the output voltage vo, the output voltage vo is vo = R · io = 2R · ω · C ·
It becomes E · sin (ωt + π / 2), which is always 90 ° in phase with the input voltage.

FIG. 5 shows a simulation result in the above-described circuit. In FIG. 5, the input voltage vin is represented by a solid line and the output voltage vo is represented by a chain double-dashed line. According to this simulation result, for example, the time 75 at which the input voltage vin becomes the negative maximum value
At 0 ns, the output voltage vo is zero, and at time 800
In ns, the input voltage vin is zero, whereas the output voltage vo has a maximum positive value, and the phase of the output voltage vo leads the input voltage vin by 90 degrees. You can check.

In any of the above-described embodiments, the type and type of transistor used are merely examples and are not limited to the types and types in the examples, and are similar to those in the above-described examples. It is needless to say that the circuit may be configured using transistors of other types and kinds as long as the operation can be obtained.

In the above-mentioned embodiment, the first current generating means in claim 1 and the first current generating circuit in claims 4 and 5 include the capacitor 23, and the first, second and fifth transistors 1, This is realized by a portion in which 2, 5 are connected in series. Further, the second current generating means in claim 1 and the second current generating circuit in claims 4 and 5 include the capacitor 23, and the third, fourth, and sixth capacitors are included.
Of the transistors 3, 4, and 6 are connected in series. Further, the voltage converting means in claim 2 and the voltage converting circuit in claim 4 are the same as the current mirror circuit formed by the second and fourteenth transistors 2 and 14 in the embodiment shown in FIG.
Of the current mirror circuit, the connection part of the fourteenth transistor 14 and the fifteenth transistor 15, and the connection part of the output resistor 26.

Further, the voltage converting means in claim 3 and the voltage converting circuit in claim 5 are the same as those in the embodiment shown in FIG.
A current mirror circuit, a fourth and nineteenth transistor 4, 19 current mirror circuit, a fifteenth and sixteenth transistor 15, 16 current mirror circuit, a seventeenth and eighteenth current mirror circuit,
It is realized by the output resistor 26.

[0060]

As described above, according to the present invention, a current whose phase is advanced by 90 degrees with respect to the input voltage is obtained, and based on this current, the phase is advanced or delayed by 90 degrees with respect to the input voltage. By configuring so that it is possible to obtain an output voltage different from the conventional one, it is possible to configure without using a so-called time constant circuit consisting of a resistor and a capacitor, so that it is possible to be affected by variations in the electrical characteristics of each component. It is possible to provide a stable and highly accurate phase shift circuit.

In particular, as in the inventions according to claims 4 and 5, by adopting a structure in which the input voltage is converted into a current through a capacitor, a current having a phase advanced by 90 degrees with respect to the input voltage is obtained. In principle, this phase is not affected by the value of the capacitor, the resistance connected to this capacitor, etc., so it is stable over a relatively wide frequency range and has a high accuracy of 90 degrees. A phase circuit can be provided. Moreover, since a stable phase can be obtained and the structure can be formed without using special parts, the IC
It is also suitable for implementation in a digitalized circuit.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a 90-degree phase shift circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a 90-degree phase shift circuit according to a second embodiment of the present invention.

FIG. 3 is a characteristic diagram showing a result of simulating a phase difference between an input voltage and an output voltage in the circuit of the first embodiment.

FIG. 4 is a characteristic diagram showing a result of simulating changes in the phase difference between the input voltage and the output voltage when the frequency of the input signal is changed in the circuit of the first embodiment.

FIG. 5 is a characteristic diagram showing a result of simulating a phase difference between an input voltage and an output voltage in the circuit of the second embodiment.

6A and 6B are circuit diagrams showing an example of a conventional phase shift circuit for delaying a 90-degree phase, wherein FIG. 6A is configured by an integrating circuit and FIG. 6B is configured by using a transistor. The circuits are respectively shown.

7A and 7B are circuit diagrams showing an example of a conventional phase shift circuit for advancing a phase by 90 degrees, wherein FIG. 7A is configured by a differentiating circuit, and FIG. 7B is configured by using a transistor. The circuits are respectively shown.

[Explanation of symbols]

1 ... first transistor 2 ... second transistor 3 ... Third transistor 4 ... Fourth transistor 14 ... Fourteenth transistor 15 ... Fifteenth transistor 23 ... Capacitor 24 ... Input terminal 25 ... Output terminal 26 ... Output resistance

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-145350 (JP, A) JP-A-7-46059 (JP, A) Fukukaihei 4-23328 (JP, U) SITTHICHAI POOKAI YAUDOM and KANOK SAMOOTRUT, A differen tial-current electronically-variable current-mirror phase-shifter, INI. ELECTRONICS, 1988, VOL. 65, NO. 1, p. 59-65 (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03H 11/16

Claims (5)

(57) [Claims] 1. A constant current flows in a non-input state, and when an input voltage is applied, a current having a difference between the constant current and a current advanced in phase by 90 degrees with respect to the input voltage is generated. And a constant current flows in a non-input state, and when an input voltage is applied, a sum of the constant current and a current that is 90 degrees in phase with respect to the input voltage. Second to generate current
Current generating means, the current generated by the first current generating means, and the second current generating means
And a voltage conversion means for generating a voltage according to a current difference from the current generated by the current generation means. 2. The voltage converting means converts a current obtained by subtracting a current generated by the second current generating means from a current generated by the first current generating means into a voltage. 90 degree phase shift circuit. 3. The voltage converting means converts a current obtained by subtracting a current generated by the first current generating means from a current generated by the second current generating means into a voltage. 90 degree phase shift circuit. 4. An input stage configured to apply an AC voltage as an input signal via a capacitor, wherein a constant current is applied in the absence of the input signal, while the input signal is applied. A first current generating circuit that generates a current having a difference between the constant current and a current flowing through the capacitor according to the input signal; and an AC voltage as an input signal is applied through the capacitor. When the input signal is applied, a constant current is applied in the absence of the input signal, and a constant current and a current flowing through the capacitor in response to the input signal A second current generating circuit for generating a current, and a second current generating circuit for generating the second current from the current generated by the first current generating circuit
A 90-degree phase shift circuit comprising: a voltage conversion circuit that reduces the current generated by the current generation circuit and converts into a voltage according to the subtraction result. 5. An input stage configured to apply an AC voltage as an input signal via a capacitor, wherein a constant current is applied in the absence of the input signal, while the input signal is applied. A first current generating circuit that generates a current having a difference between the constant current and a current flowing through the capacitor according to the input signal; and an AC voltage as an input signal is applied through the capacitor. When the input signal is applied, a constant current is applied in the absence of the input signal, and a constant current and a current flowing through the capacitor in response to the input signal A second current generating circuit for generating a current, and a first current from the current generated by the second current generating circuit
A 90-degree phase shift circuit comprising: a voltage conversion circuit that reduces the current generated by the current generation circuit and converts into a voltage according to the subtraction result.