JPH0249048B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a transistor bias circuit.

[Technical background of the invention and its problems]

Conventionally, as an example of a bias circuit whose output current does not depend on the power supply voltage, a bias circuit 80 shown in FIG. 8 has been known (JOHN WILLEY & SONS
Published by PAUL R. GRAY, ROBERT G. MEYER
Author: ANALYSIS AND DESIGN OF
ANALOG INTEGRATED CIRCUITG”,
(See p.246-p.247). The bias circuit 80 is an NPN
Transistors Q ₁ , Q ₂ , PNP transistors Q ₃ , Q ₄
have. The emitter of diode-connected transistor Q ₁ is grounded, and its base is connected to the base of transistor Q ₂ . The emitter area of transistor Q ₂ is that of transistor Q ₁
The emitter is grounded via a resistor _R1 . Also, PNP transistor Q ₃ ,
The collectors of _Q4 are both grounded to the power supply voltage _Vcc . Transistor Q ₄ is diode-connected and its base connects to the base of transistor Q ₃ . In this way, the input of the current mirror circuit constituted by transistors Q ₃ and Q ₄ , that is, the collector of transistor Q ₄ , is connected to the collector of transistor Q ₂ , and the output of the current mirror circuit, that is, the collector of transistor Q ₃ , is connected to the collector of transistor Q _1. is connected to the collector of The output of the bias circuit 80 configured in this way is
The base of the transistor _Q1 as shown in figure a
The emitter is connected to the base of the
A PNP output transistor whose base is connected to the base of transistor _Q4 and whose emitter is grounded to the power supply as shown in FIG. 8b.
It is derived from its collector via Qb.

The output current Iout of the bias circuit 80 is determined as follows. Assuming that the base current of the transistor is sufficiently smaller than the collector current, and ignoring this, the emitter currents of the transistors _Q1 to _Q4 are all equal due to the current mirror circuit constituted by the transistors _Q3 and _Q4 . Also the 8th
In figure a, output transistor Qa and transistor Q ₁
However, in FIG. 8b, since the output transistor Qb and the transistor _Q4 each constitute a current mirror circuit, the current flowing through all the transistors is ultimately equal to the output current Iout. Therefore, if we pay attention to the currents flowing through transistors Q ₁ and Q ₂ , the following equation holds true.

V _T lnI _put /I _s = V _T lnI _put /nI _s +R ₁ I _put …(1) Here, V _T =kt/q, q: electron charge, k: Boltzmann constant, T: absolute temperature, Is :Transistor Q ₁
is the reverse saturation current.

Solving equation (1), I _put = V _T l _o n / R ₁ = kT l _o n / qR ₁ ... (2) Therefore, the output current I out is proportional to the absolute temperature T, and its temperature coefficient is ∂I _put / T is ∂I _put /∂T=l _o n/R ₁・∂V _T /∂T=V _T l _o n/TR ₁ =I _pu
t /T…(3).

In this _way , the conventional bias circuit 80 has the advantage that its output current Iout does not depend on the power supply voltage, but on the other hand, its temperature coefficient ∂I _put /∂T
Since the temperature coefficient depends on the output current value, it has the disadvantage that an arbitrary temperature coefficient cannot be set independently of the output current value.

[Purpose of the invention]

The present invention has been made in view of the above conventional problems, and provides a bias circuit whose output bias voltage does not depend on the power supply voltage and whose temperature coefficient can be set independently of the bias voltage value. The purpose is to provide

[Summary of the invention]

The present invention is based on inserting a resistor _R2 into the current path of the conventional bias circuit 80 as shown in FIGS. 9A to 9D. The insertion position of the resistor R ₂ is between the collectors of transistors Q ₁ and Q ₃ , between the collectors of transistors Q ₂ and Q ₄ , between the emitter of transistor Q ₁ and the reference potential (ground terminal), or between the emitter of transistor Q ₄ and the reference potential ( power supply). At this time, the smells A, C, and D in Figure 9 are resistance.
A voltage of _{R 2 /} R ₁ V _T l _o n is generated across R 2 , and in Figure B, a voltage of R ₂ /R ₁ − _{R 2} V _T l _o n is generated across the resistor R ₂ . .

Therefore, the output voltage V in FIG. 9A
outN, that is, the voltage between the collector and ground of transistor _Q3 and the output voltage at C and D, _VputP ,
In other words, the collector power supply Vc.c of transistor _Q2 .
The voltages between _both are _equal , and Vout= _VputN = _VputP = _VBE + _R2 / _R1VTlon ...(4). Also, the output voltage V _put in FIG. 9B
(= _VputN ) becomes _Vput = _VputN = _VBE + _R2 / _{R1 -R2VTlon ... (} 5).

As mentioned above, the conventional bias circuit 80 includes a resistor R ₂
By inserting , it is possible to generate a V _BE term in the bias voltage V _put as shown in equations (4) and (5). Since V _BE /∂T takes a negative value and ∂V _T /∂T takes a positive value, it seems that ∂V _put /∂T can be set independently of the value of the output voltage V _put . ) and (5), the coefficient of the transistor base-emitter voltage V _BE is fixed at one value, so the only coefficient that can be manipulated to set the output voltage value is the coefficient of the V _T term. ,
It is still not possible to independently set the output voltage V _put and its temperature coefficient.

Therefore, in the present invention, a V _BE multiplier circuit 10 is inserted into the bias circuit shown in FIG. 9 so that KV _BE (K is an arbitrary constant) can be added to the output voltage V _put . The insertion position of this multiplier circuit 10 is a resistor.
Between the collector of the transistor on the side where R ₂ is inserted,
Alternatively, there are two ways between the collector and base of the diode-connected transistor on the side where the resistor R ₂ is inserted. Ultimately, as the bias circuit according to the present invention, eight types of bias circuits shown in FIGS. 1 and 2 can be considered based on the bias circuit shown in FIG. 9.

The output voltage V _putN of the bias circuits shown in FIG. 1 A-1 and A-2 and the output voltage V _putp of the bias circuit shown in FIG. 2 are equal, V _put = V _{put N} = V _putp = (1+K) V _BE +R ₂ /R ₁ V _T l _o n ...(6), and the output voltage V _put (=V _putN ) of the bias circuit of FIG. 1 B-1 and B-2 is V _put = V _putN = (1+K) V _BE +R ₂ /R ₁ −R ₂ V _T l _o n (7). In equations (6) and (7), the coefficient of the V _T term is replaced by A for convenience, and the temperature drift of the output voltage V _prt is calculated as follows: V _put /∂T=(1+K)∂V _BE /∂T+A・k/q …(8) becomes. Therefore, the bias circuit according to the present invention has two
By selecting appropriate values for the two variables (1+K)·A, the values of the output voltage V _put and its temperature coefficient ∂V _put t/∂T can be determined independently.

[Embodiments of the invention]

Hereinafter, specific circuit examples of the bias circuit according to the present invention will be explained using FIGS. 3 to 7. In addition,
The bias circuit shown in Figure 3 a-1 is as shown in Figure 1 A-1.
This is a specific example of the circuit, as shown in Figure 3 a-2-1 below.
a-2-2 is b-2-1 to b- shown in Fig. 1 A-2, Fig. 3 b-1 Fig. 1 B-1, Fig. 4, and Fig. 5.
2-6 is Figure 1 B-2, Figure 6 c-1 is Figure 2 C
-1, Figure 6 c-2-1, c-2-2 are Figure 2C
-2, Figure 6 d-1 is Figure 2 D-1, Figure 7 d-
2 is a specific example of the circuit shown in FIG. 2 D-2. In addition, in the following explanation, we will assume that the transistor's base-emitter voltage V _BE is a function of temperature only and does not depend on the collector current, and ignore this as the transistor's base current is sufficiently small compared to the collector current. and think about it.

First, we will begin by explaining the bias circuit shown in FIG. 3a-1. In this example, the V _BE multiplier circuit 10 is NPN
It consists of a transistor Q ₅ and resistors R ₃ and R ₄ , and resistors R ₃ and R ₄ are connected between the collector and base and between the emitter and base of the transistor Q ₅ , respectively.
is connected. Therefore, the voltage V _kBE across the resistors R ₃ and R ₄ is V _kBE = (1+R ₃ /R ₄ ) V _BE (9). Therefore, the output voltage V _put is the sum of the above equation (4) and the above V _kBE , and V _put = (1 + R ₃ / R ₄ ) V _BE + V _BE + R ₂ / R ₁ V _{T lo} n=(2+
R ₃ /R ₄ )V _BE +R ₂ /R ₁ V _{T lon} ...(10). In this way, the output voltage V _put of the bias circuit in Figure 3 a-1 has the same form as equation (6), and the two variables
By appropriately selecting R ₃ /R ₄ ·R ₂ /R ₁ l _o n , the output voltage V _put and its temperature coefficient ∂V _put /∂T can be set independently.

The bias circuit of Fig. 3 b-1 uses the same multiplier circuit as a-1, so that its output voltage V _put
is, V _put = (2 + R ₃ / R ₄ ) V _BE + R ₂ / R ₁ − R ₂ V _T l _o n …(11), which again requires two variables R ₃ /R ₄・R ₂ /R ₁ −R By appropriately selecting ₂ l _o n , the output voltage V _put and the temperature coefficient ∂V _put /∂T can be set independently.

Furthermore, in Fig. 6 c-1 and d-1, a PNP transistor is used as the transistor _Q5 constituting the multiplier circuit, and the output voltage in Fig. 6 c-1 is (10).
The output voltage in FIG. 6 d-1 is the same as (11).

Next, the bias circuit shown in FIG. 3a-2-1 will be explained. In this bias circuit, the resistor R ₂
In order to make all the current flowing into the collector current of transistor Q ₁ , a bias current of another system is supplied using _{transistor Q 6 and} resistor R ₅ to the multiplier circuit consisting of transistor Q 5 and resistors R ₃ and R ₄ . . The output voltage V _put in this example is the addition of the V _BE of the transistor Q ₆ compared to the example of a-1, and V _put = (3 + R ₃ / R ₄ ) V _BE + R ₂ / R ₁ V _T l _o n ...( 12) becomes.

The bias path shown in FIG. 6c-2-1 corresponds to the bias circuit shown in FIG. 3a-2-1 described above, and the output voltage is similarly given by equation (12).

The bias circuit in Fig. 3 a-2-2 is a-2-
This bias circuit has almost the same principle as the bias circuit of No. 1, but the functions of transistors Q ₄ and R ₄ that constituted the multiplier circuit are included in the functions of transistor Q ₁ and resistor R ₅ .

Figure 6c-2-2 is also constructed based on the same idea, and the bias voltages of both bias circuits are equal, V _put = (2 + R ₃ / R ₅ ) V _BE + R ₂ / R ₁ V _{T lo} n...(13)

The bias circuit of FIG. 4b-2-1 also supplies a bias current from the transistor _Q5 and the resistor _R5 to the multiplier circuit composed of the transistor Q5 and _the resistors _R3 and _R4 . However, it differs from FIG. 3 a-2-1 in that transistors Q ₁ , Q ₂ , and Q ₅ share a common base. The bias voltage V _put1 at this time is equal to that shown in equation (11).

Moreover, the bias circuit of FIG. 7 d-2 is
This corresponds to the bias circuit in Figure b-2-1,
The output voltage is also given by equation (11).

The bias circuit in Fig. 4 b-2-1 is shown in Fig. 4 b-2-1.
Transistor Q ₅ in the bias circuit of 2-1,
The function of the resistor _R5 is combined with the function of the transistor _Q1 and the resistor _R2 , and the bias voltage V _put1 is V _put1 = (2 + R ₂ + R ₃ / R ₄ ) V _BE + R ₂ / R ₁ - R ₂ V _{T lon} (14).

Next, the bias circuits of Fig. 4 b-2-3 and b-2-4 connect one end of the resistor _R1 in the bias circuits b-2-1 and b-2-2 of the same figure through the resistor _R2 . The structure is such that it is grounded. At this time, the bias voltage of b-2-3 is V _put1 = (2 + R ₃ / R ₄ ) V _BE + 2R ₂ / R ₁ V _{T lon} (15), and the bias voltage of b-2-4 is , _Vput1 =(2+ _R2 + _R3 / _R4 ) _{VBE + 2R2} / _{R1VTlon ...} (16).

Figure 5 b-2-5 shows transistor Q ₅ , resistor R ₃ ,
This is an example of simply combining a multiplier circuit consisting of R ₄ and an emitter follower output transistor Q ₆ .
The output voltage _{is Vput1} =(3+ _R3 / _R4 ) _VBE + _2R2 / _R1VTlon ... ₍ 17).

Figure 5 b-2-6 is an example in which m diodes connected in series are used as a multiplier circuit in b-2-5 above, and the output voltage is V _put1 (2+m)V _BE +2R ₂ /R ₁ V _T・l _o n …(18).

As mentioned above, the bias circuits shown in Figures 4, 5, and 7 can all take out their output from the emitter of transistor _Q6 , and the output voltage V _put2 at that time is greater than V _put1 in each bias circuit.
The value obtained by subtracting V _BE , that is, V _put2 = V _put − V _BE (19). Also, at this time, the output is the transistor Q ₆
Since the output is taken out through the emitter follower, the output impedance is extremely low.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide a bias circuit in which the bias voltage to be output and its warming coefficient can be set independently, and which does not depend on the power supply voltage.

[Brief explanation of drawings]

1 and 2 are circuit configuration diagrams showing the basic configuration of the bias circuit of the present invention, FIGS. 3 to 7 are specific circuit configuration diagrams of the bias circuit of the present invention based on the above basic configuration, and FIG. 8 9 is a configuration diagram of a conventional bias circuit, and FIG. 9 is a circuit configuration diagram for explaining the principle of the bias circuit of the present invention. Q ₁ , Q ₂ , Q ₃ , Q ₄ ...transistor, R ₁ , R ₂ ...
...Resistance, Vcc...Power supply voltage, GND...Grounding terminal,
10...V _BE multiplier circuit.

Claims (1)

[Claims] 1. A first circuit whose emitter is connected to a first reference potential, and whose collector and base are connected by a first line.
a transistor having the same polarity as the first transistor but having a different emitter area, the emitter being connected to the first reference potential via a first resistor,
a second transistor whose base is connected to the base of the first transistor, whose polarity is different from that of the first transistor, whose emitter is connected to a second reference potential, and whose collector is connected to the collector of the first transistor; A third transistor to be connected has the same polarity as the third transistor, has an emitter connected to the second reference potential, a base connected to the base of the third transistor, and a collector and base connected to the second reference potential. a fourth transistor connected by a line and whose collector is connected to the collector of the second transistor, the fourth transistor being between the emitter of the first transistor and a first reference potential or between the first transistor and the fourth transistor; A voltage generating means for generating a voltage multiplied by the base-emitter voltage of the transistor is connected between the collectors of the first transistor and the third transistor together with a second resistor inserted between the collectors of the first transistor and the third transistor. or between the collectors of the second transistor and the fourth transistor, or between the emitter of the fourth transistor and the second reference. The second resistor is inserted and connected somewhere between the potentials, and the voltage generating circuit has it either between the collectors of the second transistor and the fourth transistor or in the second line. A bias circuit characterized by comprising: