JPS6239548B2 - - Google Patents
Info
- Publication number
- JPS6239548B2 JPS6239548B2 JP53150328A JP15032878A JPS6239548B2 JP S6239548 B2 JPS6239548 B2 JP S6239548B2 JP 53150328 A JP53150328 A JP 53150328A JP 15032878 A JP15032878 A JP 15032878A JP S6239548 B2 JPS6239548 B2 JP S6239548B2
- Authority
- JP
- Japan
- Prior art keywords
- dielectric layer
- electrons
- holes
- mosfet
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 17
- 238000000034 method Methods 0.000 claims description 13
- 239000002923 metal particle Substances 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 1
- 230000000694 effects Effects 0.000 description 15
- 238000009826 distribution Methods 0.000 description 9
- 230000014759 maintenance of location Effects 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- 230000005684 electric field Effects 0.000 description 7
- 239000010419 fine particle Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 4
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 4
- 239000011651 chromium Substances 0.000 description 4
- 239000011882 ultra-fine particle Substances 0.000 description 4
- 239000006185 dispersion Substances 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005284 excitation Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 1
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 229910052792 caesium Inorganic materials 0.000 description 1
- TVFDJXOCXUVLDH-UHFFFAOYSA-N caesium atom Chemical compound [Cs] TVFDJXOCXUVLDH-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000005264 electron capture Effects 0.000 description 1
- IXCSERBJSXMMFS-UHFFFAOYSA-N hcl hcl Chemical compound Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052740 iodine Inorganic materials 0.000 description 1
- 239000011630 iodine Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000005865 ionizing radiation Effects 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910052701 rubidium Inorganic materials 0.000 description 1
- IGLNJRXAVVLDKE-UHFFFAOYSA-N rubidium atom Chemical compound [Rb] IGLNJRXAVVLDKE-UHFFFAOYSA-N 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
Description
【発明の詳細な説明】
本発明は二重誘電体層MOSFET不揮発性記憶
装置の製造方法に関し、特に記憶保持特性および
記憶消去特性の加善にかかわるものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a dual dielectric layer MOSFET non-volatile memory device, and in particular to improving memory retention and erasure characteristics.
二重誘電体層MOSFET不揮発性記憶装置は、
FETのゲート絶縁層が、半導体表面に形成され
た、電子ないし正孔に対する捕獲中心密度が極め
て少ない第１の誘電体層と、第１の誘電体層表面
に形成された、電子ないし正孔に対する捕獲中心
密度が極めて多い第２の誘電体層からなる二重構
造で形成されており、第１の誘電体層を通して第
２の誘電体層に注入された電子ないし正孔が、第
２の誘電体層中の捕獲中心に捕獲されることによ
る、MOSFETの閾値電圧の変化を利用するもの
である。即ち、ＮチヤンネルMOSFETの場合、
ゲート電極に、基板に対して正の電位を印加する
ことにより、Ｐ型半導体より電子が第１の誘電体
層を通つて第２の誘電体層に注入され、そこで捕
獲されることにより閾値電圧が上昇する（これを
書き込み動作と称する）。また、第２の誘電体層
中に捕獲された電子は、ゲート電極に、基板に対
して負の電位を印加することにより、第１の誘電
体層を通つてＰ型半導体に放出され、閾値電圧は
下降する（これを消去動作と称する）。（Ｐチヤン
ネルMOSFETの場合は、Ｐ型半導体がＮ型半導
体に、電子が正孔に、またゲート電極の基板に対
する電位が逆になるだけで、正孔の注入、放出と
閾電圧の上昇下降の関係は変らない。）したがつ
て、二重誘電体層MOSFET不揮発性記憶装置は
電気的に書き込み、消去が可能であり、特に紫外
線消去を要する浮遊ゲートMOSFET不揮発性記
憶装置に比較して、ビツト単位ないしワード単位
の書き換えが可能であるという利点を有すること
からEAROM（Electrically Alternative Read
Only Memory…電気的に書き換えが可能な読み
出し専用記憶装置）として用いられる。 Double dielectric layer MOSFET non-volatile memory device
The gate insulating layer of the FET consists of a first dielectric layer formed on the semiconductor surface with extremely low trapping center density for electrons or holes, and a first dielectric layer formed on the surface of the first dielectric layer that traps electrons or holes at a very low density. It is formed of a double structure consisting of a second dielectric layer with extremely high trapping center density, and electrons or holes injected into the second dielectric layer through the first dielectric layer are absorbed into the second dielectric layer. This utilizes the change in the threshold voltage of the MOSFET caused by capture at the capture center in the body layer. In other words, in the case of N-channel MOSFET,
By applying a positive potential to the gate electrode with respect to the substrate, electrons are injected from the P-type semiconductor into the second dielectric layer through the first dielectric layer and captured there, thereby increasing the threshold voltage. increases (this is called a write operation). Furthermore, by applying a negative potential with respect to the substrate to the gate electrode, the electrons captured in the second dielectric layer are emitted to the P-type semiconductor through the first dielectric layer, and the threshold value is The voltage drops (this is called an erase operation). (In the case of a P-channel MOSFET, a P-type semiconductor becomes an N-type semiconductor, electrons become holes, and the potential of the gate electrode relative to the substrate is simply reversed to control the injection and release of holes and the rise and fall of the threshold voltage. (The relationship remains the same.) Therefore, dual dielectric layer MOSFET non-volatile storage devices can be electrically written and erased, especially compared to floating gate MOSFET non-volatile storage devices that require ultraviolet erasure. EAROM (Electrically Alternative Read) has the advantage of being able to rewrite unit or word units.
Only Memory: Used as an electrically rewritable read-only storage device).
二重誘電体層MOSFET不揮発性記憶装置の書
き込み特性は、ゲート電極に印加される規定の電
圧および幅をもつた書き込みパルスによつて、第
２の誘電体層に注入される電子または正孔の量に
よつて定まり、消去特性はゲート電極に印加され
る規定の電圧および幅をもつた消去パルスによ
る、第２の誘電体層中に捕獲されている電子また
は正孔の放出量によつて定まる。また、記憶保持
特性は第２の誘電体層中に捕獲されている電子ま
たは正孔の量の自然減少率によつて定まる。ここ
で、自然減の原因としては、捕獲されている電子
または正孔によつて生じる電界による捕獲中心か
らの放出、熱的励起、電離放射線による励起等が
あり、捕獲中心から放出された電子ないし正孔
は、第１の誘電体層を通つて半導体に流れるか、
あるいは第２の誘電体層中の空の捕獲中心間での
ホツピング伝導によりゲート電極に流れる。 The write characteristics of a double dielectric layer MOSFET nonvolatile memory device are determined by the number of electrons or holes injected into the second dielectric layer by a write pulse of a specified voltage and width applied to the gate electrode. The erase characteristic is determined by the amount of electrons or holes trapped in the second dielectric layer released by an erase pulse having a specified voltage and width applied to the gate electrode. . Further, the memory retention characteristics are determined by the natural reduction rate of the amount of electrons or holes captured in the second dielectric layer. Here, the causes of natural attrition include emission from the capture center due to the electric field generated by the captured electrons or holes, thermal excitation, excitation by ionizing radiation, etc. The holes flow into the semiconductor through the first dielectric layer, or
Alternatively, it flows to the gate electrode by hopping conduction between empty trap centers in the second dielectric layer.
ところで、二重誘電体層MOSFET不揮発性記
憶装置においては、第１の誘電体層を電子あるい
は正孔が通り抜けるには２種類のモードがある。
１つは、第１の誘電体層の厚さが20Å程度の場合
で、電子あるいは正孔は直接トンネル効果によつ
て通り抜けるモード。今１つは、第１の誘電体層
の厚さが50〜70Å程度の場合で、電子あるいは正
孔は、フオーラー ノルドハイン（Fowler−
Nordheim）トンネル効果によつて通り抜けるモ
ード。直接トンネル効果を用いる場合（即ち、第
１の誘電体層の厚さが20Å程度の場合）、
MOSFETの閾値電圧を充分上昇させるにたるだ
けの電子あるいは正孔を第２の誘電体層に注入す
ると、第１の誘電体層には直接トンネル効果が生
じるに充分な電界が発生し、したがつて第２の誘
電体層中に注入された電子あるいは正孔は再び半
導体中に放出されてしまう。即ち、記憶保持特性
が良くない。特に、直接トンネル効果による注入
された電荷の再放出は、正孔よりも有効質量の小
さい電子に関して顕著であるため、高速動作が可
能なＮチヤンネルMOSFET不揮発性記憶装置に
は直接トンネル効果モードは適用できないという
難点がある。 By the way, in a double dielectric layer MOSFET nonvolatile memory device, there are two types of modes in which electrons or holes pass through the first dielectric layer.
One mode is when the thickness of the first dielectric layer is approximately 20 Å, in which electrons or holes pass through by direct tunneling. The other case is when the thickness of the first dielectric layer is about 50 to 70 Å, and the electrons or holes are
Nordheim) A mode of passing through by means of a tunnel effect. When using direct tunneling effect (i.e., when the thickness of the first dielectric layer is about 20 Å),
When enough electrons or holes are injected into the second dielectric layer to sufficiently increase the threshold voltage of the MOSFET, an electric field is generated in the first dielectric layer sufficient to cause direct tunneling. The electrons or holes injected into the second dielectric layer are then emitted into the semiconductor again. That is, the memory retention characteristics are not good. In particular, the re-emission of charges injected by the direct tunnel effect is remarkable for electrons, which have a smaller effective mass than holes, so the direct tunnel effect mode is not applicable to N-channel MOSFET nonvolatile memory devices capable of high-speed operation. The problem is that it cannot be done.
一方、フオーラー ノルドハイン（Fowler−
Nordheim）トンネル効果モードを用いる場合
（即ち第１の誘電体層の厚さが50〜70Å程度の場
合）、第２の誘電体層中に注入された電子あるい
は正孔自体による電界は第１の誘電体層を電子あ
るいは正孔が通り抜けることができるほど高くは
ならない。したがつて、ＮチヤンネルMOSFET
に適用することが可能である。しかしながら、第
２の誘電体層中の電子あるいは正孔に対する捕獲
中心は、第２の誘電体層内で均一に分布している
ことから、捕獲された電子あるいは正孔の密度分
布は、第１図に示すように第１の誘電体層と第２
の誘電体層との界面よりゲート電極に近いところ
に最大値を有する。したがつて、捕獲された電子
あるいは正孔の密度分布の最大値が第１の誘電体
層と第２の誘電体層との界面にある場合に比較す
ると、ゲート電極に印加すべき消去パルスの電圧
を高くするか、あるいは幅を広くしなければなら
ない。換言すれば、フオーラー ノルドハイン
（Fowler−Nordheim）トンネル効果モードを用
いた場合、消去特性が悪化する。さらに、第２の
誘電体層中に捕獲された電子あるいは正孔自体に
よる電界は第２の誘電体層中にも形成されるか
ら、捕獲された電子あるいは正孔はこの電界によ
つて第２の誘電体層中の空の捕獲中心間でホツピ
ング伝導を行ないゲート電極に流れてしまう。即
ち、フオーラー ノルドハイン（Fowler−
Nordheim）トンネル効果モードを用いた場合で
も、直接トンネル効果モードを用いた場合に比較
して、記憶保持特性が大きく改善されるわけでは
ない。 On the other hand, Fowler-Nordhain
Nordheim) When using the tunnel effect mode (i.e., when the thickness of the first dielectric layer is approximately 50 to 70 Å), the electric field due to the electrons or holes themselves injected into the second dielectric layer is equal to that of the first dielectric layer. It is not high enough to allow electrons or holes to pass through the dielectric layer. Therefore, N-channel MOSFET
It is possible to apply it to However, since the trapping centers for electrons or holes in the second dielectric layer are uniformly distributed within the second dielectric layer, the density distribution of the trapped electrons or holes is similar to that of the first dielectric layer. As shown in the figure, the first dielectric layer and the second dielectric layer
It has a maximum value closer to the gate electrode than the interface with the dielectric layer. Therefore, compared to the case where the maximum value of the density distribution of trapped electrons or holes is at the interface between the first dielectric layer and the second dielectric layer, the erase pulse to be applied to the gate electrode is The voltage must be increased or the width must be increased. In other words, when the Fowler-Nordheim tunneling mode is used, the erasure characteristics deteriorate. Furthermore, since the electric field caused by the electrons or holes themselves captured in the second dielectric layer is also formed in the second dielectric layer, the captured electrons or holes are transferred to the second dielectric layer by this electric field. Hopping conduction occurs between empty trap centers in the dielectric layer and flows to the gate electrode. That is, Fowler-Nordhain
(Nordheim) Even when the tunnel effect mode is used, memory retention properties are not significantly improved compared to when the direct tunnel effect mode is used.
Fowler−Nordheimトンネル効果モードを用い
た二重誘電体層MOSFET不揮発性記憶装置の消
去特性を改善する方法として、第１の誘電体層と
第２の誘電体層との界面に金属の極微粒子を分散
させる方法が提案されている。この金属極微粒子
は各々が電子あるいは正孔に対する捕獲中心とし
て働らき、かつその捕獲断面積が第２の誘電体層
中の電子あるいは正孔に対する捕獲中心の捕獲断
面積より大きいことから、第２の誘電体層中で捕
獲された電子あるいは正孔の密度分布の最大値は
第２図に示すように、第１の誘電体層と第２の誘
電体層との界面に存在し、したがつて消去特性は
金属微粒子が存在しない場合に比較して改善され
る。しかしながら、捕獲された電子あるいは正孔
自体による電界に起因する、捕獲された電子ある
いは正孔のホツピング伝導による自然減少には変
化がないから、記憶保持特性は金属微粒子の存在
しない場合と変らない。 As a method to improve the erase characteristics of a double dielectric layer MOSFET nonvolatile memory device using the Fowler-Nordheim tunnel effect mode, ultrafine metal particles are added to the interface between the first dielectric layer and the second dielectric layer. A method of dispersion has been proposed. These ultrafine metal particles each act as a trapping center for electrons or holes, and their trapping cross section is larger than the trapping cross section of the trapping center for electrons or holes in the second dielectric layer. As shown in Figure 2, the maximum value of the density distribution of electrons or holes captured in the dielectric layer exists at the interface between the first dielectric layer and the second dielectric layer, and Therefore, the erasing characteristics are improved compared to the case where metal fine particles are not present. However, since there is no change in the natural reduction of trapped electrons or holes due to hopping conduction caused by the electric field caused by the trapped electrons or holes themselves, the memory retention characteristics are the same as in the case where metal fine particles are not present.
本発明の目的は、前記、従来の二重誘電体層
MOSFET不揮発性記憶装置の難点を排し、金属
微粒子分散型Fowler−Nordheimトンネル効果モ
ード動作二重誘電体層MOSFET不揮発性記憶装
置のＮチヤンネルMOSFETへの適用可能性及び
良好な消去特性を維持し、かつ記憶保持特性を改
善した半導体不揮発性記憶装置の製造方法を提供
することにある。 The object of the present invention is to solve the above-mentioned conventional double dielectric layer
Eliminating the drawbacks of MOSFET non-volatile memory devices, maintaining the applicability of metal particle dispersed Fowler-Nordheim tunnel effect mode operation double dielectric layer MOSFET non-volatile memory devices to N-channel MOSFETs and good erase characteristics; Another object of the present invention is to provide a method for manufacturing a semiconductor nonvolatile memory device with improved memory retention characteristics.
本発明にしたがえば、MOS型FETのゲート絶
縁層の形成方法が、半導体表面に第１の誘電体層
を形成した後、第１の誘電体層表面に金属の極微
粒子群を付着せしめ、さらに、第１の誘電体層表
面および金属の極微粒子群とを覆うように第２の
誘電体層を形成するとともに、第２の誘電体層の
形成期間中ないし形成後に第２の誘電体層中に不
純物を添加することにより、第２の誘電体層中に
存在する電子あるいは正孔に対する捕獲中心密度
を減少せしめるものであることを特徴とする半導
体不揮発性記憶装置の製造方法が得られる。 According to the present invention, a method for forming a gate insulating layer of a MOS FET includes forming a first dielectric layer on a semiconductor surface, and then attaching a group of ultrafine metal particles to the surface of the first dielectric layer, Further, a second dielectric layer is formed to cover the surface of the first dielectric layer and the metal ultrafine particle group, and the second dielectric layer is formed during or after the formation of the second dielectric layer. A method for manufacturing a semiconductor nonvolatile memory device is obtained, characterized in that the density of trapping centers for electrons or holes existing in the second dielectric layer is reduced by adding impurities therein.
以下、本発明に関し、Ｎチヤンネル
SiMOSFETのゲート絶縁層の第１の誘電体層を
熱酸化SiO2層、第２の誘電体層をCVDSi3N4層、
極微粒子金属をＷとした金属微粒子分散型
Fowler−Nordheimトンネル効果モード二重誘電
体層MOSFET不揮発性記憶装置を例に挙げて述
べる。 Below, regarding the present invention, N channel
The first dielectric layer of the SiMOSFET gate insulating layer is thermally oxidized SiO 2 layers, the second dielectric layer is CVDSi 3 N 4 layers,
Metal fine particle dispersion type using ultrafine metal as W
A Fowler-Nordheim tunnel effect mode double dielectric layer MOSFET nonvolatile memory device will be described as an example.
ＮチヤンネルMOSFET不揮発性記憶装置の金
属微粒子分散型二重誘電体層ゲート絶縁層の製造
方法は、次の通りである。Ｐ型Si基板上のSiO2層
のMOSゲートとすべき部分をホトレジスト工程
によつて取り除き、露出したＰ型Si表面を不活性
気体で希釈された乾燥酸素雰囲気で加熱すること
により50〜70Å程度の熱酸化SiO2膜を第１の誘
電体層として形成する。次に真空蒸着法によりタ
ングステンＷの極微粒子群を基板表面全面に約
0.5〜２×1015原子／cm2の割合で付着せしめさら
にCVD法により450〜480Å程度のSi3N4膜を第２
の誘電体層として基板表面全面に被着する。次に
ホトレジスト工程によつて、MOSゲート部分を
覆うに必要にして十分な部分のみを残してSi3N4
膜およびタングステンＷの極微粒子群を取り除
く。このようにして得られた二重誘電体層ゲート
絶縁層を有する不揮発性記憶装置は、記憶保持特
性を除いては期待される性能を充分有するもので
ある。ところで、Si3N4膜中に存在する電子に対
する捕獲中心は、負の電荷に親和力を有するアク
セブタ型であるから、Si3N4膜形成期間中ないし
形成後に、負に帯電しやすい物質（例えばクロム
Cl）をSi3N4膜中に添加すれば、アクセブタ型捕
獲中心にはクロムCl-イオンが捕獲される結果、
Si3N4膜中の電子に対する捕獲中心の密度は大き
く減少する。したがつて、捕獲された電子自体に
よつて形成される電界にしたがつて生じるホツピ
ング伝導も、空の電子捕獲中心が極めて少ないた
め、非常に小さいものとなる。即ち、記憶保持特
性は大きく改善されたものとなる。従来方法によ
るものでは、100〜300時間程度で閾電圧が大きく
低下しはじめるが、本発明の方法によるもので
は、10倍以上の時間を経過したものでも閾電圧の
低下はみられていない。さらに本発明の今一つの
効果として、捕獲された電子の密度分布が第３図
に示すようにSiO2−Si3N4界面およびその近傍に
限定される結果、第２図に示したように、第２の
誘電体層の表面近くまで捕獲された電子あるいは
正孔の密度分布が尾をひいている従来方法で製造
された金属微粒子分散型二重誘電体層不揮発性記
憶装置に比較してさらに消去特性が改善されてい
る。 A method for manufacturing a metal fine particle dispersed double dielectric layer gate insulating layer of an N-channel MOSFET nonvolatile memory device is as follows. The portion of the SiO 2 layer on the P-type Si substrate that should be used as the MOS gate is removed by a photoresist process, and the exposed P-type Si surface is heated in a dry oxygen atmosphere diluted with an inert gas to form a MOS gate of about 50 to 70 Å. A thermally oxidized SiO 2 film is formed as the first dielectric layer. Next, ultrafine particles of tungsten W are applied to the entire surface of the substrate using a vacuum evaporation method.
A second Si 3 N 4 film with a thickness of about 450 to 480 Å is deposited at a rate of 0.5 to 2×10 15 atoms/cm 2 using the CVD method.
The dielectric layer is deposited over the entire surface of the substrate. Next, through a photoresist process, Si 3 N 4 is removed, leaving only the necessary and sufficient area to cover the MOS gate area.
The film and the ultrafine particles of tungsten W are removed. The nonvolatile memory device having the double dielectric gate insulating layer thus obtained has sufficient expected performance except for memory retention characteristics. Incidentally, the trapping center for electrons present in the Si 3 N 4 film is an acceptor type that has an affinity for negative charges. chromium
If Cl) is added to the Si 3 N 4 film, chromium Cl - ions are captured in the acceptor type capture center, resulting in
The density of trapping centers for electrons in the Si 3 N 4 film is greatly reduced. Therefore, the hopping conduction that occurs in accordance with the electric field formed by the captured electrons itself is also very small because there are very few empty electron capture centers. In other words, the memory retention characteristics are greatly improved. With the conventional method, the threshold voltage begins to decrease significantly after about 100 to 300 hours, but with the method of the present invention, no decrease in threshold voltage is observed even after 10 times or more of the time. Furthermore, as another effect of the present invention, as shown in FIG. 2, the density distribution of captured electrons is limited to the SiO 2 -Si 3 N 4 interface and its vicinity, as shown in FIG. Compared to a metal fine particle dispersed double dielectric layer nonvolatile memory device manufactured by a conventional method in which the density distribution of trapped electrons or holes tails close to the surface of the second dielectric layer, Erasing characteristics are improved.
Si3N4膜中へのClの添加は、Si3N4膜のCVD成長
時に微量の塩酸HClを流すか、あるいはSi3N4膜
形成後イオン注入法を用いてクロムCl-イオンを
注入することによつて得られる。 Cl can be added into the Si 3 N 4 film by flowing a small amount of hydrochloric acid HCl during CVD growth of the Si 3 N 4 film, or by implanting chromium Cl - ions using an ion implantation method after the Si 3 N 4 film is formed. obtained by doing.
以上説明したように、本発明にしたがえば高速
動作が可能な二重誘電体層Ｎチヤンネル
MOSFET不揮発性記憶装置の記憶保持特性を大
きく改善することが可能となり、さらに消去特性
をも改善することが可能である。 As explained above, according to the present invention, a double dielectric layer N-channel capable of high-speed operation is provided.
It becomes possible to greatly improve the memory retention characteristics of a MOSFET nonvolatile memory device, and it is also possible to improve the erase characteristics.
なお、以上の説明においては、第２の誘電体層
をSi3N4膜に、極微粒子金属をタングステンＷ
に、第２の誘電体層に添加する不純物をクロム
Clに、限つたが、上記材料に限定する必要はな
い。たとえば、第２の誘電体層としてAl2O3膜を
極微粒子金属として、モリブデンMo、タンタル
Ta、イリジウムIrを不純物として臭素Br、ヨウ
素Ｉを用いて本発明を実施しても全く同様な効果
が得られる。また、ＰチヤンネルMOSFETに本
発明を実施する場合、第２の誘電体層に添加する
不純物としてはセシウムCs、ルビジウムRbを用
いれば同様な効果が得られる。 In the above explanation, the second dielectric layer is a Si 3 N 4 film, and the ultrafine particle metal is tungsten W.
The impurity added to the second dielectric layer is chromium.
Although the material is limited to Cl, there is no need to limit it to the above materials. For example, an Al 2 O 3 film is used as the second dielectric layer, and molybdenum Mo and tantalum are used as the ultrafine metal particles.
Exactly the same effect can be obtained even if the present invention is carried out using Ta and iridium Ir as impurities and bromine Br and iodine I. Further, when the present invention is applied to a P-channel MOSFET, the same effect can be obtained by using cesium Cs or rubidium Rb as the impurity added to the second dielectric layer.
第１図は、単純な二重誘電体層MOSFET半導
体記憶装置の第２の誘電体層中に捕獲された電子
あるいは正孔の密度分布を示す図、第２図は、従
来の金属微粒子分散型Fowler−Nordheimトンネ
ル効果モード動作二重誘電体層MOSFET半導体
記憶装置の第２の誘電体層中に捕獲された電子あ
るいは正孔の密度分布を示す図、第３図は、本発
明を実施した金属微粒子分散型Fowler−
Nordheimトンネル効果モード動作二重誘電体層
ＮチヤンネルMOSFET半導体記憶装置のSi3N4膜
（第２の誘電体層）中の捕獲された電子の密度分
布を示す図である。
Figure 1 shows the density distribution of electrons or holes captured in the second dielectric layer of a simple double dielectric layer MOSFET semiconductor memory device, and Figure 2 shows the density distribution of electrons or holes captured in the second dielectric layer of a simple double dielectric layer MOSFET semiconductor memory device. A diagram showing the density distribution of electrons or holes trapped in the second dielectric layer of a double dielectric layer MOSFET semiconductor memory device operating in the Fowler-Nordheim tunnel effect mode. Fine particle dispersion type Fowler−
FIG. 3 is a diagram showing the density distribution of captured electrons in the Si 3 N 4 film (second dielectric layer) of a dual dielectric layer N-channel MOSFET semiconductor memory device operating in Nordheim tunnel effect mode.
Claims (1)
成方法が半導体表面に第１の誘電体層を形成した
後、第１の誘電体層表面に金属の極微粒子群を付
着せしめ、さらに、第１の誘電体層表面および金
属の極微粒子群とを覆うように第２の誘電体層を
形成するとともに、第２の誘電体層の形成期間中
ないし形成後に第２の誘電体層中に不純物を添加
することにより、第２の誘電体層中に存在する電
子あるいは正孔に対する捕獲中心密度を減少せし
めるものであることを特徴とする半導体不揮発性
記憶装置の製造方法。1. A method for forming a gate insulating layer of an insulated gate type semiconductor device includes forming a first dielectric layer on a semiconductor surface, then attaching a group of ultrafine metal particles to the surface of the first dielectric layer, and then depositing a group of ultrafine metal particles on the surface of the first dielectric layer. Forming a second dielectric layer so as to cover the surface of the dielectric layer and the group of ultrafine metal particles, and doping impurities into the second dielectric layer during or after the formation of the second dielectric layer. A method for manufacturing a semiconductor nonvolatile memory device, characterized in that the density of trapping centers for electrons or holes existing in the second dielectric layer is reduced by doing so.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15032878A JPS5575268A (en) | 1978-12-04 | 1978-12-04 | Manufacturing method of nonvolatile semiconductor memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15032878A JPS5575268A (en) | 1978-12-04 | 1978-12-04 | Manufacturing method of nonvolatile semiconductor memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5575268A JPS5575268A (en) | 1980-06-06 |
| JPS6239548B2 true JPS6239548B2 (en) | 1987-08-24 |
Family
ID=15494608
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15032878A Granted JPS5575268A (en) | 1978-12-04 | 1978-12-04 | Manufacturing method of nonvolatile semiconductor memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5575268A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4917981A (en) * | 1972-06-07 | 1974-02-16 |
-
1978
- 1978-12-04 JP JP15032878A patent/JPS5575268A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4917981A (en) * | 1972-06-07 | 1974-02-16 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5575268A (en) | 1980-06-06 |
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