JPS6238595A - Mos semiconductor memory circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption by providing a latch circuit temporarily holding an output signal in the state where the 2nd switch is turned on based on a clock signal and connecting the 1st and 2nd switches to the 2nd signal line. CONSTITUTION:When address signals AD1-ADF change to cause the clock signal phi at a level H, MOSQA1-MOSQAM and QB1-QBN are turned on. When the clock signal phi comes to a level L after a certain period, the MOSQA 1-MOSQAM and the QB1-QBN are turned off, and a current does not flow to loads MOSQL1-MOSQLM and QPL-PQN. When the clock signal phi comes to a level L, reading action is not prevented, because data is held while a memory circuit 14 is reading data on bit lines O1-ON at a level H. Thus a power source current flows only when the address signal changes, and does not flow in other cases, whereby power consumption can be substantially reduced.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to MOS semiconductor storage devices such as read-only memories (hereinafter referred to as ROM) and programmable logic arrays (hereinafter referred to as PLA) using MOS transistors. It is something.

(Prior art) Conventionally, as a technology in this field,
There was one described in Publication No. 898. The configuration will be explained below using figures.

FIG. 2 is a circuit diagram showing an example of the configuration of a PLA, which is a conventional MO3 semiconductor memory circuit. This memory circuit is
AND) configuration address decoder 1 and +7 (oR)
4fi& memory cell matrix 2, both of which are constituted by ROM.

Address decoder 1 has multiple address input lines (first
signal line) Al to AL and word line (second signal line)
Enhancement type MOS transistors (hereinafter referred to as MOS) Q11 to QL2 whose sources are connected to the word lines W1 to WN, whose drains are connected to ground potential, and whose gates are connected to the address input lines Al to AL, respectively. It is equipped with a depletion type load MOSQL1-QLM whose gate and drain are connected to the word lines 1111 to 111M, respectively, to the power supply voltage VDD, and a coded address signal (input signal) input to the address input lines A1 to AL. Decipher ADI~ADF.

This is a circuit that selects one of the word lines W1 to 1111M. Note that the address input lines AI, A3. ..., A(L-
1) and A2. A4. ..., the inverters INI to IN (L-1) connected between the address signal A[]
l-A[lF is inverted and address input line A2. A4.・
..., is given to AL.

The memory cell matrix 2 is a circuit that stores MXN bits of information, and has a plurality of bit lines (second signal lines) 01 to 0 arranged to intersect with the word lines 1 to .
N, the enhancement type MO5Q old model whose source is connected to the bit line 01 to ON, the drain is connected to the ground potential, and the gate is connected to the word line W1 to WN, respectively, and the source is connected to the power supply voltage VDD, and the gate and drain are connected to the bit line Depression-type loads connected to 01 to ON, respectively! It is equipped with tO3QPL~QPN. The stored contents (N-bit information) on word lines 1-WM selected by address decoder 1 are read from bit lines 01-ON and output as output signals DI-DN.

Next, the operation will be explained.

If MOsQM 11 in memory cell matrix 2
.

Assume that data is written to QMIM, 0M21.0MN2, and 0MN3.

Address signal ADI-ADF is input to address input lines A1 to AL of address decoder 1, and when MOSQII is turned off and only word line W1 is selected, this word line Wl is set to "H" level by power supply voltage V[lD. ft'
), MOS to which other word lines W2 to -N are connected
becomes °゛L” level.Then, the word line -1
Only MOSQMII, 0M21 connected to turns on,
Since the other MOSQNIM, 0M22, 0MN2, 0MN3 are turned off, the bit lines 01, 02 are MOSQMII,
0M2L turns “L” level other bit lines 03~ON
is set to the ``H'' level by the power supply voltage VDD. Therefore, the read data on the bit lines 01 to ON are outputted as output signals D1 to DN.

(Problems to be Solved by the Invention) However, in the MOS semiconductor memory device with the above configuration,
During a read operation, current continues to flow through the loads MOSQL2 to QLN connected to the unselected word lines w2 to 11M and the loads MOSQPI and QP2 connected to the selected bit lines 01 and 02, resulting in large power consumption. There was a problem with that.

The present invention solves the problems that the prior art had, such as inputting an address from one address to the next! The object of the present invention is to provide a MOS semiconductor memory device that solves the problem of large power consumption during a read operation until it goes low.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a plurality of first signal lines to which input signals are applied, and a plurality of first signal lines arranged to intersect with the first signal lines. a plurality of second signal lines to which a power supply voltage is applied; and a plurality of MOSs connected by VC to the intersection of the first and second signal lines; In a MOS semiconductor memory device that selects a signal line and outputs an output signal from the second signal line,
Detects the change in the input signal and detects the positive value for a certain period of time.

a clock signal generation circuit that generates a pair of negative clock signals φ and "φ-; first and second switches that turn on and off the power supply voltage and output signal based on the clock signal φ or T; a latch circuit that temporarily holds the output signal before the second switch is turned off based on the signal φ or φ-;
A switch is connected to the second signal line.

(Function) According to the present invention, since the semiconductor memory device is configured as described above, the first and second switches are turned on by the clock signals φ and T generated only when the address signal changes. Otherwise, it is in the off state. The latch circuit operates to hold the output signal before the second switch off state.

This allows the power supply current to reach the second level only when the address signal changes.
At other times, the power supply current does not flow to the second signal line, making it possible to reduce current consumption. Therefore, the above problem can be eliminated.

(Example) FIG. 1 is a υ1 path diagram of PLA showing a first example of the present invention. Note that the same elements as those in FIG. 2 are given the same reference numerals.

The difference between this embodiment and the conventional one shown in FIG. 2 is that AsD
An enhancement type N-channel MOS (il switch) QAI-QAM is added to the address decode 11 of the configuration, and enhancement type N-channel MOS (first switches) QBI to QBN are added to the memory cell matrix 12 of the OR configuration. , and the clock signal φ
, a clock signal generation circuit 13 that generates T, and a memory circuit 1
4.

That is, each MOSQA in the address decoder 11
1~QAM, whose source is each load MO9QL 1~
The drain of QLH is connected to each word line (second
The signal lines W1 to 111M are connected to each other, and function as a switch that turns on and off between the source and drain in response to a clock signal φ applied to the gate thereof.

Each MO8QB 1~ in the memory cell matrix 12
The QBN has its source connected to each load 110sQP 1-Q
The drain of PN is connected to each bit line (second signal line) 01 to ON, respectively, and functions as a switch that turns on and off between the source and drain in response to a clock signal φ applied to its gate.

The clock signal generation circuit 13 is a circuit that detects a change in at least one of the address signals ADI to ADF input to the address decoder 11 and generates a pair of positive and negative clock signals φ and T having a predetermined pulse width. It is. This clock signal generation circuit 13.

A plurality of inverters IN11. lNl2~INFI, l
NF2. and exclusive or game) XORl
A plurality of signal delay circuits consisting of NX0RF and a NOR gate NO that takes the NOR of the outputs of these signal delay circuits.
A positive clock signal φ is output from the NOR gate, and a negative clock signal T is output from the inverter INF.

Further, the memory circuit 14 is a circuit that temporarily holds read data on each bit line 01 to ON, and stores data on each bit line 01 to ON.
A plurality of second switches connected to ON and turned on and off by clock signal φ, and holding data on each bit line 01 to ON based on clock signal 3-, output signal D.
It is composed of a plurality of latch circuits that send out i-DN. Here, the 6th first switch is composed of enhancement type xosc+ci~QCN, its source is connected to the bit line O1~ON, and the source and drain are turned on and off by the positive clock signal given to the gate. controlled. Each latch circuit has an input terminal of each MOSQG
MOS inverters Tll to TIN connected to the drains of 1 to QCN, and each MOS inverter Tl1 whose input terminal is
- Connected to the output terminal of TIN and output signal D1 from the output terminal
MOS inverters 721 to 72N that send out ON, and enhancement type MOSQDs 1 to Q whose sources are connected to the drains of each MOSQCI to QC'N and whose drains are connected to the output terminals of each MOS inverters 721 to 72N, respectively.
It is composed of DN. Each MOSQD 1-QDN
The source and drain are turned on and off by the clock signal T given to its gate, and when it is turned on, it forms a closed loop with the inverter connected in parallel to the source and drain, temporarily holding the data on the bit lines 01 to ON. do.

In FIG. 1, IWI is the current flowing through the word line W1, VWI is the potential of the word line W1, and 101 is the bit line 01.
The current flowing through VOI is the potential of bit line 01.

The operation of the PLA configured as described above will be explained with reference to the signal waveform diagram in FIG.

First, when the address signals ADI to ADF change from "L" level (20) to H" level (=VDD), the clock signal generation circuit 13 generates clock signals φ, ゛φ− (however, φ=VDD.

T=O) is output, MOSQA 1 to QAM, QBI
~QBN.

QC1 to QCN are turned on. Then, the power supply voltage vDD is applied to the word lines Wl~ through the loads MOSQL1~QLN.
It is applied to WM as well as to the focus lines OI-ON via loads MO5QPI-QPN.

In the address decoder 11, if address input iA
1. Only AL is at “H” level, and other addresses are not
Assuming that A2 to A (L-1) are at "L" level, MOSQI 1. connected to address input lines AI and AL. Q
Only L3, QL1, and QL2 are turned on, and MOSQ22 and the like connected to other address input lines A2 to A (L-1) are turned off. Then, the enemy 1 of the word lines Wl to WM
Only the potential VWI of word lines becomes "L" level (=O), current IWI flows thereto, and the other word lines W2 to WM become "H" level.
level = VDD). In this way, the address decoder 11 receives the input address signals ADI~A.
The word line Wt is selected by decoding the DF, and the selected signal is transmitted to the RAM memory cell matrix 12.

In the memory cell matrix 12, MOSQMIM, Q
Since only M21 is turned off and other MOSQM LM etc. are turned on, the potentials VOI etc. of bit lines 01 and 02 are set to "H" level (=
VDD), and the current IOl etc. flowing therein become zero. The voltages on the other bit lines 03 to ON are at the "L It level. The data on these bit lines 01 to ON are input to the memory circuit 14.

Next, after a certain period of time has elapsed, the clock signal φ goes to L” level (=0), and its inverted signal T goes to “H” level (=vDD
)tonal and IIOsQAI-QAM, QBI ~QB
N, QCI to QGN are turned off, and MOSQD 1
~QDN turns on. Then, the read data on the bit lines 01-ON inputted to the memory circuit 14 is transferred to the inverters Tll-TIN, T21-72N and MOSQDs 1-
The output signal D1 is held by a latch circuit consisting of Q[lN.
~Continues to be output as ON.

Thereafter, when the address signals ADI-ADF change from the "H" level to the "L" level, the next read operation is executed in substantially the same manner as described above.

In this embodiment, when the address signals AOL to ADF change and the clock signal φ is at the "H" level, the MOSQ
A 1~QAIII, QBI NQBN are turned on, but
When the clock signal φ reaches the "L" level after a certain period of time has elapsed, MOSQA1 to QAM and QBI to QBN are turned off and no current flows to the loads MO3QL1 to QLM and QP1 to QPH, resulting in a significant reduction in power consumption. Further, when the clock signal φ goes to the 'L' level, the data on the bit lines O1 to ON at the 'H' level is held by the storage circuit 14 during the reading period, so that the reading operation is not hindered.

FIG. 4 is a circuit diagram of a ROM device showing a second embodiment of the present invention.

The difference between this ROM device and the one in FIG. 1 is that a memory cell matrix 2 is used instead of the address decoder 11 in FIG.
2, and the memory circuit 14 is connected to the word lines w1 to WN of the memory cell matrix 22 except for the memory cell matrix 12 shown in FIG.

Here, the memory cell matrix 22 basically consists of the first
It has a circuit configuration similar to that of the address decoder 11 shown in the figure, and the only difference is the arrangement state of MOSQII to QLI.

In such a ROM device, address signals A11l to A
DF is decoded by memory cell matrix 22, and the decoded signals are output to bit lines W1-WM and sent out via storage circuit 14 as output signals D1-DN. In such a read operation, data ADI−'ADF
The clock signal φ causes the load MOSQ to change only when
Since current flows through L1-QLM, power consumption can be reduced similarly to the first embodiment.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of variations include the following.

(i) In Figure ii and Figure 4, address decoder 1
1 and the enhancement type NNOSQAI-QAM, QBI to QBN in the memory cell matrix 12.22,
Even if the enhancement type PMOS is replaced and a negative clock signal T is applied to their gates, the same operation and effect as in the above embodiment can be obtained.

(ii) i 1 In Figures 1 and 4, either one or both of enhancement type NMOS
If the CMOS is configured by connecting these in series and applying a negative clock signal T to the gate of PKO9, the voltage drop can be reduced compared to the case where the NMOS QAI~I;JAM, QBI~QBH are used alone. Therefore, there is an advantage that the power consumption generated therein is reduced.

(iii) The clock signal generation circuit 13 can also be constructed from other circuits, such as the circuit described in Japanese Patent Application Laid-open No. 165983/1983.

(iv) Other enhancement type M forming the address decoder 11 and memory cell matrix 12.22
Various modifications are possible, such as changing OSQ 11 to QL2 and QNI 1 to 0MN3 to depletion type MOS, or configuring the memory circuit 14 with other circuits.

(Effects of the Invention) As explained in detail below, according to the present invention, a change in the address signal is detected, and the detection signal causes the power supply current to be supplied to the second signal line to be turned on. Since it is controlled, the power supply current flows only when the address signal changes, and no power supply current flows at other times. Therefore, a significant reduction in power consumption can be expected.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a PLA showing a first embodiment of the present invention,
FIG. 2 is a circuit diagram of a conventional PLA, FIG. 3 is a signal waveform diagram of FIG. 1, and FIG. 4 is a circuit diagram of a ROM device showing a second embodiment of the present invention. II...Address decoder, 12.22...
...Memory cell matrix, 13...Clock signal generation circuit, 14...Memory circuit, A1-A
L...Address input line (first signal line), W1
~Wt...Word line (second signal line), 01~ON
...Bit line (second signal line), QAI-
QAM, QBI~QBN...MOS (first switch), QC:1-Qlll:N...M
O5 (second switch), Tll~TIN, D21
~T2N, QD1~QDN...Latch circuit, ADI-ADF...Address signal (input signal), DI-DN...Output signal. Applicant's agent: Yasushi Kakinoki Figure 2

Claims (1)

[Scope of Claims] A plurality of first signal lines to which an input signal is applied, a plurality of second signal lines arranged to intersect with the first signal lines and to which a power supply voltage is applied; a plurality of MOS transistors connected to intersections of the first and second signal lines, selects the second signal line based on the input signal and outputs an output signal from the second signal line; In the output MOS semiconductor memory device, a clock signal generation circuit detects a change in the input signal and generates a pair of positive and negative clock signals φ, @φ@ with a constant time width, and is connected to the second signal line. a first switch connected to the second signal line that turns on and off the power supply voltage based on the clock signal φ or @φ@; and a first switch connected to the second signal line that turns on and off the power supply voltage based on the clock signal φ or @φ@. A second switch that turns on and off, and a latch circuit that temporarily holds the output signal before the off state of the second switch based on the clock signal φ or @φ@. MOS semiconductor memory device.