JPS59135690A - Decoder circuit - Google Patents

Abstract

PURPOSE:To decrease remarkably the current consumption of a decoder circuit at nonselection state by using a latch circuit holding an output level of an NOR gate constituting the decoder circuit to a prescribed level and a transistor (TR) activating the said NOR gate at address change. CONSTITUTION:When bits A0...An-1 of an address signal are changed all from a low level state into a high level, at least for one bit, that is, the nonselecting state, even if a potential of a node E is elevated temporarily to an intermediate level or a high level by a clock pulse CP, since at least one of inverter TRs Q11...Q1n is turned on always, the potential of the node E is latched to the low level after the clock pulse CP is decayed. At the selecting state, all the inverter TRs Q11...Q1n are turned off and no current flows to the NOR gate. Further, in nonselecting state, a load TRQ7 is cut off and a TRQ3 is cut off at normal state, then no current flows to the NOR gate and the current consumption of the decoder circuit is reduced remarkably.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a decoder circuit, and more particularly, to a decoder circuit which is used in, for example, a MOS static random access memory and which greatly reduces current consumption when not selected.

(2) Background of the Technology Recently, as semiconductor memories such as MOS static random access memories have become larger in capacity and more highly integrated, the power consumption per memory chip has tended to increase. As the power consumption of the memory chip increases, the amount of heat generated increases, resulting in the inconvenience that an elaborate heat dissipation device is required to effectively cool the memory chip. Furthermore, in devices including large-capacity storage devices that use a large number of memory chips, there arises the disadvantage that power consumption becomes extremely large. Therefore, in order to eliminate such inconveniences, it is necessary to reduce the power consumption of each circuit that makes up the semiconductor memory as little as possible.

(3) Prior Art and Problems As a decoder circuit used as an address decoder of a MOS static random access memory, a circuit as shown in FIG. 1 has conventionally been used. The decoder circuit in the figure has an address signal AO+ for each bit.
Inverter transistors Qlt+..., Qln controlled by n-1 and connected in parallel to each other, and a load transistor Q2 (r-), a load transistor Q3
, an inverter made up of an inverter transistor Q4, and an output circuit made up of transistors Q5 and Q6.

In the decoder circuit shown in FIG. 1, when all bits AO+...+An-1 of the address signal are at a low level, the selected state is reached, and all inverter transistors Q
11 r Qln is turned off and the output of the NOR gate becomes high level. At this time, the next-stage inverter transistor Q4 is turned on, and the output X of the decoder circuit becomes high level, selecting a word line (not shown) or the like. On the contrary,
Address signal Ao.

... r When at least one of An+ is at high level, the inverter transistor corresponding to the high level address signal is turned on, and the output of the NOR gate becomes low level. Therefore, the next stage inverter transistor Q
4 is off and the multi-output X is at a low level.

In the conventional decoder circuit shown in FIG. 1, in the non-selected state, all inverter transistors Qu + . . . r Qsn of the NOR gate are turned off and no current flows through the NOR gate. However, when the decoder circuit becomes non-selected, the inverter transistor Q11. ...+Qx
Since at least one of the transistors n is turned on, current flows from the load transistor Q2 to the transistor that is turned on. That is, in the decoder circuit shown in FIG. 1, current flows through the NOAK 9-gate when selected, and current is consumed when not selected. In general, in memory devices, for example, when only one of the decoder circuits connected to each word line is in the selected state, all other decoders are in the non-selected state. In this case, a large amount of current flows through the non-selected decoder, making it impossible to reduce the power consumption of the semiconductor memory.

Margin below (3) (4) Purpose of the Invention The purpose of the present invention is to:
A decoder circuit used in semiconductor memory, etc. uses a launch circuit that holds the output level of a NOR gate constituting the decoder circuit at a predetermined level depending on whether it is selected or unselected, and a transistor that activates the NOR gate when an address changes. Based on this concept, the present invention aims to significantly reduce the current consumption of the decoder circuit in the non-selected state, thereby reducing the power consumption of the semiconductor memory.

(5) Structure and object of the invention According to the invention, a plurality of inverter transistors controlled by each bit of an address signal and connected in parallel between a first power supply terminal and a common output node;
A load transistor connected between the common output node and a second power supply terminal, a transistor that inverts the signal of the common output node and applies positive feedback to the load transistor, and a level of the common output node when the address signal changes. This is achieved by providing a decoder circuit comprising a transistor that controls the voltage (4) to change for a short period of time in the direction of the voltage at the second power supply terminal.

(6) Examples of the invention Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 2 shows the configuration of a decoder circuit according to an embodiment of the present invention. The decoder circuit in the same figure
AO+ "' + An-1 is connected to the dirt, and the inverter transistor Qll+ is connected in parallel with each other.
...+Q1n and P-channel type load transistor Q7
A next-stage inverter comprising a NOR gate and N-channel MOS transistors Q3 and Q4,
An output circuit composed of Nf innel MOS transistors Q5 and Q6, and an output point E of the NOR gate, that is, the first stage inverter transistor Qll r...r
The common drain of Q 1 n and the power supply V. . An N-channel MOS transistor Q8 is connected between the two transistors. The address signal AO+ is applied to the dirt of the transistor QB.
・+Clock pulse CP generated when An-1 changes
is applied.

The decoder circuit in FIG.
+...The selected state is reached when all An-1 are at low level. At this time, as shown in FIG. 3, at the time of change of the address signal, the clock pulse CP becomes high level for a short period of time, and the transistor QB is turned on for a short period of time. Then, all the inverter transistors Qst +...”In
is off, the potential of the output node E of the Nordart is pulled up to a high level. As a result, the next stage transistor Q4 is turned on, and the drain of the transistor Q4, that is, the node F becomes low level. When the node F becomes a low level, the υ load transistor Q7 is turned on, and the voltage at the node E is held at a high level.

That is, a positive feedback loop is formed by a circuit including transistor Q4 and transistor Q7 from node E, and latches the level of node E to a high level. At this time,
Even if clock pulse CP goes low and transistor Q8 turns off, node E remains at a high level.

Therefore, decode output X is held at a high level.

Next, each bit of the address signal Ao+...1An-1
Suppose that all of the inverter transistors Q11+...+Q change from a low level state to a state where at least one becomes a high level, that is, a non-selected state.
At least one of 1n turns on and pulls node E low, at least after the clock pulse CP disappears. As a result, the transistor Q4 is turned off and the i-linode F is set to a high level, so that the transistor Q7 is also turned off and the potential of the node E is held at a low level. At this time, the decode output X becomes a low level. in this way,
In the case of non-selection, even if the potential of the node E is temporarily raised to an intermediate level or a high level by the clock pulse CP, the inverter transistor Qll
+..., Qln is always on, so after the clock pulse cP disappears, the potential of the node E is latched to a low level.

In the decoder circuit shown in FIG. 2, when selected, the inverter transistors Qlt + . Also, when not selected, load transistor Q7
is cut off and the transistor Q8 is also cut off in a steady state, so that no current flows through the gate, and the power consumption of the decoder circuit is greatly reduced.

4A or 4B is used in the decoder circuit of FIG. 2, and is used for the decoder circuit of FIG.
2 shows a circuit for generating the clock f pulse CP that occurs when the voltage An-1 changes from a high level to a low level or from a low level to a high level. 4th A
In the figure, G1 to G4 are inverters, Gs and G6 are nor-darts, and G7 is or-dirts, which are connected as shown and output a clock CKi upon receiving 1 bit A of the address signal. This circuit CKG of FIG. 4A.

is provided for each bit A of the address signal, and the outputs of the respective circuits CKGO, CKGl, . .

The operation of these circuits will be explained with reference to Figure 4C. One bit A1 of the address signal changes from a low level to a high level or from a high level to a low level as shown in a in column 1) of Figure 4C. When doing so, inverter G! The output of is as shown in column 2) b, and the output of inverter G is the inverted output d (4th column) which is slightly delayed by the capacitor CI.
, and the output f of the Nordart G5 becomes the i4' signal generated at the rising edge of bit AI of the address signal. The system of inverter G11, 4% capacitor C2, and NOAG G6 operates in the same manner, but its output g (seventh column) becomes a NO4 pulse that occurs when bits A and t fall. The combination of these at OR gate G7, CK, is a pulse that occurs when bit A of the address signal changes. Therefore, the output of OR gate G is when at least one bit of each bit of the address signal changes. The target clock pulse CP is generated when

(7) Effects of the Invention As described above, according to the present invention, since no current flows to the NOR gate even when the decoder circuit is in the non-selected state, it is possible to significantly reduce the power consumption of the decoder circuit. It becomes possible to significantly reduce the power consumption of a semiconductor memory using such a decoder circuit.

[Brief explanation of drawings]

FIG. 1 is an electric circuit diagram showing a conventional decoder circuit, FIG. 2 is an electric circuit diagram showing a decoder circuit according to an embodiment of the present invention, and FIG. 3 is an operation of the decoder circuit shown in FIG. 2. 4A and 4B are electrical circuit diagrams showing a circuit for generating clock pulses used in the decoder circuit of FIG. FIG. 4B is a waveform chart for explaining the operation of the circuit shown in FIG. 4 and FIG. 4B. Qls +”'IQ1nl Q will + Qs r G
4 r Q! ++Qa +Qa: N-channel MOS transistor, G7: P-channel MO8) transistor, Gl + Gl rG,, G4: Inverter, G5, G,: Noah boot, G7, Gs Nior gate, CITC! : Kifno ni Shita. Patent Applicant: Fujitsu Limited Patent Attorney: Akira Aoki, Patent Attorney: Kazuyuki Nishidate, Patent Attorney: 1) Yukio, Patent Attorney: Akira Yamaguchi (11) Figure 1 Figure 2 (12) Figure 3 I: 1 arrogant arrogance - hehehe~ + Nn q φ ψ Tortious procedural amendment March 2, 1980 Commissioner of the Patent Office Kazu Wakasugi Blunder 1, Indication of incident 1982 Patent Application No. 226607 2, Invention Name of decoder circuit 3, relationship with one case of person making an amendment Patent applicant name (522) Fujitsu Ltd. 4, agent (3 others) 5. Subject of amendment (1) ``Patent claim'' in the specification Column 6 of ``Scope'' (2) Column 6 of ``Detailed Explanation of One Invention'' in the Specification, Contents of Amendment (1) The ``Claims'' of the Description will be amended as shown in the attached sheet. (2) From the 5th member, line 12 to the 6th member, line 2 of the specification, the phrase ``And this object is achieved...'' is replaced with ``And this object is achieved.'' According to the present invention, the inverter has a plurality of decoding inverter transistors, a load transistor, and a transistor controlled according to a change in an address signal, and the plurality of inverter transistors are controlled by each bit of the address signal. A first power supply terminal is connected in parallel to a common output node, and the load transistor is connected between the common output node and a second power supply terminal, and is controlled to provide positive feedback to the output of the common output node. This is achieved by providing a decoder circuit, wherein the transistor is controlled to connect the common output node to the second power supply terminal for a predetermined period of time when the signal changes. ”. 7. Amended Patent Claims in the Attached Document 1 2. Controlled by the claims and connected in parallel between the first power supply terminal and the common node Q-, the load transistor is connected to the common output node. 1. A decoder circuit, wherein the decoder circuit is connected between second power supply terminals, and the common output node is connected to the second power supply terminal for a predetermined period of time when the decoder circuit is turned on. (3)

Claims (1)

[Claims] a plurality of inverter transistors controlled by each bit of an address signal and connected in parallel between a first power supply terminal and a common output node; a load transistor connected between the common output node and a second power supply terminal; and the common output node. a transistor that inverts a signal of the signal to apply positive feedback to the load transistor, and a transistor that controls the level of the common output node to change for a short time in the direction of the voltage of the second power supply terminal when the address signal changes. A decoder circuit comprising: