JPS6237583B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a modem in a data communication system, and the line speed can be rolled back according to the line quality within the modem without reducing the transmission speed between the data communication device and the modem. The purpose is to

Conventionally, in data communication systems such as those between a computer and a terminal device, or between transmitting and receiving devices in some types of facsimile communication, when an error occurs due to a line failure, the data communication device retries, and if the retry is not successful, Communication became impossible and the line had to be disconnected. In addition, in certain data communication systems that involve computers, the computer monitors the frequency of errors,
When the frequency of errors exceeded a certain standard, the modem was instructed to slow down the line speed. However, with this method, as the number of data communication devices connected to a computer via communication media increases, a line quality monitoring circuit is installed for each line, and speed control is performed for each line. However, the disadvantage is that the control is complicated and the cost is high. Furthermore, if the line speed changes, the speed between the modem and the computer must also be changed to the same speed, which places a heavy burden on the computer.

The present invention aims to eliminate such drawbacks in conventional data communication systems, and in order to achieve this purpose, the present invention includes the following:
In a data communication system in which data communication devices such as computers and facsimiles are interconnected by communication media such as communication lines, satellite lines, and data highways, a modem and modulation device installed between the data communication devices and the communication medium, which is a communication line. A circuit that sends and receives check signals to check quality, a circuit that sends and receives check results to and from the other device, a clock generation circuit that generates clocks of multiple frequencies, and a fallback based on the check results. A circuit that generates an instruction signal, a line speed selection control circuit that switches the clock from the clock generation circuit and outputs it to the line interface section in response to a fallback instruction signal from the other party, and a line speed selection control circuit that outputs data from the communication device of the local station or the other station. A buffer for storing a clock is provided, and the clock is fixedly supplied to the communication device from the clock generation circuit, and when the communication quality is degraded as a result of the check signal, the clock generation circuit A circuit configuration is adopted that selects a clock with a lower frequency among the outputs.

Next, an embodiment of a modulation/demodulation device according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a system diagram of an example in which a modem according to the present invention is used between a host computer and a terminal device of a data communication system, and FIG. 2 is a configuration of a modem according to the present invention used in the system of FIG. FIG.

In FIG. 1, 1 is a host computer,
2A, 2B...2N are modem devices connected to the host computer 1, respectively; 3A, 3B...3
N is a terminal side modem device connected to the modem device 2A, 2B...2N via a communication line, respectively;
4A, 4B...4N are terminal side modem devices 3A, 3
B, . . . 3N are terminal devices respectively connected to the terminals. Each terminal device 4A, 4B, . . . 4N is controlled by a host computer 1 via modem devices 2A, 2B, . FIG. 2 is a block diagram showing the line control section of the modulators 2A and 3A. In FIG. 2, first, the modem 2A on the side of the host computer 1 will be described. Reference numeral 5 denotes an interface control unit that constitutes an input end and an output end between the modem 2A and the host computer 1. 6 is a clock signal generation circuit connected to the interface control unit 5, which supplies a clock signal at a constant speed to the host computer 1, and supplies a clock signal to the line according to the line quality; For example, the speed of the clock signal
Can be switched to 9600bps, 7200bps, 4800bps, 2400bps. 7 is a clock signal generation circuit 6
This is a line speed selection control unit that gives a line speed selection instruction to the user. Reference numeral 8 denotes an interface control unit that constitutes an input end and an output end between the modulation and demodulation device 2A and the modulation and demodulation device 3A on the terminal device 4A side. 9 is
This is a "0" bit string generation/check circuit, which transmits a "0" bit string to the other party's modem 3A for a certain period of time, and in reception mode, it transmits the "0" bit string sent from the other party's modem 3A. The line is monitored, and if more than a certain number of "0" bits change to "1" bits, it is considered that there is a line failure, and the line speed selection control section 7 is notified of the 'line failure'. 10 is an error transmission/reception circuit, and line speed selection control section 7
When receiving the line failure notification, it instructs the terminal side modem 3A that transmitted the "0" bit string to transmit a line speed fallback, and also instructs the line speed selection control section 7 to perform a clock fallback. When a fallback instruction is received from the terminal side modem 3A, the line speed selection control section 7 is similarly instructed to perform a clock fallback. 11 is
A buffering control circuit 11' buffers data from the host computer 1 and performs flow control when the buffer becomes full; 11' is a buffering control circuit that buffers data to the host computer 1; 12,1;
2' is a flow control circuit provided in the buffering control circuits 11, 11'. 13 is a data transmitter, and 14 is a data receiver. The terminal side modem 3A has exactly the same configuration, but the interface control section 5 is connected to the terminal device 4A.

Next, the operation of this modem will be explained. Data communication is performed according to a predetermined sequence, and a line quality check operation is inserted at a predetermined position on the sequence, for example, at the beginning of the sequence. Now, prior to data communication, the "0" bit string generation/check circuit 9 of one modem, for example, the host computer side modem 2A, sends a signal to the "0" bit string generation/check circuit 9 of the terminal side modem 3A. , transmits a signal of "0" bit string for a certain period of time. Then, the "0" bit string generation/check circuit 9 of the terminal-side modem 3A receives and monitors this "0" bit string, and if more than a certain number of "0"s change to "1", the line quality is determined. is considered to be defective, and notifies the line speed selection control unit 7 that the line is defective. The line speed selection control unit 7 of the terminal side modem transmits the line speed by one level to the host computer side modem 2A, which is the "0" bit string transmitting side, via the error transmitting/receiving circuit 10. At the same time as instructing a fallback, the speed selection terminal 6a of its own clock generation circuit 6 is also switched from, for example, 9600 bps to 7200 bps, thereby lowering the line speed by one level and causing its own clock to fall back.

If the "0" bit string generation/check circuit 9 of the terminal modem 3A on the receiving side does not detect a certain number of "1" bits or more and the line quality is normal, the host computer on the transmitting side Notify the side modem 2A that it is normal,
The above fallback operation is not performed.

On the other hand, in the host computer side modem device 2A which transmitted the "0" bit string, when the line speed fallback instruction is received by the error transmitting/receiving circuit 10, the line speed selection control unit 7 is notified of this fact.
As a result, the line speed selection control section 7 switches the speed selection terminal 6a from 9600 bps to 7200 bps, similar to the receiving side, and rolls back the clock by one stage. Then, by transmitting the "0" bit string again and repeating the above fallback operation, the line speed is lowered one step at a time until the error no longer occurs.
Select the optimal line speed.

This fallback operation is performed between the modem 2A and the modem 3A, so between the host computer 1 and the modem 2A, the
A and the terminal device 4A are not involved in the fallback operation. As a result, the line speed between the host computer 1 and the modem 2A does not fall back, so it can be fixed at the fastest speed of 9600 bps, even if the line speed between the modem 2A and 3A falls back and becomes slower. , there is no need to change the information transmission rate between the host computer 1 and the modem 2A.

Therefore, between the host computer 1 and the modem 2A, and between the modem 2A and the modem 3
In order to absorb the difference in line speed between A and A, each modem has a buffering control circuit 11, 11' in which data from the host computer 1 is buffered. Since the buffering control circuits 11 and 11' have limited processing capacity,
When the buffer is full, the flow control circuit 1
2 requests the host computer to stop data transmission.

Therefore, as mentioned above, even if the line speed between the modem devices 2A and 3A becomes slower due to fallback,
The transmission speed between the host computer 1 and the modem 2A and between the modem 3A and the terminal device 4A can always be kept constant. host·
Although the line between the computer 1 and the terminal device 4A has been explained, other modem devices 2B,...2N, 3B
...3N has exactly the same configuration and is automatically rolled back in the same way.

As described above, according to the present invention, since the modem has a fallback function, even in data communication systems such as some types of facsimile communications where automatic fallback operation was not possible in the past, the modem can always respond to the line quality. communication at the best possible transmission speed. In addition, even the modem device only needs to be replaced with the device of the present invention, and the data transmission device itself does not require modification.
Even with conventional devices, the effects of the present invention can be easily obtained. Furthermore, each data communication device does not have anything to do with line quality, and the transmission speed between the modem and the modem can always be fixed at high speed, which simplifies the configuration of the data communication device and allows it to be integrated into one device as shown in Figure 1. Even when a large number of lines are connected, for example, the transmission speed between the host computer 1 and each modulation/demodulation device 2A, 2B, . . . , 2N can be kept constant. Automatic fallback is therefore achieved at extremely low cost.

[Brief explanation of the drawing]

FIG. 1 shows a modem device according to the present invention as a host computer.
A diagram of a system used for data communication between a computer and each terminal device, and FIG. 2 is a block diagram showing an embodiment of a modulation/demodulation device according to the present invention. In the figure, 1 is the host computer, 2
A, 2B, . . . 2N, 3A, 3B, . . . 3N are modem devices, 4A, 4B, . 10 is an error transmission/reception circuit, 11 and 11' are buffering control circuits, and 12 and 12' are flow control circuits.

Claims (1)

[Scope of Claims] 1. In a data communication system in which data communication devices such as computers and facsimile machines are interconnected by communication media such as communication lines, satellite lines, and data highways, a modulation/demodulation system provided between the data communication devices and the communication medium. A device that includes a circuit that transmits and receives check signals for checking communication line quality, a circuit that transmits and receives check results to and from a partner device, and a clock generator that generates clocks of multiple frequencies. a circuit that generates a fallback instruction signal based on the check result; a line speed selection control circuit that switches the clock from the clock generation circuit and outputs it to the line interface section in response to a fallback instruction signal from the other party; the local station or the other station; A buffer for storing data from a communication device is provided, and a clock is fixedly supplied to the communication device from the clock generation circuit, while the communication quality is degraded as a result of the check signal. A modulation/demodulation device characterized in that the circuit is configured to select a clock having a lower frequency from among the outputs of the clock generation circuit.