JPS6237476B2 - - Google Patents
Info
- Publication number
- JPS6237476B2 JPS6237476B2 JP57093807A JP9380782A JPS6237476B2 JP S6237476 B2 JPS6237476 B2 JP S6237476B2 JP 57093807 A JP57093807 A JP 57093807A JP 9380782 A JP9380782 A JP 9380782A JP S6237476 B2 JPS6237476 B2 JP S6237476B2
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- node
- type transistor
- terminal
- charge trapping
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000007493 shaping process Methods 0.000 claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- 230000002950 deficient Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000007664 blowing Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
Landscapes
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Semiconductor Memories (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57093807A JPS58211399A (ja) | 1982-06-01 | 1982-06-01 | 半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57093807A JPS58211399A (ja) | 1982-06-01 | 1982-06-01 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58211399A JPS58211399A (ja) | 1983-12-08 |
| JPS6237476B2 true JPS6237476B2 (enrdf_load_stackoverflow) | 1987-08-12 |
Family
ID=14092671
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57093807A Granted JPS58211399A (ja) | 1982-06-01 | 1982-06-01 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58211399A (enrdf_load_stackoverflow) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62107500A (ja) * | 1985-11-05 | 1987-05-18 | Matsushita Electronics Corp | 半導体メモリ装置 |
| JP2533213B2 (ja) * | 1990-02-13 | 1996-09-11 | 株式会社東芝 | 半導体集積回路 |
-
1982
- 1982-06-01 JP JP57093807A patent/JPS58211399A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58211399A (ja) | 1983-12-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6700821B2 (en) | Programmable mosfet technology and programmable address decode and correction | |
| US4970686A (en) | Semiconductor memory cells and semiconductor memory device employing the semiconductor memory cells | |
| US4639895A (en) | Semiconductor memory device | |
| JP4992149B2 (ja) | モス構造のアンチヒューズを利用したメモリリペア回路 | |
| US4546454A (en) | Non-volatile memory cell fuse element | |
| US4896055A (en) | Semiconductor integrated circuit technology for eliminating circuits or arrays having abnormal operating characteristics | |
| US3940740A (en) | Method for providing reconfigurable microelectronic circuit devices and products produced thereby | |
| EP0058049B1 (en) | Defect-remediable semiconductor integrated circuit memory with spare substitution | |
| US6686791B2 (en) | Oxide anti-fuse structure utilizing high voltage transistors | |
| US6693481B1 (en) | Fuse circuit utilizing high voltage transistors | |
| US4794568A (en) | Redundancy circuit for use in a semiconductor memory device | |
| US4725980A (en) | Read only memory circuit | |
| EP0131930A2 (en) | Semiconductor memory device | |
| US7539074B2 (en) | Protection circuit with antifuse configured as semiconductor memory redundancy circuitry | |
| US4590388A (en) | CMOS spare decoder circuit | |
| US5677888A (en) | Redundancy circuit for programmable integrated circuits | |
| US5390150A (en) | Semiconductor memory device with redundancy structure suppressing power consumption | |
| EP0090331A2 (en) | Semiconductor memory device | |
| US5058070A (en) | High speed memory with row redundancy | |
| US4912674A (en) | Read-only memory | |
| US20060244510A1 (en) | E-fuse circuit using leakage current path of transistor | |
| JPS6237476B2 (enrdf_load_stackoverflow) | ||
| US5355338A (en) | Redundancy circuit for semiconductor memory device | |
| US12217809B2 (en) | One-time programmable bitcell for frontside and backside power interconnect | |
| EP0530376B1 (en) | Semiconductor memory having nonvolatile semiconductor memory cell |