JPS6237416B2 - - Google Patents
Info
- Publication number
- JPS6237416B2 JPS6237416B2 JP57129900A JP12990082A JPS6237416B2 JP S6237416 B2 JPS6237416 B2 JP S6237416B2 JP 57129900 A JP57129900 A JP 57129900A JP 12990082 A JP12990082 A JP 12990082A JP S6237416 B2 JPS6237416 B2 JP S6237416B2
- Authority
- JP
- Japan
- Prior art keywords
- command
- circuit
- command step
- processing device
- information processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000010365 information processing Effects 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 5
- 238000001514 detection method Methods 0.000 description 7
- 230000010355 oscillation Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 1
- 238000003745 diagnosis Methods 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Description
【発明の詳細な説明】
(1) 発明の技術分野
本発明は情報処理装置に係り、コマンドが実行
されていく時のコマンドを、メインクロツク以下
の最小記録単位のクロツクで計数し、正解計数と
比較することにより自動診断に使用する様にした
情報処理装置におけるコマンド実行検証方法に関
する。[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to an information processing device, in which the number of commands as they are executed is counted by clocks in the minimum recording unit below the main clock, and compared with the correct count. The present invention relates to a method for verifying command execution in an information processing device that is used for automatic diagnosis.
(2) 従来技術及び問題点
情報処理装置の障害発生時の診断において、ロ
ギングというステイタス情報を記憶装置に記録し
て行き、障害発生時その情報を調査するという方
法があるが、従来はプログラムを構成する命令の
実行数をカウントしているため、障害発生時、命
令単位でしか障害発生箇所がわからないため、障
害発生の原因の究明に時間を要していた。(2) Prior art and problems When diagnosing the occurrence of a failure in an information processing device, there is a method known as logging in which status information is recorded in a storage device and the information is investigated when a failure occurs. Since the number of executions of the constituent instructions is counted, when a failure occurs, the location of the failure can only be determined on an instruction-by-instruction basis, so it takes time to investigate the cause of the failure.
(3) 発明の目的
本発明は上記欠点を除去し、障害発生原因の究
明が容易となるコマンド実行検証方法を提供する
ことを目的とする。(3) Purpose of the Invention It is an object of the present invention to provide a command execution verification method that eliminates the above drawbacks and facilitates investigation of the cause of a failure.
(4) 発明の実施例
上記本発明の目的は、情報処理装置のコマンド
の実行において、情報処理装置がもつメインクロ
ツク以下の最小記録単位のパルスでコマンド実行
における準備段階から終了までの時間を計数記録
し、そのコマンドの正解計数と比較し、コマンド
実行検証を行うことを特徴とした情報処理装置に
おけるコマンド実行検証方法によつて達成され
る。(4) Embodiments of the Invention It is an object of the present invention to count and record the time from the preparation stage to the end of command execution in the execution of commands by an information processing device using pulses of the minimum recording unit below the main clock of the information processing device. This is achieved by a method for verifying command execution in an information processing device, characterized in that the command execution is verified by comparing the command with a correct count of the command.
(5) 発明の構成 以下本発明を実施例に基づいて説明する。(5) Structure of the invention The present invention will be explained below based on examples.
図は、本発明の実施例を示す図で、図中１は発
振回路、２はメインクロツク発生回路、３はコマ
ンド制御回路、４はコマンドレジスタ、５はコマ
ンドステツプ計数スタート回路、６はコマンドス
テツプ計数ストツプ回路、７はコマンドステツプ
カウンター、８はコマンドステツプ記憶回路、９
はコマンドストツプ・エラー検出回路、１０はエ
ラー検出回路、１１はコマンドステツプレジスタ
ー、１２は比較回路、１３は正解コマンドステツ
プレジスター、１４はコマンドステツプ格納メモ
リ、１５はメモリ制御回路である。 The figure shows an embodiment of the present invention, in which 1 is an oscillation circuit, 2 is a main clock generation circuit, 3 is a command control circuit, 4 is a command register, 5 is a command step count start circuit, and 6 is a command step count. 7 is a command step counter; 8 is a command step storage circuit; 9 is a stop circuit;
10 is a command stop/error detection circuit, 10 is an error detection circuit, 11 is a command step register, 12 is a comparison circuit, 13 is a correct command step register, 14 is a command step storage memory, and 15 is a memory control circuit.
動作について説明すると、発振器１出力は、メ
インクロツク発生回路で分周されて、処理部（図
示せず）に入力される一方コマンドステツプ計数
スタート回路５に直接入力する。 To explain the operation, the output of the oscillator 1 is frequency-divided by the main clock generating circuit and inputted to a processing section (not shown), and directly inputted to the command step counting start circuit 5.
コマンド制御回路３は処理部が発したコマンド
を収集し、ストアとか、ロードとかのコマンドの
判別を行なう。 The command control circuit 3 collects commands issued by the processing section and determines whether the command is a store or a load.
コマンド制御回路３からコマンドステツプ計数
スタート回路５に、コマンドオン信号を入力する
一方コマンドレジスタ４に実行中のコマンドをセ
ツトする。 A command ON signal is input from the command control circuit 3 to the command step count start circuit 5, while the command being executed is set in the command register 4.
コマンドステツプ計数スタート回路５はコマン
ドオン信号を受けるとコマンドステツプカウンタ
ー７を起動する。 The command step count start circuit 5 starts the command step counter 7 upon receiving the command on signal.
一方コマンドストツプ・エラー検出回路９は、
コマンド制御回路３からのコマンドストツプ信号
を受けるとコマンドステツプカウンター７のカウ
ント動作を停止させるとともに、コマンドステツ
プレジスター１１にカウト値をコマンドステツプ
レジスタ１１にセツトする。 On the other hand, the command stop error detection circuit 9
When a command stop signal is received from the command control circuit 3, the counting operation of the command step counter 7 is stopped, and a count value is set in the command step register 11.
一方メモリ制御回路１５は、コマンドレジスタ
４からのコマンドに基づき、コマンドステツプ格
納メモリ１４からコマンド対応のステツプ数を読
み出し、正解コマンドステツプレジスタ１３にス
トアしておく。 On the other hand, the memory control circuit 15 reads the number of steps corresponding to the command from the command step storage memory 14 based on the command from the command register 4, and stores it in the correct command step register 13.
比較回路１２は両レジスタの値を比較し、一致
すれば、メモリ制御回路１５、コマンドステツプ
記憶回路８をリセツトし、次のコマンドのカウン
トを開始する。 Comparison circuit 12 compares the values of both registers, and if they match, resets memory control circuit 15 and command step storage circuit 8, and starts counting the next command.
一方不一致の場合はコマンドステツプ記憶回路
８にスマンドステツプ数をストアする。 On the other hand, if they do not match, the command step number is stored in the command step storage circuit 8.
又、パリテイエラー等がエラー検出回路１０に
より検出された場合には、コマンドストツプ検出
回路９によりコマンドステツプ計数ストツプ回路
を起動し、コマンドステツプカウンター７による
カウント動作を停止させる。 If a parity error or the like is detected by the error detection circuit 10, the command stop detection circuit 9 activates the command step counting stop circuit and stops the counting operation by the command step counter 7.
そして、比較器１２では不一致となるのでカウ
ンタ値をコマンドステツプ記憶回路８にストアす
る。 Since the comparator 12 does not match, the counter value is stored in the command step storage circuit 8.
不一致の場合において、比較回路１２からアラ
ームが出力された場合には、コマンドステツプ記
憶回路８とメモリ制御回路１５の内容を読み出
す。 In the case of a mismatch, if an alarm is output from the comparator circuit 12, the contents of the command step storage circuit 8 and the memory control circuit 15 are read out.
一方不一致の場合において、アラームが出力さ
れなかつた場合には、他の原因によるエラー、例
えばパリテエ・エラー発生時に読み出す様にす
る。 On the other hand, in the case of a mismatch, if an alarm is not output, the reading is performed when an error due to another cause, for example, a parity error occurs.
(6) 発明の効果
以上の如く、本発明によれば、コマンドの実行
ステツプ数をカウントし、正解と比較し、不一致
の場合、ステツプ数とコマンドをストアするの
で、障害原因の解折が極めて容易となる。(6) Effects of the Invention As described above, according to the present invention, the number of execution steps of a command is counted, compared with the correct answer, and if there is a discrepancy, the number of steps and the command are stored, making it extremely easy to solve the cause of the failure. It becomes easier.
図は、本発明の実施例を示す図で、図中１は発
振回路、２はメインクロツク発生回路、３はコマ
ンド制御回路、４はコマンドレジスタ、５はコマ
ンドステツプ計数スタート回路、６はコマンドス
テツプ計数ストツプ回路、７はコマンドステツプ
カウント、８はコマンドステツプ記憶回路、９は
コマンドストツプ・エラー検出回路、１０はエラ
ー検出回路、１１はコマンドステツプレジスタ
ー、１２は比較回路、１３は正解コマンドステツ
プレジスター、１４はコマンドステツプ格納メモ
リ、１５はメモリ制御回路である。
The figure shows an embodiment of the present invention, in which 1 is an oscillation circuit, 2 is a main clock generation circuit, 3 is a command control circuit, 4 is a command register, 5 is a command step count start circuit, and 6 is a command step count. 7 is a command step counter, 8 is a command step storage circuit, 9 is a command stop/error detection circuit, 10 is an error detection circuit, 11 is a command step register, 12 is a comparison circuit, 13 is a correct command step register, 14 is a command step storage memory, and 15 is a memory control circuit.
Claims (1)
報処理装置がもつ、メインクロツク以下の最小記
録単位のパルスで、コマンド実行における準備段
階から終了までの時間を計数記録し、そのコマン
ドの正解計数と比較し、コマンド実行検証を行う
ことを特徴とした情報処理装置におけるコマンド
実行検証方法。1. In the execution of a command by an information processing device, count and record the time from the preparation stage to the end of the command execution using pulses of the minimum recording unit below the main clock of the information processing device, and compare it with the correct answer count for the command, A method for verifying command execution in an information processing device, characterized by verifying command execution.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57129900A JPS5920058A (en) | 1982-07-26 | 1982-07-26 | Command execution verifying method in information processor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57129900A JPS5920058A (en) | 1982-07-26 | 1982-07-26 | Command execution verifying method in information processor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5920058A JPS5920058A (en) | 1984-02-01 |
| JPS6237416B2 true JPS6237416B2 (en) | 1987-08-12 |
Family
ID=15021150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57129900A Granted JPS5920058A (en) | 1982-07-26 | 1982-07-26 | Command execution verifying method in information processor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5920058A (en) |
-
1982
- 1982-07-26 JP JP57129900A patent/JPS5920058A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5920058A (en) | 1984-02-01 |
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