JPS623617B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention is a digital-to-analog converter (DAC),
Specifically regarding DACs using resistor networks and summing amplifiers. A DAC is a device that converts digital information into corresponding analog information. Because DACs typically operate on the output of digital devices, they are sometimes considered decoders. The basic problem when converting a digital signal to the corresponding analog signal is:
The n digital levels may be converted to a corresponding analog voltage. Various methods have been developed to perform this conversion. The actual output voltage of the DAC varies at discrete points on an ideal straight line drawn across the conversion characteristic of the converter. This nonlinearity may not be a problem in some applications, but it may be a problem in others. For example, in electron beam recording applications, nonlinearity can cause distortion in CRT images. Nuclear equipment and the like also require associated data processing equipment that uses extremely linear transducers that can classify energy levels, charges, or particle moments into a plurality of clearly distinguishable channels. On the other hand, applications such as digital voice communications and airliner music distribution systems do not require very linear transducers. In the case of automatic measuring instruments, there are cases where it is desired to automatically adjust the first voltage to a second voltage and maintain this state as a reference voltage for subsequent measurements. In such applications, an essential requirement for a DAC is that its analog output voltage must never overshoot. It is therefore an object of the present invention to provide a new DAC in which the output analog voltage does not increase by more than one step for each digital input signal. The above objects and other objects and effects of the present invention,
The effects, etc. can be better understood by referring to the above explanation. It goes without saying that the embodiments described below are merely illustrative and are not intended to control the present invention. According to the present invention, it is possible to obtain a DAC in which no overshoot occurs in the expected analog output voltage.
This is achieved by operating the DAC non-monotonically. For this reason, the DAC of the present invention differs from conventional circuits in that it uses a resistor network (ladder) that does not strictly binary weight each resistor (referred to as 2 ⁿ ). The resistance for the MSB (most significant digit) is selected to be higher than the resistance required for normal binary weighting. Therefore, the analog output does not increase by more than one step at a time, and a unit increase in the digital input can cause the analog output to decrease by several steps. Although DACs are well known to those skilled in the art, the DAC of the present invention
In order to facilitate understanding, the prior art will be briefly explained below. First, FIG. 1a is a circuit diagram of a conventional 3-bit DAC. As mentioned above, the basic function of a DAC is to convert n digital voltage levels into one corresponding analog voltage. The simplest way to do this is to design a resistive network to transform each digital word into a corresponding binary weighted voltage or current. That is, three digital information is transmitted through three parallel resistors 11, each having a different resistance value.
12 and 13 into a resistor network 80 of the converter resistors. Digital input LSB (lowest)
is ²⁰ , and the MSB is ²² . Resistor network 8
The other end of 0 is commonly connected to the inverting input terminal of the operational amplifier 40. The non-inverting input terminal is grounded, and a scaling or feedback resistor Rf is connected between the output terminal 30 of the summing amplifier 40 and the inverting input terminal. FIG. 1b shows the truth value of the 3-bit binary signal that is the input signal to the DAC 40. These eight digital words are converted into corresponding analog voltages.
The minimum value is 000, assuming 0 volts. The maximum value is 111, which is +7 volts. This determines the range of analog voltage you want to generate. The minimum change step of a digital signal is LSB (2 ⁰ )
It is. Since there are seven discrete voltage levels between 000 and 111, it is convenient for the LSB to produce an analog output change as large as 1/7 of the full scale analog output voltage. Therefore, the design of the resistor network 80 is such that if the digital signal at the ²⁰ position is 1, +7 x 1/7 = 1 volt will be produced at the output 30. Similarly for other resistors,
The successively later or more significant bits are designed to generate an output twice as much as the output of the less significant bits. This means that the weighting of each bit is binary, and 1/
It is expressed as (2 ⁿ −1). Here n is the number of bits. FIG. 1c shows the binary weighting assigned to each bit of the DAC of FIG. 1a. The resistor network must have three digital input terminals and one analog output terminal as shown in FIG. 1a. If the input signal is 001, the output voltage will be +1 volt, similarly for a 010 input signal the output voltage will be +2 volts, and for a 100 input signal the output voltage will be +4 volts. For other input signals,
This is the sum of these voltages. Resistive voltage divider 8 in Figure 1a
0 can generate these voltages. If equivalent circuits are drawn for each of the eight types of input signal combinations and Milliman's theorem is applied, the result shown in FIG. 1a can be obtained. According to Milliman's theorem, the voltage appearing at a node in a resistor network (if the voltage at that node is 0 volts) is the sum of the currents flowing into that node divided by the sum of the conductances connected to it. will be the value. Expressing this mathematically, V=E ₁ /R ₁ +E ₂ /R ₂ +E ₃ /R ₃ +……/1
/R ₁ +1R/2+1/R ₃ +... The respective binary weighted currents are summed at the inverting input terminal of operational amplifier 40. The inverted output signal is the total current multiplied by the resistance of the feedback resistor Rf. Although the DAC techniques described above are simple and relatively inexpensive, they are impractical for high resolution DACs. There are many problems in making this type of DAC, but the biggest one is matching the tolerances of each resistor. For example, in an 11-bit DAC, the MSB
If we use a 10kΩ resistor as LSB
It is necessary to use a 20.48MΩ resistor.
0.025 required for such a wide range of resistance
% resistance matching and temperature coefficient is virtually impossible to obtain. Therefore, if such
When you build a DAC, its response becomes non-monotonic. The DAC of the present invention differs from the conventional example in that each resistance voltage divider is selected and used so that no overshoot occurs in the output analog voltage. For this reason, the DAC is intentionally designed to be non-monotonic. A monotonic DAC is one in which when the input step increases, the output step increases but remains the same. Then,
When such a DAC skips or misses output codes and the output level decreases, it becomes non-monotonic. Next, referring to FIG. 2, an embodiment according to the present invention will be described. Although the illustrated DAC is 11 bit, this is chosen merely for convenience and may be other. The digital word that we wish to convert to an analog voltage is the output signal of an 11-bit binary counter 10, which counter itself, of course, does not form part of the invention. The resistor network 80 is
It consists of eleven parallel connected resistors 11-21 and operates substantially in the same manner as the resistance network 80 described above. However, resistors 11-21 are chosen to make the DAC non-monotonic, ie the output voltage can decrease as the input voltage increases. However, when the digital input increases by a single step, the analog output voltage never increases by more than the single input increment.
In other words, the output voltage cannot overshoot from the predetermined analog output. The resistances of the resistors 11 to 21 are calculated so that the DAC is non-monotonic even in the worst case of power source impedance and voltage fluctuations. For example, consider that in the embodiment of FIG. 2, the output voltage of counter 10 is 0 volts for a logic 0 and 15 volts for a logic 1. The counter 10 of FIG. 2 is capable of counting 2048 (2 ¹¹ ) counts, but certain applications require a range of 1400 counts. Initially, the 6-bit LSB is assumed to be monotonic and remains in the normal binary weighting. In the circuit shown in FIG. 2, the design width N is set to an intermediate value between the required minimum value (1400) and maximum value (2048).
That is, N=(2048+1400)/2=1724. This width can also be defined by the following equation. If we substitute 1724 for N in equation (1) to find the value of x, we find that x is approximately 0.975. Therefore, multiplying the b ₆ −b _10- bit exponent by 0.975 yields the next bit weighting.

[Table] This bit weighting and logic level value (0 volts and 15 volts) and resistor 11 of LSB are set to 512k.
If Ω is selected, the resistance shown in (Table 2) can be found by calculation.

[Table] Next, a preferred embodiment of the present invention will be described with reference to FIG. 3. Operational amplifiers 50 and 60 and resistor 5
5, 65, 70 and 75 were added to the DAC in Figure 2. The resistance of each resistor in resistor network 80'' is selected as shown in Table 3. The desired amplification is achieved by using amplifiers 50 and 60, and the values of resistors 17 to 21 are set to 17'.
It is possible to make it as large as 21' to 21'. This narrows the resistance width of the required resistor, making it easier to use.
Made DAC more practical. Resistors 55 and 65
determine the gains of amplifiers 50 and 60, respectively. Resistors 70 and 75 and 55 and 65 are six
Determine the current ratio between LSB and 5 MSBs. The resistances shown below (Table 4) were found to be useful.

[Table] A simple algebraic calculation shows that the above ratio is 1:126. FIG. 4 is a plot of the transfer function of the DAC described above. It shows the analog output voltage when the digital input changes from 0 to 1024 steps.
It can be seen from the figure that the analog output voltage of this DAC never overshoots. From the above description, it can be understood that the DAC of the present invention is novel and is extremely useful for applications where non-monotonicity is acceptable but overshoot is not acceptable. In order to simplify the explanation, details, timing, bias, etc. have been omitted in the above explanation and figures, but it is believed that these matters can be easily understood by those skilled in the art. For further information on these, please refer to the Copyright 1972 Copyright by Analog Devices, Inc.
See ``Analog-to-Digital Conversion Handbook'' by DH Schieingold and ``Analog Systems for Microprocessors and Minicomputers'' by PH Gearett, Reston Publishing Co., Ltd. 1978. Furthermore, it should be noted that any specific embodiments of the invention described and illustrated herein are merely illustrative and are not intended to limit the invention in any way. Therefore, it should be understood that the technical scope of the present invention includes these embodiments and their modifications and variations.

【table】 [Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of the circuit and operation of a conventional DAC, FIG. 2 is a circuit diagram of a first embodiment of a DAC according to the present invention, and FIG. 3 is a circuit diagram of a second embodiment of a DAC according to the present invention. FIG. 4 shows the digital input versus analog output characteristics of the DAC according to the present invention. In the figure, 11 to 21 and 17' to 21' are resistors, respectively, and 40 is an adding means.

Claims (1)

[Scope of Claims] m resistors each receiving each bit of a 1 m-bit (m is an integer of 2 or more) digital input signal, and the output currents of these m resistors are added together to obtain the above result. Adding means for obtaining an analog signal corresponding to the m-bit digital input signal is provided, and among the m resistors, the resistor receiving the lower bit digital input signal has 2 ⁿ (n is 0 and less than m). A positive integer, n=0 to n=m-1
Each of the above corresponds to each of the m bits. ), and the resistor receiving the upper bit digital input signal is weighted by 2 ⁿ 〓 (λ is a positive number less than 1).