CN220964860U - R-2R digital-to-analog conversion trimming and calibrating circuit and digital-to-analog conversion chip - Google Patents

R-2R digital-to-analog conversion trimming and calibrating circuit and digital-to-analog conversion chip Download PDF

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CN220964860U
CN220964860U CN202322732459.8U CN202322732459U CN220964860U CN 220964860 U CN220964860 U CN 220964860U CN 202322732459 U CN202322732459 U CN 202322732459U CN 220964860 U CN220964860 U CN 220964860U
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trimming
resistor
branch
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main circuit
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赵婷
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Gl Microelectronics Inc
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Gl Microelectronics Inc
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Abstract

The specification relates to the technical field of integrated circuits, in particular to an R-2R digital-to-analog conversion trimming and calibrating circuit and a digital-to-analog conversion chip, wherein the R-2R digital-to-analog conversion trimming and calibrating circuit comprises an R-2R circuit and a trimming and calibrating circuit; the R-2R circuit comprises a resistor main circuit and n identical resistor branches, the trimming and calibrating circuit comprises a plurality of identical trimming branches which are connected in parallel, and one end of each trimming branch is connected with the other end of the resistor main circuit; the trimming branch comprises a plurality of trimming resistors connected in series and a trimming switch; one end of the series-connected trimming resistors is connected with the other end of the resistor main circuit, and the other end of the series-connected trimming resistors is connected with the first reference voltage V REFH or the second reference voltage V REFL through a trimming switch; the trimming switches of the trimming branches are respectively connected with V REFH or V REFL according to multi-position trimming control signals, the number of which is the same as that of the trimming branches. According to the embodiment of the specification, trimming and calibrating with specified precision can be realized, and additional layout matching problems can not be introduced.

Description

R-2R digital-to-analog conversion trimming and calibrating circuit and digital-to-analog conversion chip
Technical Field
The specification relates to the technical field of integrated circuits, in particular to an R-2R digital-to-analog conversion trimming and calibrating circuit and a digital-to-analog conversion chip.
Background
Digital-to-analog converters (Digital to Analog Converter, DACs) are widely used in many fields such as computers, communications, digital signal processing, aerospace, etc. DACs come in many different configurations, some with partial voltages, some with currents, and some with charge ratios. The R-2R resistor ladder network DAC is the most common structure, and is composed of a resistor network with a resistance value of R-2R, as shown in FIG. 1, the resistance between each node and the power supply is 2R, n-bit digital input 1 or 0 determines that the resistor 2R is connected with V REFH or V REFL, and the output terminal voltage can be expressed as formula (1):
Where V out represents the output voltage, V REFL represents the logic low level voltage, and V REFH represents the logic high level voltage. D in＝b0·20+b1·21+…+bn-1·2n-1 of the total number of the components, B 0～bn-1 denotes the state of the n-bit digital switch.
When the inputs of the n-bit digital switches b 0～bn-1 are all 0, the output voltage V out is equal to the logic low level voltage (i.e., the second reference voltage) V REFL; when the inputs of the n-bit digital switches b 0～bn-1 are all 1, the output voltage V out is equal to the difference between the logic high voltage (i.e., the first reference voltage) V REFH and V LSB. The R-2R structure has small area and simple structure, and the output precision is mainly limited by the matching precision of the resistor, so that the 10-bit resolution can be achieved under the condition of no trimming and calibration.
However, in the actual design, the resistances R, 2R and the switch resistance deviate along with factors such as the process, the temperature gradient, and the like, so that the actual output voltage deviates from the expected voltage. It is often necessary to trim the DAC for more bits.
The current trimming and calibrating mostly adopts a mode of trimming the resistance value of the resistor, the mode needs to introduce a trimming resistor delta R and a control switch into the resistor R, and as delta R is usually one thousandth of R, the size deviation between the delta R and the resistor R is larger, and the resistor R is difficult to match, so that the layout matching problem can be caused. Meanwhile, the introduction of the limited on-resistance of the control switch causes difficulty in accurately controlling the trimming resistor delta R, and the metal interconnection line between the switch and the resistor also causes resistance deviation, so that more complex matching problem is caused, and even the problem is not solved.
How to avoid introducing complex matching problems in the trimming process of an R-2R digital-to-analog conversion circuit is a problem which needs to be solved in the prior art.
Disclosure of utility model
In order to solve the problems in the prior art, the embodiment provides an R-2R digital-to-analog conversion trimming and calibrating circuit and a digital-to-analog conversion chip, and when trimming and calibrating output voltage, the number of resistors required to be increased by the circuit is small, and particularly, the trimming and calibrating with specified precision can be realized by changing the lowest 2R resistor into a plurality of 2R resistor strings which are connected in parallel. Because the 2R resistor is a basic resistor in the DAC structure, the resistor can be matched with the resistor of the DAC structure, the problem of extra layout matching is not introduced, the size of a switch connected with the trimming resistor is consistent with that of a lowest-order control switch, and the complexity of layout design is not increased.
Embodiments herein provide an R-2R digital-to-analog conversion trimming calibration circuit comprising: an R-2R circuit and a trimming and calibrating circuit;
The R-2R circuit comprises a resistor main circuit and n identical resistor branches, the resistor main circuit comprises n-1 main circuit resistors R which are connected in series, one end of the resistor main circuit is an output end V out, and two ends of each main circuit resistor R are coupled with one resistor branch; the resistor branch comprises a branch resistor 2R and a switch, one end of the branch resistor 2R is connected with one end of the main resistor R, and the other end of the branch resistor 2R is connected with a first reference voltage V REFH or a second reference voltage V REFL through the switch; the switches of the n resistor branches are respectively connected with the first reference voltage V REFH or the second reference voltage V REFL according to n-bit input signals;
The trimming and calibrating circuit comprises a plurality of identical trimming branches which are connected in parallel, and one end of each trimming branch is connected with the other end of the resistor main circuit; the trimming branch circuit comprises a plurality of trimming resistors connected in series and a trimming switch; one end of the series-connected trimming resistors is connected with the other end of the resistor main circuit, and the other end of the series-connected trimming resistors is connected with the first reference voltage V REFH or the second reference voltage V REFL through a trimming switch; the trimming switches of the trimming branches are respectively connected with the first reference voltage V REFH or the second reference voltage V REFL according to multi-bit trimming control signals, the number of which is the same as that of the trimming branches.
Further, the number of trimming branches is 2;
The resistance value of each trimming branch after a plurality of trimming resistors are connected in series is twice the resistance value of the branch resistor 2R.
Further, the number of trimming branches is 4;
the resistance value of each trimming branch after a plurality of trimming resistors are connected in series is four times of the resistance value of the branch resistor 2R.
On the other hand, the embodiment of the specification also provides an R-2R digital-to-analog conversion trimming and calibrating circuit, which comprises an R-2R circuit and a trimming and calibrating circuit;
The R-2R circuit comprises a resistor main circuit, n-1 identical resistor branches and a standard resistor, one end of the standard resistor is connected with one end of the resistor main circuit, and the other end of the standard resistor is connected with a second reference voltage V REFL; the resistor main circuit comprises n-1 main circuit resistors R which are connected in series, and the other end of the resistor main circuit is an output end V out; the resistor branch comprises a branch resistor 2R and a switch, one end of the branch resistor 2R is connected with one end of the main resistor R, and the other end of the branch resistor 2R is connected with a first reference voltage V REFH or a second reference voltage V REFL through the switch; the main circuit resistor R close to the standard resistor is used as a first main circuit resistor R, one end, far away from the output end V out, of the first main circuit resistor R is coupled with a resistor branch, one end, close to the output end V out, of the second main circuit resistor R in the main circuit resistor R is coupled with a resistor branch, and two ends of the third to n-1 main circuit resistors R in the main circuit resistor are coupled with a resistor branch;
The trimming calibration circuit comprises a plurality of identical trimming branches connected in parallel, wherein each trimming branch comprises a plurality of trimming resistors connected in series and a trimming switch; one end of each of the series-connected trimming resistors is coupled to a connection point of a first main circuit resistor R and a second main circuit resistor R in the resistor main circuit, and the other end of each of the series-connected trimming resistors is connected with a first reference voltage V REFH or a second reference voltage V REFL through a trimming switch; the trimming switches of the trimming branches are respectively connected with the first reference voltage V REFH or the second reference voltage V REFL according to multi-bit trimming control signals, the number of which is the same as that of the trimming branches.
Further, the number of trimming branches is 4;
the resistance value of each trimming branch after a plurality of trimming resistors are connected in series is four times of the resistance value of the branch resistor 2R.
On the other hand, the embodiment of the specification also provides an R-2R digital-to-analog conversion trimming and calibrating circuit, which comprises an R-2R circuit and a trimming and calibrating circuit;
The R-2R circuit comprises a resistor main circuit, n-1 identical resistor branches and a standard resistor, wherein one end of the standard resistor is connected with one end of the resistor main circuit, and the other end of the standard resistor is connected with a first reference voltage V REFH; the resistor main circuit comprises n-1 main circuit resistors R which are connected in series, and the other end of the resistor main circuit is an output end V out; the resistor branch comprises a branch resistor 2R and a switch, one end of the branch resistor 2R is connected with one end of the main resistor R, and the other end of the branch resistor 2R is connected with a first reference voltage V REFH or a second reference voltage V REFL through the switch; the main circuit resistor R close to the standard resistor is used as a first main circuit resistor R, one end, far away from the output end V out, of the first main circuit resistor R is coupled with a resistor branch, one end, close to the output end V out, of the second main circuit resistor R in the main circuit resistor R is coupled with a resistor branch, and two ends of the third to n-1 main circuit resistors R in the main circuit resistor are coupled with a resistor branch;
The trimming calibration circuit comprises a plurality of identical trimming branches connected in parallel, wherein each trimming branch comprises a plurality of trimming resistors connected in series and a trimming switch; one end of each of the series-connected trimming resistors is coupled to a connection point of a first main circuit resistor R and a second main circuit resistor R in the resistor main circuit, and the other end of each of the series-connected trimming resistors is connected with a first reference voltage V REFH or a second reference voltage V REFL through a trimming switch; the trimming switches of the trimming branches are respectively connected with the first reference voltage V REFH or the second reference voltage V REFL according to multi-bit trimming control signals, the number of which is the same as that of the trimming branches.
Further, the number of trimming branches is 4;
the resistance value of each trimming branch after a plurality of trimming resistors are connected in series is four times of the resistance value of the branch resistor 2R.
On the other hand, the embodiment of the specification also provides a digital-to-analog conversion chip which comprises a substrate and the R-2R digital-to-analog conversion trimming and calibrating circuit formed on the substrate.
In the embodiment of the specification, a low-order branch in an R-2R circuit is replaced by a trimming and calibrating circuit consisting of a plurality of trimming branches, the high-order branch in the R-2R circuit is kept unchanged, and when trimming is performed, the switch of each trimming branch in the trimming and calibrating circuit is controlled to be selectively connected with a first reference voltage V REFH or a second reference voltage V REFL, so that the DAC output voltage is calibrated in a specified calibrating range. In addition, DAC output curve simulation under a plurality of input intervals can be respectively carried out under a plurality of different switch control modes of the trimming and calibrating circuit, and the switch control mode of the trimming and calibrating circuit corresponding to each input interval is determined according to simulation results and DAC precision requirements, so that the precision of DAC output is ensured.
By means of the R-2R digital-to-analog conversion trimming and calibrating circuit, low-order branches in the R-2R circuit are replaced, complexity of the circuit is not increased, and complexity of layout design is guaranteed to be in a reasonable range. In addition, the resistance value of the trimming resistor in the trimming and calibrating circuit is the basic resistor in the DAC structure, so that the trimming resistor can be matched with the branch resistor and the main resistor in the DAC structure, and no additional layout matching problem is introduced.
Drawings
In order to more clearly illustrate the embodiments herein or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments herein and that other drawings may be obtained according to these drawings without inventive effort to a person skilled in the art.
FIG. 1 is a schematic diagram of a prior art R-2R digital to analog conversion circuit;
FIG. 2 is a schematic diagram of an R-2R digital-to-analog conversion trimming calibration circuit in an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of another R-2R digital-to-analog conversion trimming calibration circuit in an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of another R-2R digital-to-analog conversion trimming calibration circuit in an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of another R-2R digital-to-analog conversion trimming calibration circuit in an embodiment of the present disclosure;
FIGS. 6 (a), 6 (b) and 6 (c) are graphs of DAC input and output for three different cases of ideal conditions, non-ideal conditions, 2-bit trimming calibration in the embodiments of the present description, respectively;
FIG. 7 (a) is a simulation diagram of integral nonlinearity and differential nonlinearity of the DAC before and after trimming calibration in the embodiments of the present specification;
Fig. 7 (b) is a simulation diagram of the integral nonlinear curves of the DAC before and after trimming calibration in the embodiment of the present specification.
[ Reference numerals description ]
101. An R-2R circuit;
1011. a resistor main circuit;
1012. A resistor branch;
102. Trimming and calibrating the circuit;
1021. Repairing and adjusting the branch;
401. an R-2R circuit;
4011. A resistor main circuit;
4012. a resistor branch;
402. trimming and calibrating the circuit;
4021. repairing and adjusting the branch;
403. A standard resistor;
501. An R-2R circuit;
5011. A resistor main circuit;
5012. a resistor branch;
502. Trimming and calibrating the circuit;
5021. Repairing and adjusting the branch;
503. Standard resistance.
Detailed Description
The following description of the embodiments of the present disclosure will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the disclosure. All other embodiments, based on the embodiments herein, which a person of ordinary skill in the art would obtain without undue burden, are within the scope of protection herein.
FIG. 2 shows a digital-to-analog conversion trimming calibration circuit for R-2R in accordance with an embodiment of the present disclosure, comprising: an R-2R circuit 101 and a trimming calibration circuit 102;
The R-2R circuit 101 comprises a resistor main circuit 1011 and n identical resistor branches 1012, the resistor main circuit 1011 comprises n-1 main circuit resistors R connected in series, one end of the resistor main circuit 1011 is an output end V out, and two ends of each main circuit resistor R are coupled with one resistor branch; the resistor branch 1012 comprises a branch resistor 2R and a switch, one end of the branch resistor 2R is connected with one end of the main resistor R, and the other end of the branch resistor 2R is connected with the first reference voltage V REFH or the second reference voltage V REFL through the switch; the switches of the n resistor branches 1012 are respectively connected with the first reference voltage V REFH or the second reference voltage V REFL according to n-bit input signals;
The trimming calibration circuit 102 includes a plurality of parallel identical trimming branches 1021, wherein one end of the trimming branch 1021 is connected with the other end of the resistor main 1011; the trimming branch 1021 comprises a plurality of trimming resistors connected in series and a trimming switch; one end of the series connection of the plurality of trimming resistors is connected with the other end of the resistor main circuit 1011, and the other end of the series connection of the plurality of trimming resistors is connected with the first reference voltage V REFH or the second reference voltage V REFL through a trimming switch; the trimming switches of the trimming branches 1021 are respectively connected with the first reference voltage V REFH or the second reference voltage V REFL according to multi-bit trimming control signals which are the same as the trimming branches 1021 in number.
In the embodiment of the specification, a low-order branch in an R-2R circuit is replaced by a trimming and calibrating circuit consisting of a plurality of trimming branches, the high-order branch in the R-2R circuit is kept unchanged, and when trimming is performed, the switch of each trimming branch in the trimming and calibrating circuit is controlled to be selectively connected with a first reference voltage V REFH or a second reference voltage V REFL, so that the DAC output voltage is calibrated in a specified calibrating range. In addition, DAC output curve simulation under a plurality of input intervals can be respectively carried out under a plurality of different switch control modes of the trimming and calibrating circuit, and the switch control mode of the trimming and calibrating circuit corresponding to each input interval is determined according to simulation results and DAC precision requirements, so that the precision of DAC output is ensured.
By means of the R-2R digital-to-analog conversion trimming and calibrating circuit, low-order branches in the R-2R circuit are replaced, complexity of the circuit is not increased, and complexity of layout design is guaranteed to be in a reasonable range. In addition, the resistance value of the trimming resistor in the trimming and calibrating circuit is the basic resistor in the DAC structure, so that the trimming resistor can be matched with the branch resistor and the main resistor in the DAC structure, and no additional layout matching problem is introduced.
In the embodiment of the present disclosure, the number of trimming branches 1021 in the trimming calibration circuit 102 may be plural, and the trimming control signal may be a binary number, where the number of trimming bits is the same as the number of trimming branches 1021. As shown in fig. 2, if a certain bit of the trimming control signal is 1, the switch of the trimming branch 1021 corresponding to the bit is connected to the contact 1, so that the trimming branch is connected to the first reference voltage V REFH; if a certain bit of the trimming control signal is 0, the switch of the trimming branch 1021 corresponding to the certain bit is connected with the contact 0, so that the trimming branch is connected with the second reference voltage V REFL.
The control principle of the R-2R circuit 101 is the same as that of the trimming calibration circuit 102, and will not be described here again.
In the embodiment of the present disclosure, the more the number of trimming branches 1021 is, the smaller the trimming and calibrating step length is, the finer the trimming effect is, but the number of resistors in the whole circuit is increased, and the complexity of the layout design is increased, so that the final number of trimming branches 1021 can be determined according to the actual trimming fineness and the complexity of the layout design.
Preferably, as further shown in fig. 2, the trimming calibration circuit 102 in the embodiment of the present disclosure includes two identical trimming branches 1021 connected in parallel;
The resistance value of each trimming branch after a plurality of trimming resistors are connected in series is twice as high as the resistance value of the branch resistor 2R.
As shown in fig. 2, the trimming calibration circuit 102 includes two trimming branches 1021, i.e. 2 bits trimming, the switch BLA is connected to the contact 1 if the bit corresponding to the switch BLA is 1, the branch where BLA is located is connected to the first reference voltage V REFH, and the switch BLA is connected to the contact 0 if the bit corresponding to the switch BLA is 0, and the branch where BLA is located is connected to the second reference voltage V REFL. The resistance of the trimming resistor in the trimming branch 1021 after being connected in series is twice the resistance of the branch resistor 2R and is 4R. For example, 2 resistors with a resistance value of 2R may be connected in series in each trimming branch, or 4 resistors with a resistance value of R may be connected in series, so long as the resistance value of 4R after the trimming resistors are connected in series is ensured.
The formula of the output voltage of the output terminal Vout is (2):
Wherein D in＝b0·20+b1·21+…+bn-1·2n-1, BLA and BLB have values of 0 or 1.n represents the number of resistive branches.
When only one of BLA and BLB is 1, the equivalent is BL bit linkage (V REFH-VREFL)/2 in FIG. 1 as described in the background; when BLA and BLB are both 1, the equivalent is BL bit linkage V REFH; when BLA and BLB are both 0, this is equivalent to BL bit linkage V REFL.
When bla=blb=1, V out is calculated as given in equation (2), V LSB is increased by 1 compared to V out in the related art, and similarly, when bla= |! When BLB and bla=blb=0, the corresponding V out is calculated, and the calibration range and step size can be obtained. As shown in table 1:
TABLE 1
Where LSB is the least significant bit, in the DAC, V LSB is the minimum output of the DAC,Therefore, the DAC output voltage is trimmed and calibrated in the range of [0,1V LSB ] and the trimming and calibrating step length is 0.5V LSB.
In another embodiment of the present disclosure, as shown in fig. 3, the number of trimming branches is 4; the resistance value of each trimming branch after a plurality of trimming resistors are connected in series is four times of the resistance value of the branch resistor 2R.
In the embodiment of the present disclosure, the trimming calibration circuit 102 includes 4 trimming branches 1021, i.e., 4-bit trimming is adopted, i.e., the BL bit resistor 2R in fig. 1 is split into 4 trimming branches. The resistance value of the trimming resistor in the trimming branch 1021 after being connected in series is four times of the resistance value of the branch resistor 2R and is 8R. For example, 2 resistors with 4R resistance may be connected in series in each trimming branch, or 4 resistors with 2R resistance may be connected in series, so long as the resistance after the series connection of the trimming resistors is ensured to be 8R.
The formula of the output voltage of the output terminal Vout is (3):
Wherein, the values of D in＝b0·20+b1·21+…+bn-1·2n-1, BLA, BLB, BLC and BLD are 0 or 1.n represents the number of resistive branches.
When bla=blb=blc=bld=1, V out is calculated by taking the formula (3), and compared with V out in the prior art, V LSB is increased, and similarly, when BLA-BLD is 0, only one value is 1, two values are 1, and three values are 1, the corresponding V out is calculated, so that the calibration range and step size can be obtained. As shown in table 2:
TABLE 2
Where LSB is the least significant bit, in the DAC, V LSB is the minimum output of the DAC,Therefore, the DAC output voltage is trimmed and calibrated in the range of [0,1V LSB ] and the trimming and calibrating step length is 0.25V LSB.
In another embodiment of the present disclosure, as shown in fig. 4, the b 1 bit in fig. 1 may be replaced by a trimming calibration circuit composed of 4 trimming branches.
Specifically, as shown in FIG. 4, the R-2R digital-to-analog conversion trimming calibration circuit comprises an R-2R circuit 401 and a trimming calibration circuit 402;
The R-2R circuit 401 includes a resistor main circuit 4011, n-1 identical resistor branches 4012, and a standard resistor 403, one end of the standard resistor 403 is connected to one end of the resistor main circuit 4011, and the other end of the standard resistor 403 is connected to a second reference voltage V REFL; the resistor main circuit 4011 comprises n-1 main circuit resistors R connected in series, and the other end of the resistor main circuit 4011 is an output end V out; the resistor branch 4012 comprises a branch resistor 2R and a switch, one end of the branch resistor 2R is connected with one end of the main resistor R, and the other end of the branch resistor 2R is connected with a first reference voltage V REFH or a second reference voltage V REFL through the switch; the main circuit resistor R close to the standard resistor 403 is taken as a first main circuit resistor R in the resistor main circuit 4011, one end of the first main circuit resistor R far away from the output end V out is coupled with a resistor branch 4012, one end of the second main circuit resistor R close to the output end V out in the resistor main circuit 4011 is coupled with a resistor branch 4012, and two ends of the third to n-1 main circuit resistors R in the resistor main circuit 4011 are coupled with a resistor branch 4012;
The trimming calibration circuit 402 includes a plurality of parallel identical trimming branches 4021, where the trimming branches 4021 include a plurality of trimming resistors connected in series and a trimming switch; one end of each of the series-connected trimming resistors is coupled to a connection point of a first main resistor R and a second main resistor R in the resistor main circuit 4011, and the other end of each of the series-connected trimming resistors is connected with a first reference voltage V REFH or a second reference voltage V REFL through a trimming switch; the trimming switches of the trimming branches 4021 are respectively connected to the first reference voltage V REFH or the second reference voltage V REFL according to the multi-bit trimming control signals which are the same as the trimming branches 4021 in number.
In the embodiment of the present disclosure, the trimming calibration circuit 402 may have a plurality of trimming branches 4021, and the trimming control signal may have a binary number, where the number of trimming bits is the same as the number of trimming branches 4021. As shown in fig. 4, if a certain bit of the trimming control signal is 1, the switch of the trimming branch 4021 corresponding to the bit is connected to the contact 1, so that the trimming branch 4021 is connected to the first reference voltage V REFH; if a certain bit of the trimming control signal is 0, the switch of the trimming branch 4021 corresponding to the certain bit is connected to the contact 0, so that the trimming branch 4021 is connected to the second reference voltage V REFL.
In the embodiment of the present disclosure, the more the number of trimming branches 4021 is, the smaller the trimming and calibrating step length is, the finer the trimming effect is, but at the same time, the number of resistors in the whole circuit is increased, and the complexity of the layout design is increased, so that the final number of trimming branches 4021 can be determined according to the actual trimming fineness and the complexity of the layout design.
Preferably, continuing with FIG. 4, trimming calibration circuit 402 in the present embodiment includes 4 identical trimming branches 4021 in parallel;
the resistance value of each trimming branch after a plurality of trimming resistors are connected in series is four times of the resistance value of the branch resistor 2R.
In the embodiment of the present disclosure, trimming calibration circuit 402 includes 4 trimming branches 4021, i.e., 4-bit trimming is adopted, i.e., b 1 -bit resistor 2R in fig. 1 is split into 4 trimming branches. The resistance of the trimming resistor in the trimming branch 4021 after being connected in series is four times of the resistance of the branch resistor 2R and is 8R. For example, 2 resistors with 4R resistance may be connected in series in each trimming branch, or 4 resistors with 2R resistance may be connected in series, so long as the resistance after the series connection of the trimming resistors is ensured to be 8R.
The formula of the output voltage of the output terminal Vout is (4):
Wherein, the values of D in＝b0·20+b1·21+…+bn-1·2n-1, BLA, BLB, BLC and BLD are 0 or 1.n-1 represents the total number of resistive branches.
When bla=blb=blc=bld=0, V out is calculated by taking the formula (4), and compared with V out in the prior art, V LSB is reduced, and similarly, when BLA-BLD is all 1, only one value is 1, two values are 1, and three values are 1, the corresponding V out is calculated, so that the calibration range and step size can be obtained. As shown in table 3:
TABLE 3 Table 3
Where LSB is the least significant bit, in the DAC, V LSB is the minimum output of the DAC,Therefore, the DAC output voltage is trimmed and calibrated in the range of [ -2V LSB, 0], and the trimming and calibrating step length is 0.5V LSB.
In order to further tune the tuning calibration range, the other end of the standard resistor 503 may also be connected to a first reference voltage V REFH as shown in fig. 5, according to one embodiment of the present description.
Specifically, as shown in FIG. 5, the circuit comprises an R-2R circuit 501 and a trimming calibration circuit 502;
The R-2R circuit 501 includes a resistor main circuit 5011, n-1 identical resistor branches 5012, and a standard resistor 503, where one end of the standard resistor 503 is connected to one end of the resistor main circuit 5011, and the other end of the standard resistor 503 is connected to a first reference voltage V REFH; the resistor main circuit 5011 comprises n-1 main circuit resistors R connected in series, and the other end of the resistor main circuit 5011 is an output end V out; the resistor branch 5012 comprises a branch resistor 2R and a switch, one end of the branch resistor 2R is connected with one end of the main resistor R, and the other end of the branch resistor 2R is connected with a first reference voltage V REFH or a second reference voltage V REFL through the switch; the main circuit resistor R close to the standard resistor 503 is taken as a first main circuit resistor R in the resistor main circuit 5011, one end of the first main circuit resistor R far away from the output end V out is coupled with a resistor branch 5012, one end of the second main circuit resistor R close to the output end V out in the resistor main circuit 5011 is coupled with a resistor branch 5012, and two ends of the third to n-1 main circuit resistors R in the resistor main circuit 5011 are coupled with a resistor branch 5012;
The trimming calibration circuit 502 includes a plurality of trimming branches 5021 which are connected in parallel and the trimming branches 5021 include a plurality of trimming resistors connected in series and a trimming switch; one end of each of the series-connected trimming resistors is coupled to a connection point of a first main resistor R and a second main resistor R in the resistor main circuit 5011, and the other end of each of the series-connected trimming resistors is connected with a first reference voltage V REFH or a second reference voltage V REFL through a trimming switch; the trimming switches of the trimming branches 5021 are respectively connected with the first reference voltage V REFH or the second reference voltage V REFL according to the multi-bit trimming control signals, the number of which is the same as that of the trimming branches 5021.
In this embodiment of the present disclosure, the trimming branches 5021 in the trimming calibration circuit 502 may be plural, and the trimming control signal may be a binary number, and the trimming bits are the same as the trimming branches 5021. As shown in fig. 5, if a certain bit of the trimming control signal is 1, the switch of the trimming branch 5021 corresponding to the bit is connected with the contact 1, so that the trimming branch 5021 is connected with the first reference voltage V REFH; if a certain bit of the trimming control signal is 0, the switch of the trimming branch 5021 corresponding to the certain bit is connected with the contact 0, so that the trimming branch 5021 is connected with the second reference voltage V REFL.
In the embodiment of the present disclosure, the more the number of trimming branches 5021 is, the smaller the trimming and calibrating step length is, the finer the trimming effect is, but at the same time, the number of resistors in the whole circuit is increased, and the complexity of the layout design is increased, so that the final number of trimming branches 5021 can be determined according to the actual trimming fineness and the complexity of the layout design.
Preferably, as further shown in fig. 5, the trimming calibration circuit 502 in the embodiment of the present disclosure includes 4 identical trimming branches 5021 connected in parallel;
the resistance value of each trimming branch after a plurality of trimming resistors are connected in series is four times of the resistance value of the branch resistor 2R.
In the embodiment of the present disclosure, the trimming calibration circuit 502 includes 4 trimming branches 5021, i.e., 4-bit trimming is adopted, i.e., the b 1 -bit resistor 2R in fig. 1 is split into 4 trimming branches. The resistance of the trimming resistor in the trimming branch 5021 after being connected in series is four times of the resistance of the branch resistor 2R and is 8R. For example, 2 resistors with 4R resistance may be connected in series in each trimming branch, or 4 resistors with 2R resistance may be connected in series, so long as the resistance after the series connection of the trimming resistors is ensured to be 8R.
The formula of the output voltage of the output terminal Vout is (5):
Wherein, the values of D in＝b0·20+b1·21+…+bn-1·2n-1, BLA, BLB, BLC and BLD are 0 or 1.n-1 represents the total number of resistive branches.
When bla=blb=blc=bld=0, V out is calculated by taking the formula (4), V LSB is reduced compared with V out in the prior art, and similarly, when BLA to BLD are all 1, only one value is 1, two values are 1, and three values are 1, the corresponding V out is calculated, so that the calibration range and step size can be obtained. As shown in table 4:
TABLE 4 Table 4
Where LSB is the least significant bit, in the DAC, V LSB is the minimum output of the DAC,Therefore, the DAC output voltage is trimmed and calibrated in the range of [ -1V LSB,1VLSB ] and the trimming and calibrating step length is 0.5V LSB.
The following description will take 12-bit DCA as an example for the R-2R digital-to-analog conversion trimming calibration circuit shown in fig. 2 of the present specification.
As shown in fig. 6 (a), the 12-bit DAC input-output curve is shown for the embodiment when the BLA and BLB switches are connected to different references under ideal conditions. Including bla=blb=1, BLA-! Output curves corresponding to three references, blb=blb=0. The abscissa in fig. 6 (a) is the input code of the DAC, and the ordinate is the output of the DAC.
Ideally, there is a linear relationship between the output curve and the input curve of the DAC as shown in fig. 6 (a). But non-ideal conditions may cause the DAC output curve to deviate from ideal values, as shown in fig. 6 (b), the integrated nonlinearity INL (Integral Nonlinearity) of the DAC output curve exceeds 0.5LSB. With the 2-bit trimming calibration shown in fig. 2 in the embodiment of the present specification, that is, by configuring different BLA and BLB values in different input intervals, as shown in fig. 6 (c), it is possible to ensure that the INL of the output curve is within 0.5LSB and the differential nonlinearity DNL (Differential Nonlinearity) is also within 0.5LSB.
Fig. 7 (a) is a graph of integrated nonlinearity and differential nonlinearity simulations of the DAC before and after trimming calibration in the embodiment of the present disclosure, with the abscissa representing the simulations performed on 2000 different chips. Fig. 7 (b) is a simulation diagram of integrated nonlinear curves of DACs before and after trimming calibration in the embodiment of the present disclosure, the abscissa represents 4096 DAC input codes, and the curves of different saturation in fig. 7 (b) represent 2000 different chips. The DNL (differential nonlinearity) of the DAC before calibration is 0.458LSB, the INL (integral nonlinearity) is 0.78LSB, the DNL after calibration is 0.51LSB, the INL is 0.28LSB, and the calibration circuit has an improvement effect of 0.5LSB on the INL.
On the other hand, the embodiment of the specification also provides a digital-to-analog conversion chip, which comprises a substrate and an R-2R digital-to-analog conversion trimming and calibrating circuit which is formed on the substrate and is described in the figure 2 or the figure 3 of the specification.
On the other hand, the embodiment of the specification also provides a digital-to-analog conversion chip which comprises a substrate and an R-2R digital-to-analog conversion trimming and calibrating circuit which is formed on the substrate and is shown in the figure 4 of the specification.
On the other hand, the embodiment of the specification also provides a digital-to-analog conversion chip which comprises a substrate and an R-2R digital-to-analog conversion trimming and calibrating circuit which is formed on the substrate and is shown in the figure 5 of the specification.
It should be understood that, in the various embodiments herein, the sequence number of each process described above does not mean the sequence of execution, and the execution sequence of each process should be determined by its functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments herein.
It should also be understood that in embodiments herein, the term "and/or" is merely one relationship that describes an associated object, meaning that three relationships may exist. For example, a and/or B may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.
Those of ordinary skill in the art will appreciate that the elements and algorithm steps described in connection with the embodiments disclosed herein may be embodied in electronic hardware, in computer software, or in a combination of the two, and that the elements and steps of the examples have been generally described in terms of function in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.
In the several embodiments provided herein, it should be understood that the disclosed systems, devices, and methods may be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices, or elements, or may be an electrical, mechanical, or other form of connection.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the elements may be selected according to actual needs to achieve the objectives of the embodiments herein.
In addition, each functional unit in the embodiments herein may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solutions herein are essentially or portions contributing to the prior art, or all or portions of the technical solutions may be embodied in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments herein. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Specific examples are set forth herein to illustrate the principles and embodiments herein and are merely illustrative of the methods herein and their core ideas; also, as will be apparent to those of ordinary skill in the art in light of the teachings herein, many variations are possible in the specific embodiments and in the scope of use, and nothing in this specification should be construed as a limitation on the invention.

Claims (10)

1. An R-2R digital-to-analog conversion trimming calibration circuit, comprising: an R-2R circuit and a trimming and calibrating circuit;
The R-2R circuit comprises a resistor main circuit and n identical resistor branches, the resistor main circuit comprises n-1 main circuit resistors R which are connected in series, one end of the resistor main circuit is an output end V out, and two ends of each main circuit resistor R are coupled with one resistor branch; the resistor branch comprises a branch resistor 2R and a switch, one end of the branch resistor 2R is connected with one end of the main resistor R, and the other end of the branch resistor 2R is connected with a first reference voltage V REFH or a second reference voltage V REFL through the switch; the switches of the n resistor branches are respectively connected with the first reference voltage V REFH or the second reference voltage V REFL according to n-bit input signals;
The trimming and calibrating circuit comprises a plurality of identical trimming branches which are connected in parallel, and one end of each trimming branch is connected with the other end of the resistor main circuit; the trimming branch circuit comprises a plurality of trimming resistors connected in series and a trimming switch; one end of the series-connected trimming resistors is connected with the other end of the resistor main circuit, and the other end of the series-connected trimming resistors is connected with the first reference voltage V REFH or the second reference voltage V REFL through a trimming switch; the trimming switches of the trimming branches are respectively connected with the first reference voltage V REFH or the second reference voltage V REFL according to multi-bit trimming control signals, the number of which is the same as that of the trimming branches.
2. The R-2R digital to analog conversion trimming calibration circuit according to claim 1, wherein the number of trimming branches is 2;
The resistance value of each trimming branch after a plurality of trimming resistors are connected in series is twice the resistance value of the branch resistor 2R.
3. The R-2R digital to analog conversion trimming calibration circuit according to claim 1, wherein the number of trimming branches is 4;
the resistance value of each trimming branch after a plurality of trimming resistors are connected in series is four times of the resistance value of the branch resistor 2R.
4. An R-2R digital-to-analog conversion trimming and calibrating circuit is characterized by comprising an R-2R circuit and a trimming and calibrating circuit;
The R-2R circuit comprises a resistor main circuit, n-1 identical resistor branches and a standard resistor, one end of the standard resistor is connected with one end of the resistor main circuit, and the other end of the standard resistor is connected with a second reference voltage V REFL; the resistor main circuit comprises n-1 main circuit resistors R which are connected in series, and the other end of the resistor main circuit is an output end V out; the resistor branch comprises a branch resistor 2R and a switch, one end of the branch resistor 2R is connected with one end of the main resistor R, and the other end of the branch resistor 2R is connected with a first reference voltage V REFH or a second reference voltage V REFL through the switch; the main circuit resistor R close to the standard resistor is used as a first main circuit resistor R, one end, far away from the output end V out, of the first main circuit resistor R is coupled with a resistor branch, one end, close to the output end V out, of the second main circuit resistor R in the main circuit resistor R is coupled with a resistor branch, and two ends of the third to n-1 main circuit resistors R in the main circuit resistor are coupled with a resistor branch;
The trimming calibration circuit comprises a plurality of identical trimming branches connected in parallel, wherein each trimming branch comprises a plurality of trimming resistors connected in series and a trimming switch; one end of each of the series-connected trimming resistors is coupled to a connection point of a first main circuit resistor R and a second main circuit resistor R in the resistor main circuit, and the other end of each of the series-connected trimming resistors is connected with a first reference voltage V REFH or a second reference voltage V REFL through a trimming switch; the trimming switches of the trimming branches are respectively connected with the first reference voltage V REFH or the second reference voltage V REFL according to multi-bit trimming control signals, the number of which is the same as that of the trimming branches.
5. The R-2R digital to analog conversion trimming calibration circuit according to claim 4, wherein the number of trimming branches is 4;
the resistance value of each trimming branch after a plurality of trimming resistors are connected in series is four times of the resistance value of the branch resistor 2R.
6. An R-2R digital-to-analog conversion trimming and calibrating circuit is characterized by comprising an R-2R circuit and a trimming and calibrating circuit;
The R-2R circuit comprises a resistor main circuit, n-1 identical resistor branches and a standard resistor, wherein one end of the standard resistor is connected with one end of the resistor main circuit, and the other end of the standard resistor is connected with a first reference voltage V REFH; the resistor main circuit comprises n-1 main circuit resistors R which are connected in series, and the other end of the resistor main circuit is an output end V out; the resistor branch comprises a branch resistor 2R and a switch, one end of the branch resistor 2R is connected with one end of the main resistor R, and the other end of the branch resistor 2R is connected with a first reference voltage V REFH or a second reference voltage V REFL through the switch; the main circuit resistor R close to the standard resistor is used as a first main circuit resistor R, one end, far away from the output end V out, of the first main circuit resistor R is coupled with a resistor branch, one end, close to the output end V out, of the second main circuit resistor R in the main circuit resistor R is coupled with a resistor branch, and two ends of the third to n-1 main circuit resistors R in the main circuit resistor are coupled with a resistor branch;
The trimming calibration circuit comprises a plurality of identical trimming branches connected in parallel, wherein each trimming branch comprises a plurality of trimming resistors connected in series and a trimming switch; one end of each of the series-connected trimming resistors is coupled to a connection point of a first main circuit resistor R and a second main circuit resistor R in the resistor main circuit, and the other end of each of the series-connected trimming resistors is connected with a first reference voltage V REFH or a second reference voltage V REFL through a trimming switch; the trimming switches of the trimming branches are respectively connected with the first reference voltage V REFH or the second reference voltage V REFL according to multi-bit trimming control signals, the number of which is the same as that of the trimming branches.
7. The R-2R digital to analog conversion trimming calibration circuit according to claim 6, wherein the number of trimming branches is 4;
the resistance value of each trimming branch after a plurality of trimming resistors are connected in series is four times of the resistance value of the branch resistor 2R.
8. A digital to analog conversion chip, comprising:
A substrate and an R-2R digital-to-analog conversion trimming calibration circuit as defined in any one of claims 1-3 formed on said substrate.
9. A digital to analog conversion chip, comprising:
a substrate and an R-2R digital-to-analog conversion trimming calibration circuit as claimed in any one of claims 4 to 5 formed on said substrate.
10. A digital to analog conversion chip, comprising:
A substrate and an R-2R digital-to-analog conversion trimming calibration circuit as defined in any one of claims 6-7 formed on said substrate.
CN202322732459.8U 2023-10-11 2023-10-11 R-2R digital-to-analog conversion trimming and calibrating circuit and digital-to-analog conversion chip Active CN220964860U (en)

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