CN218499127U - Digital-to-analog conversion circuit structure - Google Patents
Digital-to-analog conversion circuit structure Download PDFInfo
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- CN218499127U CN218499127U CN202222788076.8U CN202222788076U CN218499127U CN 218499127 U CN218499127 U CN 218499127U CN 202222788076 U CN202222788076 U CN 202222788076U CN 218499127 U CN218499127 U CN 218499127U
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Abstract
The utility model belongs to the technical field of the digital analog conversion, concretely relates to digital analog conversion circuit structure makes up into high resolution DAC of the same kind by two way low resolution DAC, can use two way low resolution DAC, through the mode that increases simpler hardware circuit, and corresponding software configuration of reunion can realize high resolution DAC of the same kind with relatively lower cost combination, really realizes the promotion of DAC resolution ratio. Theoretically, the utility model discloses the highest DAC that can make up two way N position into 2X (N-1) bit's DAC of the same kind. A digital-to-analog conversion circuit structure comprising: two pieces of DAC, or a piece of DAC of two channels, every DAC or every channel of DAC respectively connect a resistance in series, two resistances are connected in parallel and then are electrically connected with the summation circuit. The utility model discloses use high slew rate's low resolution DAC model, can realize the analog signal output of super high slew rate and high resolution.
Description
Technical Field
The utility model belongs to the technical field of digital-to-analog conversion, concretely relates to digital-to-analog conversion circuit structure makes up into high resolution DAC of the same kind by two way low resolution DAC.
Background
A digital-to-analog converter: the converter is a converter for converting discrete signals in the form of binary digital quantities into analog quantities based on standard quantities (or reference quantities), and is called DAC or D/a converter for short. This is referred to as DAC in the present invention.
Resolution of the digital-to-analog converter: refers to the ratio of the minimum output voltage (only the least significant bit of the corresponding input digital quantity is "1") to the maximum output voltage (all the significant bits of the corresponding input digital quantity are "1"). For example, an N-bit DAC, with a resolution of 1/(2 ^ N-1). In practical use, the method for representing the resolution of the DAC is also represented by the number of bits of the input digital quantity. The larger the number of bits of the digital-to-analog converter is, the smaller the resolution value is, and the higher the resolution of the digital-to-analog converter is.
Conversion rate of digital-to-analog converter: the DAC conversion speed is generally determined by the setup time. This time, called the settling time, is the maximum response time of the DAC, and is therefore a measure of how fast the DAC slew rate is, starting when the input abruptly changes from all 0's to all 1's until the output voltage settles within the FSR 1/2LSB range (or the range indicated by FSR x% FSR).
In the design of instruments, DACs have been widely used as key devices necessary for the conversion of digital and analog values. With the improvement of signal output precision and processing rate, the requirements on the resolution (bit number) and conversion rate of the DAC, which is a key device, are continuously increased.
Most of the DAC devices in the market are produced by international companies at present, the selling price is higher, especially the DAC with high resolution and high conversion rate is limited to export by foreign companies to a certain extent, for example, the DAC with more than 20 bits is difficult to buy. How to obtain a DAC with high resolution and high conversion rate without greatly increasing the economic cost becomes a technical problem to be solved urgently.
At present, there is almost no particularly good method for realizing higher resolution of DAC, and in the instrument, generally, the number of words of DAC resolution is fixed, and only by adding hardware shift switching on the analog signal end to reduce the range, or reduce the reference voltage, etc., can a relatively high resolution be obtained in the low voltage range. In the prior art, the principle is the same whether the measuring range is reduced or the reference voltage is reduced, the resolution of the DAC is not improved, and only the voltage difference between two adjacent words is reduced under the original resolution, so that the real resolution of the DAC cannot be improved.
SUMMERY OF THE UTILITY MODEL
In order to solve the technical problem, the utility model provides a digital-to-analog conversion circuit structure, the circuit structure who makes up into high resolution DAC of the same kind by two way low resolution DAC, can use two way low resolution DAC, through the mode that increases simpler hardware circuit, and corresponding software configuration is reunited, can realize high resolution DAC of the same kind with relatively lower cost combination, really realizes the promotion of DAC resolution ratio. Theoretically, the utility model discloses the highest low resolution DAC with two way N bits that can make up into the high resolution DAC of 2 x (N-1) bits of the same kind.
The utility model discloses the technical scheme who adopts as follows:
a digital-to-analog conversion circuit structure comprising: two pieces of DAC, or a piece of DAC of two channels, every DAC or every channel of DAC respectively connect a resistance in series, two resistances are connected in parallel and then are electrically connected with the summation circuit.
Preferably, the DAC is a voltage-type DAC.
Preferably, the method comprises the following steps: the high-voltage DAC1 (H) is connected with a first resistor R1 in series, the low-voltage DAC2 (L) is connected with a second resistor R2 in series, the first resistor R1 and the second resistor R2 are electrically connected with a positive input end of an operational amplifier after being connected in parallel, a negative input end of the operational amplifier is connected with an output end, V-REF is connected with Vrefin, the V-REF is a reference voltage signal input by an external reference voltage source, the Vrefin is a reference voltage input pin of a DAC chip, LDAC is an output loading signal, and Vout is an analog voltage output pin of the DAC chip.
Preferably, the DAC is a current-mode DAC, and further includes a voltage conversion circuit configured to the current-mode DAC.
Preferably, the summing circuit is a differential circuit, a polarity conversion circuit, or a scaling circuit.
The utility model has the advantages that:
the high resolution DAC (> 16 bits) is much more expensive than the conventional low resolution DAC (12 bits and less), and if the conversion rate has higher requirement, the cost is very high, even no purchase channel is available. The digital-to-analog conversion circuit structure provided by the utility model can realize the DAC output with high resolution by using lower cost; at present, the DAC of low resolution ratio still has the model of many super high conversion rate, uses the utility model provides a digital-to-analog conversion circuit structure cooperates the low resolution ratio DAC model of high conversion rate, can realize the analog signal output of super high conversion rate and high resolution ratio.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It should be apparent that the drawings in the following description are illustrative of some embodiments of the invention and that other drawings may be derived by those skilled in the art without inventive step from these drawings, and are within the scope of the present application.
Fig. 1 is a schematic diagram of a digital-to-analog conversion circuit structure according to a first embodiment of the present invention.
Detailed Description
The technical solution of the present invention will be described clearly and completely with reference to the accompanying drawings, and obviously, the described embodiments are some, but not all embodiments of the present invention.
Example one
As shown in fig. 1, which is a schematic diagram of a digital-to-analog conversion circuit structure according to an embodiment of the present invention, the first embodiment takes two voltage DACs as an example for description. The DAC comprises two voltage type DACs which are respectively responsible for converting a high-stage part and a low-stage part of data to be converted, DAC1 (H) is the high-stage voltage type DAC, DAC2 (L) is the low-stage voltage type DAC, V-REF is connected with Vrefin, V-REF is a reference voltage signal input by an external reference voltage source, vrefin is a reference voltage input pin of a DAC chip, LDAC is an output loading signal, vout is an analog voltage output pin of the DAC chip, R1 is a first resistor, R2 is a second resistor, and DAC-OUT is output voltage.
A digital-to-analog conversion circuit structure comprising: the high-voltage DAC1 (H) is connected with a first resistor R1 in series, the low-voltage DAC2 (L) is connected with a second resistor R2 in series, the first resistor R1 and the second resistor R2 are connected with a positive input end of the operational amplifier in parallel, and a negative input end of the operational amplifier is connected with an output end.
The embodiment of the utility model provides an in, two voltage type DAC require to have shared reference voltage, and operational amplifier is used for summating.
The following description of the operating principle of a digital-to-analog conversion circuit structure according to the first embodiment of the present invention is as follows, taking the example of combining two 12-bit DACs (low resolution) into one path of 18-bit DAC (high resolution):
first, the first embodiment of the present invention sets a targeted 18-bit binary number XX XXXX xyyyy YYYY, where each bit X and Y may be 0 or 1. The reason why the upper 7 bits of the 18 bits are replaced by X and the lower 11 bits by Y: in the design, theoretically, after two paths of N-bit low-resolution DACs are combined, only one path of 2 x (N-1) -bit new high-resolution DAC can be formed at most, that is, after two paths of 12-bit DACs are combined, each path can only use 11 bits at most; therefore, for convenience of description, the first embodiment of the present invention uses X and Y to refer to the upper 7 bits and the lower 11 bits of the 18-bit binary number of the target, respectively.
According to the formula of DAC conversion, the embodiment of the present invention is that the voltage value of the final output is expected to satisfy the following format:
the embodiment of the utility model provides a first 18 bit binary numbers that need cut into in software the target are no longer than two parts of 11 bits, are high section part and low section part respectively. Although there are theoretically many different ways for the allocation of two fractional bits, this is not the caseThe same distribution mode can affect the resistance R of the subsequent summation circuit 1 And R 2 The ratio of the two resistances is larger when the high-stage bit number is larger. And in practical application, the impedance difference of two way inputs among the summation circuit is too big can improve the performance requirement to operational amplifier, consequently for reducing the resistance difference, the embodiment of the utility model provides a principle of 18 bit binary numbers cutting of a pair of target is that low-section bit number is as much as possible, and final definite is high 7 and low 11:
the two numbers are then recombined in the following manner to form two new 12-bit binary numbers, referred to as D1 and D2:
D1＝[0XXX XXXX 0000] 12
D2＝D1+[YYY YYYY YYYY] 11
＝[0XXX XXXX 0000] 12 +[0YYY YYYY YYYY] 12
wherein, D2 is obtained by summing up 2 12-bit binary numbers with the most significant bit being 0, and the bit number thereof is less than or equal to 12 bits.
The writing method of the binary number D1 is changed into a scientific counting method, and the highest bit 0 is defaulted, so that the following form can be written:
D1＝[0XXX XXXX 0000] 12 ＝[XXXXXXX] 7 ×2 4
meanwhile, D2 may also be modified to the following form:
D2＝[XXX XXXX] 7 ×2 4 +[YYY YYYY YYYY] 11
d1 and D2 obtained by the above formula are input to DAC1 (H) and DAC2 (L), respectively.
According to the output voltage calculation formula of the 12-bit DAC:
the output voltages V of the two paths of DACs can be respectively calculated DAC1 And V DAC2 ：
In FIG. 1, the resistor R 1 、R 2 And the operational amplifier forms a voltage summation circuit, and the following voltage summation formula is satisfied:
substituting the actual selected resistance proportion:
R 2 ＝(2 7 -1)×R 1
obtain the final output voltage V DAC_OUT The calculation formula of (2):
v to be calculated before DAC1 And V DAC2 Substituting the formula to obtain:
wherein the content of the first and second substances,
[XXX XXXX] 7 ×2 11 ＝[XX XXXX X000 0000 0000] 18
[XX XXXX X000 0000 0000] 18 +[YYY YYYY YYYY] 11
＝[XX XXXXXYYY YYYY YYYY] 18
it can be seen that the original 18-bit binary number is completely reduced.
Finally, the embodiment of the present invention can write the output voltage of the whole circuit into the following form:
it can be seen from the calculation that the final output voltage value of the whole circuit is almost the same as the output voltage formula of the 18-bit DAC, and only the initial input voltage is actually halved compared with the reference voltage. That is, the circuit successfully performs the function of an 18-bit DAC with half the output range.
And theoretically, the utility model discloses the highest can expand two way 12 bit DACs to 22 bits.
Similarly, a high-resolution DAC that has undergone one-time combination is considered as a whole, and then the next combination is performed in the same manner, so that a combined DAC with a higher resolution can be obtained theoretically.
The utility model discloses can use two digit numbers to be the voltage type DAC of N, the digital analog conversion of an S bit binary number is realized in the combination, and wherein N < S is less than or equal to 2 x (N-1).
The resistance ratio of the first resistor R1 and the second resistor R2 meets the requirement:
R 2 ＝(2 S-N+1 -1)×R 1
the S-bit binary number of the target is decomposed and processed into two N-bit binary numbers for the two-slice DAC in the following manner:
taking out the higher S- (N-1) bit of the target S-bit binary number, sequentially placing the higher S- (N-1) bit in (N-2) bit of an N-bit binary number and the adjacent lower bits thereof from the higher S bit to the lower S bit, and then adding 0 to both the highest S bit and the vacant lower bits to obtain an N-bit binary number D1 for the high-section voltage type DAC:
D1＝[0 X…X 0…0] Ⅳ
wherein, X \8230, X 'represents the high-order number of the target value, the number of the order is S- (N-1), and the number of the low-order 0 \82300' is 2 (N-1) -S.
Taking out the lower N-1 bit of the target S binary number, adding 0 to the highest bit to form an N-bit binary number, and summing the N-bit binary number with the N-bit binary number D1 to obtain an N-bit binary number D2 for the low-stage DAC:
D2＝D1+[0Y…Y] Ⅳ ＝[0 X…X 0…0] Ⅳ +[0 Y…Y] Ⅳ
wherein, Y \8230, Y represents the low-order number in the target value, the number of bits is N-1, because the highest bit of two binary numbers used for summation in D2 is '0', D2 is still N-bit binary number without overflow.
The method for cutting the target binary number and the method for calculating the resistance are the prior art or the conventional technical means in the technical field.
Example two
Compared with the first embodiment, compare two voltage type DAC for two current type DAC and supporting voltage conversion circuit, what current type DAC output pin exported is current signal, can't directly use in this circuit, need cooperate DAC producer's recommended voltage conversion circuit to turn into voltage signal with it and just can access after the follow-up circuit of the utility model embodiment one. Other embodiments are the same as the first embodiment.
EXAMPLE III
In the third embodiment, compared with the first embodiment, two pieces of voltage-type DACs are replaced by one piece of two-channel voltage-type DAC, and two channels of the voltage-type DAC are respectively connected with resistors in series.
Example four
In a fourth embodiment, compared with the first embodiment, the operational amplifier is replaced by a summation circuit with other functions, such as a differential circuit, a polarity conversion circuit, a scaling circuit, etc., and other embodiments are the same as the first embodiment.
The utility model discloses a four above-mentioned embodiments choose for use two voltage type DAC, perhaps choose for use two current mode DAC, perhaps choose for use the voltage type DAC of a slice two passageways, perhaps choose for use the summation circuit of other functions, all can realize the analog signal output of super high conversion rate and high resolution through the combination of low resolution DAC.
In the embodiment of the present invention, the technical features not described in detail are prior art or conventional technical means, and are not described herein again.
Finally, it is to be noted that: the above embodiments are only specific embodiments of the present invention, and are not intended to limit the technical solutions of the present invention, and the scope of the present invention is not limited thereto. Those skilled in the art will understand that: modifications of the embodiments described above or variations thereof, or equivalent substitutions of parts of the technical features, which are obvious to those skilled in the art, are possible within the technical scope of the invention disclosed in the preceding claims; such modifications, changes or substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (5)
1. A digital-to-analog conversion circuit structure, comprising: two pieces of DACs or one piece of DAC with two channels are connected with one resistor in series respectively, and the two resistors are connected with the summing circuit after being connected in parallel.
2. The digital-to-analog conversion circuit structure of claim 1, wherein said DAC is a voltage-type DAC.
3. A digital to analog conversion circuit arrangement according to claim 2, comprising: the high-voltage DAC1 (H) is connected with a first resistor R1 in series, the low-voltage DAC2 (L) is connected with a second resistor R2 in series, the first resistor R1 and the second resistor R2 are connected with a positive input end of an operational amplifier in parallel and then electrically connected, a negative input end of the operational amplifier is connected with an output end, V-REF is connected with Vrefin, V-REF is a reference voltage signal input by an external reference voltage source, vrefin is a reference voltage input pin of a DAC chip, LDAC is an output loading signal, and Vout is an analog voltage output pin of the DAC chip.
4. The digital-to-analog conversion circuit structure of claim 1, wherein the DAC is a current-mode DAC, and further comprising a voltage conversion circuit associated with the current-mode DAC.
5. A digital-to-analog conversion circuit arrangement according to claim 1, wherein said summing circuit is a differential circuit, or a polarity conversion circuit, or a scaling circuit.
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