JPS6235707B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention replaces a memory element with a random failure location with another memory element of the same type,
The present invention relates to a storage device that creates a mapping address conversion table prior to a predetermined use of the storage device.

Since it is uneconomical to discard large-capacity memory elements that contain only a few defects that occur during the manufacturing stage and are mostly still operational, we are using hardware to eliminate the A memory device that can be used by appropriately combining defective memory elements has been proposed.

For example, if you look at a memory element two-dimensionally and divide the memory area into four parts, as shown in Fig.
Prepare pieces Ma, Mb, Mc, Md. An address conversion table ATT is provided so that defective locations Pa, Pb, Pc, and Pd of the unit memory portions of each memory element called memory cells can be replaced by other memory elements. In other words, conceptually speaking, when the address of Pa is accessed, the address translation table ATT converts the address into the memory element Md.
Convert to ARb address and access there. In the figure, both addresses are shown connected by white arrows for intuitive representation. In this way, the four partially defective devices are combined to form one storage device with a capacity of 3 bits. In this case, the address conversion table ATT uses ROM or
It is a fixed conversion using logic circuits.

However, defective locations in the memory element rarely fall within only one of the four divided ranges, but often fall within other ranges or exist throughout the area, that is, randomly. For this reason, it has been proposed to bring in a completely good device separately from a defective device and to provide an address conversion table so that the defective position can be exchanged and corresponded to any position of the good device. When manufacturing a memory element, a conversion table corresponding to a random fault location is created using a logic element or ROM. The conventional techniques described above have several drawbacks as described below.

Of the methods mentioned above, the former method cannot be combined unless the defective position of the memory element is properly located within the divided range, while the latter method allows randomly occurring defective positions to be detected without error at each stage of manufacturing the memory element and memory card. It is necessary to understand the fault location and write the conversion table without error, which differs for each storage element. The task is complex. Furthermore, if a new failure occurs while the storage device is in use, the storage device will generate an error unless the conversion table is rewritten, and it will be powerless against the new failure in the field. Furthermore, when it becomes necessary to replace a part that breaks the above-mentioned address correspondence relationship at the site of use, it is necessary to create a new conversion table that corresponds to the new part, or to replace the part with a perfectly good product without any defects. be.

The purpose of the present invention is to eliminate the above-mentioned drawbacks, and to make it possible to use the storage device without having to write or create an address conversion table during the initial manufacturing stage of the storage device using a storage element that has random failure points. An object of the present invention is to provide a storage device for creating a pre-address conversion table.

Another object of the present invention is to automatically select addresses at which alternative memory elements can operate normally even if they are good or contain random failures;
The object of the present invention is to provide a storage device that can be automatically associated with a failed address to be replaced.

In order to achieve the object of the present invention, the present invention particularly provides an address scanner 2 capable of generating addresses for testing whether normal memory elements and alternative memory elements operate normally.
The device is equipped with a set of data generators, two sets of data generators for the storage elements, and a test/control circuit for testing read data, and performs tests prior to use and automatically creates an address conversion table.

Embodiments of the present invention shown in the drawings will be described below. FIG. 2 is a block configuration diagram showing an embodiment of the present invention.MEM-N is a memory element mainly used, which has random failure locations, and is hereinafter referred to as a normal memory element in this specification. . MEM―
A is an alternative memory element, and may be a good product that has the same type of configuration as a normal memory element (for example, a semiconductor memory element) and may or may not include randomly occurring failure points. The minimum acceptable capacity usually corresponds to the number of failed addresses in the memory element. ATT is an address conversion table, and ADS-N is a normal address scanner that generates an address when testing the normal memory element MEM-N.
It is input to the N address conversion table ATT. ADS―
A is an alternate address scanner and an alternate memory element.
Generates addresses, etc. when testing MEM-A. WDR-N is normally a write data generator and usually generates data when testing MEM-N. WDR-N is an alternative write data generator and generates data when testing alternative memory element MEM-A. WDR-N is address conversion table
The register for writing data to ATT is shown. RDR―
N is a register that stores read data from the normal memory element MEM-N, RDR-A is an alternative memory element
RDR-T is a register that stores read data from MEM-A, and RDR-T is a register that stores read data from address conversion table ATT. CHK is inspected and
This is a control circuit that checks the read data of the normal memory element MEM-N and the alternative memory element MEM-A, and issues a control signal to proceed with a predetermined operation based on the check results.As a check circuit, it is used as a parity check. A circuit, a comparison circuit for each bit, a detection circuit using a Hamming code, etc. is used as appropriate. The CPU is a central processing unit, and the ASC is an address switching circuit that switches and outputs an address accessed from the central processing unit and an alternative address to an alternative memory element. Normal memory element MEM-N and alternative memory element MEM
- A and the write data generation circuit WDR-N in advance.
Write the specified data and location from WDR-A. Then, power is turned on to the storage device including each memory element, address conversion table, etc., and the central processing unit CPU, and before using the system, an address conversion table is created as shown below. FIG. 3 shows a flowchart for creating an address conversion table. First, the normal address scanner ADS-N is a normal memory element.
Generate address = 0 (N system address) for MEM-N. Data read from the normal memory element MEM-N is stored in the register RDR-N and checked by the inspection/control circuit CHK. If there is no error as a result of the check in the inspection/control circuit CHK, the address in the address conversion table ATT = 0 (N
The write data register indicates that the memory element MEM-N is valid (V = “1”) in the write data register (system address).
Write using WDR-T. FIG. 4 is a schematic diagram showing the structure of a memory element and an address table. FIG. 4A shows a conventional storage element. In Figure 4A, the N system address = 0 is normal, and the same address in the address conversion table shown in Figure 4B is set to V = "1".
shall be. Next, the normal address scanner ADS-N increments the address by 1 under the control of the inspection/control circuit CHK and generates address 1 (N-system address).
The scanner ADS-N is equipped with a maximum address discrimination circuit, and the newly generated address is normally stored in the memory element.
If it is the maximum address of MEM-N, the creation of the failure check/address conversion table ATT is completed, and this is notified to the inspection/control circuit CHK. When the maximum address control circuit does not operate, the data at the new address is read out in the same manner as described above, and the inspection/control circuit operates. If an error is detected during this process, the inspection/control circuit CHK generates an alternative address = 0 (A system address) to the alternative address scanner ADS-A, and transfers it to the alternative memory element MEM-A.
and address conversion table data register WDR-T
Enter. As a result, the read data from the alternative memory element MEM-A is stored in the register RDR-A and checked by the test/control circuit CHK. When there is no error, the cell at the address = 0 (A-system address) in the alternative memory element MEM-A is found to be normal, so the address N in the address conversion table is determined to be normal.
Write {V=0, A system address=0} in the area of system address = 1, then write the normal address scanner ADS-
Add 1 to the address of N and continue. FIG. 4C is a diagram showing an outline of the alternative memory element MEM-A, and shows that the A-system address "B" is written in the address A of the address conversion table and is replaced when necessary.

If an error is detected in the read data from the alternative memory element MEM-A, the inspection/control circuit
CHK generates an address that is +1 step higher than the alternative address scanner ADS-A, and that is the alternative memory element.
As long as it is not the maximum address of MEM-A, the inspection/control circuit CHK is checked and the address is incremented until a cell in a normal state is found. If the alternative address scanner ADS-A generates the maximum address before the creation of the address conversion table ATT is completed (the test of the maximum address of the normal memory element is finished as described above), the alternative memory element MEM -A is a “normal memory element”
Since it is not worthy of being used as a replacement for MEM-N, it will be necessary to replace it completely or to handle abnormalities such as adding other elements. In this way, the memory element
The normal memory element is used to create an address conversion table while checking whether each cell of MEM-N and alternative memory element MEM-A is normal or abnormal.
The fault address in MEM-N is replaced by an alternative memory element MEM-A.
This means that the correspondence with the normal address has been established. This correspondence can be easily handled by creating a new address conversion table even when a new failure is discovered during information processing operation or when parts are replaced that break the correspondence.

Next, from the central processing unit CPU to the normal memory element MEM
- Explain the case of accessing N.

The address information A to C from the central processing unit CPU first accesses the address conversion table ATT and reads the data set at the address {V, A system address}.
is read to the read data register RDR-T. The address switching circuit ASC looks at the data in the register RDR-T, and when V="1", the address information AC is passed through and the normal storage element MEM-N is accessed. When V = “0”, the A system address is cut off and the data A system address of the read data register RDR-T is output, and in that case, the data A system address of the read data register RDR-T is output, and in that case, the data A system address of the read data register RDR-T is output.
access.

In addition, as an address conversion table, a normal logic element,
The same thing can be done even if an associative memory element or the like is used. In order to reduce the number of entries in the address conversion table ATT, it is also possible to ignore the address specifying the memory cell and convert only a part of the address, such as an address specifying the chip. Furthermore, it is natural that the hardware of the apparatus can be reduced by using a good quality substitute memory element, and various other modifications can be made without departing from the spirit of the present invention.

In this way, according to the present invention, instead of creating an address conversion table at the stage of manufacturing a storage device, it is sufficient to create the address conversion table prior to using the storage device for information processing operations, for example, immediately after power is turned on. Any failure that occurs during operation can be dealt with immediately. The alternative memory element may be a good product or one with random failures, so by providing an alternative memory element, the overall storage device does not become expensive or bulky, and on the contrary, it can be discarded. This means that products that are considered defective can be used. In addition, by selecting a slightly larger capacity for the defective memory element to be used, it is possible to configure a memory device with a predetermined memory capacity or more from memory elements containing random failures, and then selectively access only the normal cells among them. I can do it. It is extremely effective in practice to be able to immediately rewrite the table even if the user replaces parts that disrupt the correspondence of the address conversion table in use.

[Brief explanation of the drawing]

Fig. 1 is a conceptual diagram of the configuration of a storage device using a conventional address conversion table, Fig. 2 is a block configuration diagram showing an embodiment of the present invention, and Fig. 3 is an operation when creating the address conversion table of the present invention. flowchart,
FIG. 4 is a schematic diagram showing the structure of a normal memory element, an address conversion table, and an alternative memory element of the present invention. Ma, Mb, Mc, Md...Memory element, ATT...Address conversion table, MEM-N...Normal memory element,
MEM-A...Alternative memory element, ADS-N...Normal address scanner, ADS-A...Alternative address scanner, WDR-N...Normal write data generator, WDR
-A...Alternative write data generator, CHK...Test/control circuit.

Claims (1)

[Scope of Claims] 1. In a storage device in which a faulty address of a storage element in which faulty locations are randomly located is switched to a normal address by hardware, a normal storage element in which a random fault occurs, and the same as the normal storage element. an address conversion table that associates a faulty address in a normal memory element with a normal address in an alternative memory element, and a normal address scanner and an alternative address scanner that generate read/write addresses for each memory element. , a normal write data generator and an alternative write data generator that generate write data to each memory element, and a detection/control unit that checks the normality of the read data and instructs the next operation based on the check result. The memory is characterized in that, prior to use of the memory device, the memory device completes the creation of the address conversion table while testing the normality of operation of the normal memory element and the alternative memory element, and starts communication with the central processing unit. Device.