JPS6234418A - Developing method for detailed logic circuit - Google Patents

Abstract

PURPOSE:To minimize the signal delay time of a specific path by minimizing the fan-out of signal lines on the specific path at the stage where the function logic expressed by a Boolean algebra expression is developed, gate by gate, into detailed logic circuits. CONSTITUTION:A gate 51 is interposed between a gate 22 and gates 25-27 so as to minimize the fan-out of signal lines passed through the specific path. Consequently, the fan-out of the gate 22 is decreased from four to two and the delay time due to the input pin capacity of the gate is shortened. Consequently, the signal delay time of the path of gates 21-28 is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for automatically generating a logic circuit, and more particularly to a method for developing functional logic expressed in Boolean algebraic expressions into detailed logic circuits configured in units of gates.

[Background of the invention]

In order to quickly develop logic devices such as large-scale computers, it is necessary to avoid introducing delay defects in the pre-design process.

By the way, when designing logic devices, it is rare to directly design detailed logic circuits.

First, a functional logic diagram is created, and an automatic logic circuit design device is used to automatically develop it into a detailed logic circuit with the support of a program. At that time, the problem is
The problem is that the developed detailed logic circuit contains delay defects.

Conventionally, a method for automatically generating detailed logic circuits for each gate from functional logic by taking delay and delay time into consideration is the "IBM J Res Development" (IBM J
, RES DEVELOP) (September 1984, 28
Vol. 5), Johnnie Dellinger (John A.
Darringer et al.
SS: A System for pr.

ducI + ion logic 5 synthesis)
The method discussed under the title is known. However, this method checks whether the number of gate stages of the path satisfies the allowable number of stages, and if it exceeds the allowable number of stages, the number of logic stages is reduced to the minimum, focusing on paths where delay time is critical. , no consideration is given to developing functional logic into detailed logic circuits for each gate so that the signal delay time of the path is minimized.

[Purpose of the invention]

An object of the present invention is to provide a method for minimizing the signal delay time of a designated bus when developing functional logic expressed in Boolean algebraic expressions into a detailed logic circuit composed of gates.

[Summary of the invention]

The present invention minimizes the signal delay time of a specific path by minimizing the number of fanouts of signal lines on a specific path at the stage of developing functional logic expressed in Boolean algebraic expressions into detailed logic circuits for each gate. It is something to do.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 3 shows an example of functional logic written in Boolean algebraic expressions. 1 indicates a flip-flop serving as a starting point, and numbers 8 to 1 indicate flip-flops serving as an ending point. 2 to 7 indicate functional logic boxes expressed by Boolean algebraic expressions. When the functional logic expressed by the Boolean algebraic expression in FIG. 3 is developed into gate logic, it becomes as shown in FIG. 4. Here, flip-flop 1 in FIG. 3 corresponds to flip-flop 21, functional logic boxes 2-7 correspond to gates 22-27, and flip-flops 8-11 correspond to flip-flops 28-31, respectively.

FIG. 1 shows an embodiment of the present invention, and in FIG. 3, the functional logic when an instruction is given to minimize the signal delay time of the bus between the start point flip-flop 1 and the end point flip-flop 8 is shown. An example of expansion into gate logic is shown, in which a gate 51 is inserted between gate 22 and gates 25 to 27 in order to minimize the fan-out number of signal lines passing through a designated bus. As a result, the number of fanouts of the gate 22 is reduced from 4 to 2, and the delay time due to the input pin capacitance of the gate is reduced. As a result, the signal delay time of buses 21 to 28 is shortened.

FIG. 2 shows another embodiment of the present invention, in which two paths 1 to 8 and 1 to 11 in FIG. 3 are designated as buses that minimize signal delay time. In FIG. 2, 52 is a newly inserted gate, and for buses 21 to 28 and buses 21 to 31, which are the buses that minimize the delay time, the output of gate 22, which is a gate shared by both paths. The signal is sent directly to the gate 23.2 without passing through the insertion gate 52.
Give to 7. That is, the fanout number of gate 22 is reduced from 4 to 3 as shown in FIG.

The delay times of buses 21-28 and buses 21-31 are minimized.

FIG. 5 is a flowchart showing the procedure of the detailed logic expansion method according to the present invention, and FIGS. 6 to 9 are flow charts showing the detailed processing of the detailed logic expansion method shown in FIG. This shows the case of expansion.

First, the functional logic is developed into a detailed logic circuit (step 60), and a tree structure table shown in FIG. 6 is created. Now, for steps 21 to 3, create a column table for the specific bus for which you want to minimize the primary signal delay time corresponding to 21 to 31 in Figure 4, respectively.Step 61), and enter the specific bus in the - column table. Fill in the route indicating each signal line above (step 62
). FIG. 7 shows a list of specific buses and a route table.

Next, the first specific bus is extracted (step 63), and one signal line on the extracted specific bus is extracted (step 6).
4). Next, a gate is inserted to minimize the fanout number of the signal line extracted in step 64, and the tree structure table is updated (step 65). At this time, a gate is inserted to minimize the fanout number of the extracted signal line. If a gate has already been inserted, the logical connection (tree structure table) is updated so that it does not go through that insertion gate. In this way, steps 64 and 65 are repeated until all signal lines of one specific bus have been processed (step 66).

FIG. 8 shows an updated tree structure table in which bus 1 in FIG. 7 is extracted and the delay time of its routes 21 to 28 is minimized.

Next, the second specific path is extracted and the processes of steps 64 and 65 are repeated. In step 64, if a gate has already been inserted into the extracted signal line to minimize the number of fan-outs, the logical connection is updated so as not to go through the inserted gate.

FIG. 9 shows that after processing the paths 21 to 28 of pass 1 in FIG.
The tree structure after updating is shown for paths 21 to 31 of path 2.

By performing the above processing for all the specific paths in the specific path list, the detailed processing is completed (step 67
).

〔Effect of the invention〕

According to the present invention, it is possible to minimize the signal delay time of a critical path when developing functional logic into detailed logic circuits in units of gates.

[Brief explanation of drawings]

1 and 2 are diagrams showing configuration examples of detailed logic circuits according to the present invention, FIG. 3 is a diagram showing functional logic corresponding to FIGS. 1 and 2, and FIG. 4 is a diagram showing the functions of FIG. 3. FIG. 5 is a flowchart showing the procedure of the method of developing the logic into a detailed logic circuit according to the present invention, and FIGS. 6 to 9 are for explaining the processing in FIG. 5. This is a diagram. 1.21.8-11.28-31...Flip-flop, 3-7...Functional logic written in Boolean algebraic expressions, 22-27...Gate, 51.52...Insertion gate. f-＼ Representative Patent Attorney Katsutoshi Ogawa 1・□・(-Yu,
゛

Claims (1)

[Claims] (1) In a method of developing functional logic expressed in Boolean algebraic expressions into detailed logic circuits in gate units, the fan-out number of signal lines on a specific path is minimized at the stage of development into the detailed logic circuits. 1. A detailed logic circuit development method, characterized in that the signal delay time of the path is minimized by the development.