JPS6234092A - Timer apparatus - Google Patents

Abstract

PURPOSE:To always enable time allotment of a constant ratio to a substantial timer time and to effectively perform the advance control of a conference, by performing the percentage display of the timer time between start time and finish time on a display part on the basis of an advance degree signal. CONSTITUTION:The present time from a timing circuit 100 generating time information is set to start time and, on the basis of this start time and the finish time set by a timer information setting circuit 12, a timer time is calculated by a timer circuit 13. Next, the timer time is converted to percentage data by a percentage operation circuit 14 and the advance degree signal of the timer time is generated on the basis of the percentage data by an advance degree signal generation circuit 15. Further, the percentage display of the timer time between the start time and the finish time is performed on the percentage display parts of display parts 2-7 on the basis of said advance degree signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a timer device, and more particularly to a timer device used for managing the progress of meetings and work hours in the workplace.

[Prior art and problems to be solved by the invention] As is already known, a timer device (hereinafter referred to as a timer)
It is used in all fields. In general, there are two types of timers: one type that is built into a system or product and performs time management functions, and the other type that is commercialized as a single item and used by the user for time management purposes. Most of the former type are so-called composite products that have both a clock function and a timer function, and use a clock to perform the timer function. The audio timer is widely known as a timer that belongs to this category, but it is used by individual users depending on their purpose.Furthermore, the latter type is used for meetings in the workplace and for managing the progress of work time. Timers that are used are also known.These types of timers include table clock types and wall-mounted types, and they display the elapsed time from the start time and sound a buzzer or light a lamp when or just before the set time elapses. This notifies you of the elapse of a predetermined period of time.

However, the timers used to manage the progress of meetings and work are of the type that displays the elapsed time or remaining time moment by moment, so it is difficult to know what percentage of the total time that should be managed has passed. That's difficult. That is,
It is not possible to display elapsed time as a percentage of the total time. Furthermore, it is not possible to display a break time expressed as a percentage between the start time and the end time.

[Means for solving problems]

The present invention provides a timer device that solves the above-mentioned problems, and the means thereof includes a clock circuit that generates time information, a timer information setting circuit that sets the end time of the timer operation, and a current time from the clock circuit. a timer circuit that calculates a timer time based on the start time and an end time set in a timer information setting circuit; a percentage calculation means that converts the timer time into percentage data; It is characterized by comprising a progress signal generating circuit that generates a time progress signal and a display section, and displaying the timer time between the start time and the end time as a percentage on the display section using the progress signal.

〔Example〕

FIG. 1 is a front view of a timer device as an embodiment of the present invention. In FIG. 1, the timer device 1 is shaped like a table clock, is placed in the center of a conference hall or a meeting room, has a display part of an appropriate size that can be recognized even by the last seats, and has a size that is portable. , shall have weight. The timer display section 2 subtracts the elapsed time and digitally displays it in hours and minutes, and is provided near the upper front, and the percentage display section 3 displays the elapsed time as a percentage of the set time. The percentage display section 3 includes a division display section 31 that displays divisions of the allocated time and a progress display section 3 that displays the elapsed time as a percentage.
2, and the progress display section 62 has 60 patterns, with numbers assigned every 10%. Further, the delimiter display section 31 displays K, respectively, corresponding to the 60 patterns. 9 is provided in ~. The time display section 4 is a digital clock and displays the current time. The start time display section 5 digitally displays the start time of the time to be managed by a timer, that is, the time to be managed by a timer, and the end time display section 6 displays the end time. The scale time display section 7 has nine display sections 7a to 71 for displaying the time every 10% of the percentage display section 3. The buzzer 8 is used to notify the user of the elapse of the break time and the end of the time. There are operation buttons at the bottom of the front.

That is, the start button ST starts time counting, and the repeat button RE is used when presentations at the same break time are repeated. The clear button CL is used to clear the set time. The select button SL is used to select the time to be managed, and the set button SE selects the time selected by this button. In addition, the select button SL is 1
Use a type that allows you to select minutes, hours, and separator marks by operating two buttons.

FIG. 2 is a circuit block diagram of the device shown in FIG. 1.

In FIG. 2, 11 is a selection circuit, 12 is a timer information setting circuit, 16 is a timer circuit, 14 is a percentage calculation circuit, 1
5 is a progress signal generation circuit, 16 is a time counter, 17 is an oscillation circuit, 18 is a frequency dividing circuit, 19 is a timer frequency dividing circuit, 2
D is an acoustic drive circuit, 21 is a control signal generation circuit, 22 is a scale time calculation circuit, 100 is a time measurement circuit, which is composed of the oscillation circuit 17, the frequency dividing circuit 18, and the time counter 16, PS, PSE, PSL, PC, and PR are circuits that generate a sole start pulse Ps, set pulse p se1 select pulse p s11 clear pulse Pc1, and repeat pulse pr.

The configuration and functions of the circuit will be explained in detail below.

The timekeeping circuit 100 includes an oscillation circuit 17, a frequency dividing circuit 18, and a time counter 16, and displays hour and minute time information generated by the time counter 16 on the time display section 4.

The timer information setting circuit 12 includes a start time memory 121 for storing a start time and an end time memory 1 for storing an end time.
22, and the start time T set in the start time memory 121 and the end time memory 122 by a method described later.
k and end time T.

is outputted from the Od terminal and displayed on the start time display section 5 and the end time display section B, and is also supplied to the timer circuit 13 and the scale time calculation circuit 22 from the Qm terminal and the O terminal, respectively.

The timer circuit 16 includes a timer memory and a timer counter (not shown). Then, the timer memory stores the start time 'fk and end time T supplied to the terminal Slt.
From o, timer time T is calculated and stored using equation (1).

T2'l' o -'I' k ・
...(1) Then, the timer time T is output from the Od terminal and displayed on the timer display section 2, and l) is supplied from the terminal to the percentage calculation circuit 14, and is further preset to the timer counter. The timer counter performs a subtraction operation based on the clock signal φ0 supplied to the CL terminal, and when the subtraction is completed, the end signal p a is sent from the Qs terminal.
generate s.

When the repeat signal pr is supplied to the Rp terminal after the timer operation ends, the timer time T stored in the timer memory is again preset in the timer counter, resulting in a repeat operation in which a subtraction operation is performed.

When the clear signal pc is supplied to the R terminal, the timer time T set and stored in the timer memory is cleared and the device returns to the initial state.

The scale time calculation circuit 22 calculates the timer time T from the start time Tk and end time To supplied to the terminal 3mt according to the equation (1), and further calculates the time width Tm of one scale by T/10. And this Tm is the start time Tk
By sequentially adding , nine scale times are determined, outputted from terminal Od, and displayed on nine display sections 73 to 7I constituting the scale time display section 7. If the time width Tm of one scale exists in seconds as a result of calculation, it is rounded up or down after 30 seconds and displayed in minutes.

The above series of arithmetic operations are executed by the arithmetic command signal pd generated from the control signal generation circuit 21 supplied to the terminal C, and cleared by the clear signal PC supplied to the terminal R. When the clear signal pc is supplied to the R terminal, the timer time T set and stored in the timer memory is cleared and the device returns to the initial state.

The percentage calculation circuit 14 displays the timer time T supplied from the Dt terminal of the timer circuit 16 through the progress display section 6 shown in FIG.
This is a circuit for calculating percentage data with one cycle of 2 being 100. First, the set timer time T is set to T/100.
Calculate the percentage at 8 and display this value on the progress display section 62
In order to convert the number of steps in the 01st lap to 60, it is multiplied by 100/60, and the time Ta for advancing the progress display section 62 by one step is calculated as in equation (2). Then, this calculated one-step time T8 is converted into pulse number data N of the clock signal φO, and this pulse number data N is output. The series of arithmetic operations described above is executed by the arithmetic command signal Pd supplied to the terminal C.

The raw progress signal generation circuit 15, as shown in detail in FIG.
Percentage memory 151, matching circuit 152, counter 156
, a progress signal circuit 154, a delimiter setting circuit 155, and a comparison circuit 156.

The pulse number data N is input from the terminal Dp as described above, and this data N is stored in the percentage memory 151 as the number of pulses required to send one division. On the other hand, counter 1
53 counts the clock signal φ0 inputted to the terminal CL, and a matching circuit 152 detects a coincidence between the count of this counter 156 and the pulse number data N stored in the percentage memory 151. That is, counter 15
When the count number of 6 reaches the stored value N of the percentage memory 151, the coincidence circuit 152 outputs a coincidence pulse pc, and this coincidence pulse pe is supplied to the progress signal circuit 154, and at the same time passes through the OR gate OR3 to the counter. 156 momentarily.

The counter 156 performs the counting operation again, and each time the count reaches N, the matching circuit 152 outputs a matching pulse, and this operation is repeated thereafter. Therefore, the period of the coincidence pulse P@ becomes equal to the one step time T calculated by the percentage calculation circuit 14. The progress signal circuit 154 consists of a 60-step shift register corresponding to the number of scales on the progress display section 32, and is shifted for each coincidence pulse pe to sequentially light up the scales on the progress display section 32 via the terminal Od. (. The delimiter setting circuit 155 has 60 memories corresponding to the delimiter mark K. In response to the selection signal, 9 is sequentially selected from the delimiter marks K to 9, and the selection marks are displayed blinking.Then, while the delimiter mark to be set is blinking, a set pulse pse is supplied from the terminal St. , the delimiter mark is lit, and the corresponding memory of the delimiter setting circuit 155 is set.The comparison circuit 156 compares the information of the progress signal circuit 154 with the setting value of the delimiter setting circuit 155, and sets the progress signal. When the progress of the circuit 154 matches the memory set in the break setting circuit 155, the break alarm signal Poa is output from the terminal Qa.The progress signal generation circuit 15 performs an OR when the repeat pulse pr is supplied from the terminal Rp. Progress signal circuit 154 is reset via gate OR4,
Further, by resetting the counter 156 via OR3, the display lighting of the progress display section 32 is returned to zero, and a repeat operation is performed in which the progress signal generation operation is repeated according to the pulse number data N stored in the percentage memory. becomes. Furthermore, when a clear pulse pc is supplied to the terminal R, the progress signal circuit 154, counter 156, and percentage memory 151 are all reset, so that they become initial states and stop operating.

The acoustic drive circuit 20 generates a warning sound by sounding a buzzer 8 based on a signal that passes through the OR2, and sounds for 2 seconds in response to a break alarm signal P oa, and then outputs an end signal P o
Sounds for 5 seconds with s.

The control signal generation circuit 21 starts after pressing the start button.
It operates for a certain period of time within sec, and a computation command signal Pd instructing to start computation is input to terminal C of the timer information setting circuit 12, percentage computation circuit 14, timer circuit 13, and scale time computation circuit 22. This means that the timer information setting circuit 12 stores the time counter in the start time memory 121 within the time (1 second) from when the start button ST is pressed until the timer frequency dividing circuit 19 operates and outputs the clock signal φ0. 16
The timer circuit 16 calculates and stores the timer time T as the start time, the scale time calculation circuit 22 determines the scale time, and the percentage calculation circuit 14
is used to input the timer time T from the timer circuit 16, calculate the pulse number data N, and transfer it to the progress signal generation circuit 15.

The selection circuit 11 has a normal terminal N, an hour setting terminal H2 for setting the end time, a minute setting terminal M2, and a delimiter setting terminal K.
. - to 3. has each output terminal, and select pulse P81
For each input, the designated signal is output to each output terminal in sequence.

The flip-flop circuit FF and the AND gate AND1 constitute a start/stop control circuit in the timer function, and when the FF is set by the start pulse P3 or repeat pulse pr passing through the OR gate ORI, its output Q , Q releases the reset of the timer frequency divider circuit 19 and opens ANDI (therefore, the clock signal φ0 is supplied to the timer circuit 16 and the timer operation starts. Then, the clock signal φ0 is supplied to the timer circuit 16 and the timer operation starts. Then, the clock signal φ0 is output from the Qs terminal of the timer circuit 13. When the end signal Pos passes through ORI and resets the FF, the frequency dividing circuit 19 is reset and ANDI is closed to end the timer operation.The setting of the FF by the repeat pulse pr is used for repeat and start.

Next, the operation of this circuit will be explained in detail. In the non-operating state of the timer, the selection circuit 11 is in the normal terminal N specified state, and the timer circuit 13, percentage calculation circuit 14, progress signal generation circuit 15, and flip-flop FF are all in the reset state. In order to use the timer from this state, first operate the select button SL to select the selection circuit 11.
is set to the selected state of the hour setting terminal H for setting the end time. As a result, the end time memory 12 of the timer information setting circuit 12
The hour digit of 2 is specified, and the end time display unit 60 is flashed through the output terminal Od, and the end time memory 1 is displayed.
The hour digit of 22 becomes settable. When the set button SE is operated in this state, the number on the end time display section 6 changes each time the set button SE is operated, and the hour digits are set. When the setting of the hour digit is completed, operate the select button SL to set the selection circuit 11 to the selection state of the minute setting terminal M, the minute digit will blink, the minute digit of the end time display section 6 will become settable, and the minute digit will be set. Minute digits can be set using button SE. By these operations, the end time 'ro is set in the timer information setting circuit 12.

Next, the delimiter display section 31 in the percentage display section B is set. When the select button S f is operated, the selection circuit 110
6. to - to the delimiter setting terminal. are sequentially selected, and each separator mark on the separator display section 31 becomes a '@next point' state. Therefore, if you operate the seven-node button SE while the setting l-dai separator mark is blinking, the The delimiter mark is kept in a lit state; and the memory of the delimiter setting circuit 155 corresponding to the delimiter mark is set. Any number of delimiter marks can be set corresponding to the schedule items entered in the schedule entry section 9, which will be described later. In this way, a series of settings are completed, and then the timer operation is started.

When the start button ST is operated, a start pulse (1) 8 is supplied to the control signal generation circuit 21 and passes through OR1 to set the flip-flop FF. As a result, the calculation command signal Pd output from the control signal generation circuit 21 is
By being supplied to the control terminal C of the timer information setting circuit 12, the current time of the time counter 16 is stored in the start time memory 121 as a start time Tk, and is also displayed on the start time display section via the output terminal Od. Further, the timer information setting circuit 12 calculates a timer setting time T from the set start time "rk" and end time To, and supplies it to the evening timer circuit 16. At the same time as ANDI is opened by
Seconds later, the clock signals φ and I: output from the timer frequency dividing circuit 19 pass through ANDI and are supplied to the clock terminal CL of the timer circuit 16 and the progress signal generating circuit 15; Within one second from the release of the cent signal until the clock signal φ0 is output, the percentage calculation circuit 14 calculates the pulse number data N, transfers it to the percentage memory 151 of the progress signal generation circuit 15, and completes the storage operation. There is. Then, the timer circuit 16 performs a subtraction operation using the clock signal φ. output from the frequency dividing circuit 19 every second, so that the timer display section 2 displays a subtracted value, and the progress signal generation circuit 15 generates a progress signal. As a result, the progress display section 62 displays an integrated percentage.

Also, each time the progress of the progress signal circuit 154 matches a break mark set in the break setting circuit 155, the acoustic drive circuit 20 drives the buzzer 8 for 2 seconds in response to the break warning signal poa output from the terminal Oa, and an alarm is generated. make a sound. Furthermore, when the subtraction operation of the timer circuit 16 is completed, the terminal 0
The end signal p as is output from 3, passes through ORI, and resets the FF, thereby ending the timer operation.At the same time, the end signal P os, which passes through OR2, sounds an alarm for 5 seconds to notify the conference attendees of the time. announces the end of.

FIG. 4 is a front view for explaining the specific operation of the timer device according to the present invention, and FIG. 5 is a front view of another embodiment of the timer device according to the present invention. The embodiment shown in FIG. 5 differs from the first embodiment in the arrangement of each display section, and is further provided with a schedule entry section 9. In the schedule entry section 9, for example, "problem posed", "problem clarified", "problem investigated" are written.
, ``Planning countermeasures,'' etc., are entered with waiting time allocated. Functionally, it is completely similar to the first embodiment.

4 and 5 show a case where the end time is set at 10 o'clock and the start button ST is operated when the current time on the time display section 4 is 8 o'clock, that is, the start time Tk=8:00 and the end time To=10:00, timer setting time T=2 (H)
(To-Tk) and shows the state 23 minutes have passed since the start, and the separator marks are 6, K24,
K4□, K, and 6 indicate the respective divisions of the schedule entry section 9. The progress display section 32 displays 1 as shown by diagonal lines.
One step forward.

That is, the operations of the percentage calculation circuit 14 and the progress signal generation circuit 15 in the usage state shown in FIGS. 4 and 5 will be explained as follows.
The percentage calculation circuit 14 inputs the evening meeting time T = 120 (minutes), calculates it according to the formula (1) above, and converts this Ts into the number of pulses of the clock signal φ0 with a 1 second period, N = 120 pulse number data in percentage memory 151
to be memorized. As a result, every time the counter 156 counts 120 clock signals φ0, the coincidence pulse ps is output from the coincidence circuit 152, and the progress signal circuit 154 is advanced in 2-minute steps, so that the progress display section 62 is displayed in 2-minute steps (Ts ) to display the total. Then, when the progress signal circuit 154 advances by 6 steps, the comparison circuit 156 detects a match with the memory number 6 set in the delimiter setting circuit 155, and generates a delimiter alarm signal Poa. The operation of the scale time calculation circuit 22 is to calculate the timer time T=120 minutes from the input start time Tk and end time To, and further calculate the time width 'l' of one scale at 120/10.
Calculate m = 12 minutes and use this time width Tm as the start time'
Sequentially add = 8:00 to l', 8:12.8 2
24, 8: 36, 8: 48, 9
: 00.9:12.9:24.9:36.9:48
The scale time is determined and displayed on the scale time display section 7.

When the progress display section 62 has 60 patterns as described above, when the timer time T is 60 minutes (1 hour), T, =
1 (minute), N=60, which is a 1 minute step, and T=
For 120 minutes (2 hours), T, = 2 (minutes), N = 120
Then, in 2 minute steps, furthermore, at T=30 minutes, 'ra=
-3o (seconds), N=30, resulting in a 30 second step.

Note that it is possible to replace the above configuration with a microcomputer, in which case all the operations described above are performed by C.
It is controlled by the PU and memory based on a predetermined program.

In addition, in this embodiment, the scale of the progress display part of the percentage display part is 60 scales per round, but this is the most useful considering that the timer setting time T is set as an integer multiple or fraction of 60 minutes. Although the number of scales is easy to use, it is not limited to this, and it is also possible to set it to 100 scales, for example, and it goes without saying that in this case, the scale display will be a percentage display as it is. As for the start time, if you press the start button when the participants have gathered, the time from that time to the end time becomes the timer time T and is converted into a percentage, so the actual meeting time is always constant. It is possible to allocate agenda items based on ratios.

〔Effect of the invention〕

As described above, according to the present invention, by displaying the elapsed time as a percentage, it becomes easier to manage the progress of meetings and work hours. Since the time at which work starts can be set, it is possible to always allocate time at a fixed ratio to the actual timer time, which is extremely effective in terms of progress management.

[Brief explanation of drawings]

FIG. 1 is a front view of a timer device as an embodiment of the present invention, FIG. 2 is a circuit block diagram of the device shown in FIG. 1, and FIG.
4 is a front view for explaining the operation of the device shown in FIG. 1, and FIG. 5 is another embodiment according to the present invention. FIG. 1... Timer device, 2... Timer display section, 6... Percentage display section, 4... Time display section, 5...... Start time display section, 6... Song/end time display section, 7... Scale time display section, 8...
····buzzer. Figure 1 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] A clock circuit that generates time information, a timer information setting circuit that sets the end time of the timer operation, the current time from the clock circuit being the start time, and based on the start time and the end time set in the timer information setting circuit. A timer circuit that calculates a timer time, a percentage calculation means that converts the timer time into percentage data, a progress signal generation circuit that generates a progress signal of the timer time based on the percentage data, and a display section, A timer device characterized in that the timer time between a time and an end time is displayed as a percentage on the display section using a progress signal.