JPS6233676B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a nonvolatile semiconductor memory device in which a memory cell is a double-gate MOS transistor having a floating gate structure.

Nonvolatile semiconductor memory devices, especially those whose memory cells are double-gate MOS transistors with a floating gate structure, are used in various systems including microcomputer systems because data can be rewritten. ing. As is well known, the double-gate MOS transistor has two gate structures: a floating gate and a control gate provided above the gate, and electrons are currently injected into the floating gate. If so, the threshold voltage has increased, so a high level signal (for example +
5V) is applied, there is no continuity. On the other hand, if no electrons are injected into the floating gate and it is in a neutral state, its threshold voltage is low, so if a high level signal is applied to the control gate at this time, it becomes conductive.
That is, data is stored by making the conduction and non-conduction states of the transistor correspond to data "1" and "0" when a high level signal is applied to the control gate. When injecting electrons into the floating gate, a high potential (for example, +20 to +25V) is applied to both the control gate and the drain. Impact ionization occurs in the pinch-off region of the channel region near the drain.
Electrons from the electron-hole pairs generated by ionigation are injected into the floating gate. Since the electrons once injected into the floating gate remain in the floating gate unless erased, the data becomes non-volatile.

By the way, it is well known that the pinch-off region that occurs when injecting electrons occurs when a MOS transistor operates as a pentode. It is dangerous to use a memory cell in a biased state that results in pentode operation, even if, for example, a high potential is not applied to both the control gate and drain. That is, since a pinch-off region also occurs at this time, impact ionization occurs. At this time, because the potential is low, the channel current is small and only a few pairs of electrons and holes are generated, so the probability that electrons will be injected into the floating gate is extremely small, but this state exists for a long time. If so, electrons will be accumulated in the floating gate one after another. As a result, the threshold voltage of the memory cell may fluctuate, leading to a possibility that the stored data may change.

Conventionally, the drain potential of the memory cell is lower than the control gate potential to prevent the pinch-off region from occurring except when writing data, and even if the threshold voltage of the memory cell fluctuates, this is prevented. Nonvolatile semiconductor memory devices that can be canceled have been developed. FIG. 1 shows its configuration. In the figure
R ₁ to _{R n} are row lines to which outputs from row decoders (not shown) are given, C ₁ to _Co are column selection lines to which outputs from column decoders (not shown) are given, and each column selection line
N enhancement type column line selection transistors G ₁ -G _o are respectively driven by C ₁ -C _o . One end of each of the column line selection transistors G ₁ to _Go is commonly connected to point A, and the other end is connected to each of the n transistors provided to intersect with the row lines R ₁ to R _n . Column line COL ₁ ~
Connected to COL _o . At each intersection of the row lines R ₁ to _{R n} and the column lines COL ₁ to _{COL o} , there is a double gate type MOS having a floating gate and a control gate.
Each memory cell M ₁₁ to M _no consisting of a transistor is provided. And this memory cell M ₁₁ ~M
Row line Ri (1≦i≦m) corresponding to the control gate of _no
, the drain is connected to the corresponding column line COL _j (1≦j≦
n), and all sources are further connected to a ground potential V _s application point (OV application point).

At the point Aa, a load circuit LO is provided from enhancement type MOS transistors 1a to 5a. In this load circuit LO, the gates are both connected to the V _c application point, and a bias lower than V _c is obtained by transistors 4a and 5a inserted in series between the V _c application point and the V _s application point. , by applying this bias to the gate of transistor 1a whose source is connected to point Aa, the potential at point Aa is set to be lower than V _c , and the above bias is also applied to the gate of transistor 2a. In particular, transistor 3a allows approximately V _c
The Ba point set at , and the above Aa point are separated. That is, by setting the amplitude of the signal at point Aa to be less than or equal to V _c , memory cells M ₁₁ to M
When _no is selected, each drain potential is set lower than the control gate potential, and each memory cell M ₁₁ to M _no operates as a triode except when writing data. The amplitude of the signal at the point Aa is amplified to _Vc at the point Ba by the transistor 3a.

Enhancement type MOS transistor 6
a, 6b, 9, 10a-12a, 10b-12
The sense amplifier circuit SA, which is composed of depletion type MOS transistors 7a, 7b, and 8, is of a well-known differential amplification type having a chip select function, and the sense amplifier circuit SA is of a well-known differential amplification type having a chip select function. The potential at point Ba is applied to the gate of transistor 6a in the input stage.

In addition, the circuit surrounded by a broken line in FIG. 1 is a reference potential generation circuit 14 that generates a reference potential to be applied to the sense amplifier circuit SA, and is used to detect the signal potential at the Ba point. The potential at the point is "1" from the memory cells _M11 to _Mno ,
It is set to approximately the middle potential of the amplitude of the signal at point Ba when data "0" is read. For this reason, this reference potential generation circuit 14 includes the column line selection transistors G ₁ - , whose drains are connected to the Ab point and whose gates are connected to the V _c application point.
An enhancement type MOS transistor G _b equivalent to G _o , and the memory cells M ₁₁ to M inserted between the source of this transistor G _b and the V _s application point.
A double-gate MOS transistor M _b whose floating gate is in a neutral state, equivalent to _no , and a V _c application point and a V _s application point to give a bias lower than V _c to the control gate of this transistor M _b two depletion-type MOS transistors 15 and 16 connected in series between the point and the transistor 1a;
5a and a load circuit LO consisting of transistors 1b to 5b equivalent to the transistors 1b to 5b. That is,
In this reference potential generation circuit 14, memory cells M ₁₁ to
By providing a transistor M _b equivalent to M _no , variations in the threshold voltages of the memory cells M ₁₁ to _{M no} are canceled.

In a memory device having such a configuration, if another row line R ₁ and one column line COL ₁ are selected, the memory cell M ₁₁ at the intersection thereof is selected. If the floating gate of the selected memory cell _M11 is in a neutral state and the threshold voltage is low, this memory cell _M11 becomes conductive, the column line _COL1 is discharged, and the Ba point is at a predetermined low level. It becomes electric potential. Further, if electrons are injected into the floating gate of this memory cell _M11 and the threshold voltage is in a high state, this memory cell _M11 becomes non-conductive, and the column line _COL1 is charged by transistors 1a and 3a. Then, point Ba becomes a predetermined high potential. At this time, the sense amplifier circuit
Since the potential at point Bb, which is set to approximately the midpoint potential of the signal amplitude at point Ba above, is given as the reference potential for SA, the sense amplifier circuit SA detects data by comparing both potentials. , outputs this detection data to the output buffer.

By the way, in the conventional memory device described above, a bias lower than V _c is applied to the control gate of the transistor M _b in the reference potential generation circuit 14 in order to create a reference potential to be applied to the sense amplifier circuit SA. Therefore, this transistor _Mb operates in a state closer to pentode operation than the memory cells _{M11 to Mno} . Actually, the control gate of the transistor _Mb is used at about 3V, and the drain is used at 2V to 3V, so this transistor _Mb operates as a pentode. Note that the pentode operation and triode operation here refer to the following bias conditions, where the gate voltage of the MOS transistor is V _G , the drain voltage is V _D , the source voltage is V _S , and the threshold voltage is V _TH Operation in this state is called pentode operation, and operation in the bias state is called triode operation.

V _G −V _TH −V _s <V _D −V _s V _G −V _TH −V _s <V _D −V _s Because the above transistor M _b operates as a pentode, this transistor M _b Electrons are sequentially accumulated in the floating gate of memory cell M 11 , and as a result, the potential at point Bb, which becomes the reference potential, rises, and memory cell M ₁₁
~The data read speed from M _no changes,
The disadvantage is that erroneous data may be detected, resulting in low reliability.

This invention was made in consideration of the above circumstances, and its purpose is to improve reliability by setting a bias so that a transistor equivalent to a memory cell in a reference potential generating means always operates as a triode. An object of the present invention is to provide a nonvolatile semiconductor memory device with high performance.

An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 2 to 5 are block diagrams of different embodiments of the present invention, in which only the reference potential generation circuit 14 is shown. That is, in the present invention, the bias is set so that the transistor M _b equivalent to the memory cells M ₁₁ to _{M no} always operates as a triode, and the sense amplifier circuit SA
The potential at point Bb, _which is given _as a reference potential to This is what I did.

In the embodiment shown in FIG. 2, instead of setting the control gate potential of transistor M _b to a potential lower than V _c , the control gate potential of transistor M _b is set to V _c and
The gate potential of the transistor G _b equivalent to the column selection transistors G ₁ to _{G o} connected between the V c and V s application points is set by two transistors connected in series between the V _c application point and the V _s application point. The potential is set to be lower than V _c obtained by the depletion type MOS transistors 17 and 18.

With this configuration, the potential at point Bb can be set to approximately the midpoint potential of the signal amplitude at point Ba, and since the drain potential of transistor M _b is sufficiently lower than the control gate potential, Depending on the bias condition, transistor _Mb is completely triode-operated.

Note that in this embodiment, two transistors 1
Resistance elements may be used in place of 7 and 18.

In the embodiment shown in FIG. 3, the control gate potential of transistor M _b and the gate potential of transistor G _b are both set to V _c , and transistors 1 b,
The gate potential of 2b is set lower than that of the conventional one. For this purpose, between the V _c application point and the V _s application point, there are two enhancement-type MOS transistors whose gates are both connected to the V _c application point and whose gm ratio is set differently from the conventional one.
Transistors 19 and 20 are connected in series, and the potential at this series connection point is applied in parallel to the gates of transistors 1b and 2b.

With such a configuration, the conduction resistance of transistors 2b and 1b increases, and transistor M _b
Even though both the control gate potential of transistor Gb and the gate potential of transistor _Gb are set to _Vc , the potential at point Bb can be set to approximately the middle potential of the signal amplitude at point Ba. Also in this case, the drain potential of the transistor M _b is sufficiently lower than the control gate potential, so that the bias state causes the transistor M _b to completely operate as a triode.

By the way, in the embodiment shown in FIG. 3, the potential obtained by transistors 19 and 20 is applied in parallel to the gates of transistors 1b and 2b, but in order to set the potential at point Bb to the above potential, It is only necessary to set the gate potential of transistor 2b low. Therefore, in the embodiment shown in FIG. 4, the potential obtained by transistors 4b and 5b is applied to the gate of transistor 1b.

In the embodiment shown in FIG.
The control gate potential of transistor _Gb and the gate potential of transistor _Gb are both set to _Vc , and transistor 3b
Instead, an enhancement type MOS transistor 3c having a lower conduction resistance is provided.

With this configuration, the potential at point Ba can be raised higher than when transistor 3b is used, so
The potential at point Bb can be set to approximately the middle potential of the signal amplitude at point Ba, and the transistor M _b
Since the drain potential of Mb is sufficiently lower than the control gate potential, the bias state causes the transistor _Mb to completely operate as a triode.

As described above, in the embodiment devices shown in FIGS. 2 to 5, the memory cells in the reference potential generation circuit 14 are
Since the bias is set so that the transistor M _b , which is equivalent to M ₁₁ to _{M no} , always operates as a triode, no electrons are injected into the floating gate of this transistor M _b , and the point Bb, which is the reference potential, is The potential does not increase sequentially as in the conventional case. In other words, the potential at point Bb changes only when the threshold voltages of memory cells M ₁₁ to _{M no} change to cancel them, so the data read speed is always constant and erroneous data is not detected. There is no fear of being damaged, and reliability is high.

As explained above, according to the present invention, since the bias is set so that the transistor equivalent to the memory cell in the reference potential generating means always operates as a triode, it is possible to provide a highly reliable nonvolatile semiconductor memory device. can.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional nonvolatile semiconductor memory device, and FIGS. 2 to 5 are block diagrams of different embodiments of the present invention. _R1 to _Rn ...Row line, _C1 to _Co ...Column selection line,
COL ₁ ~ COL _o ... Column line, M ₁₁ ~ M _no ... Memory cell, LO... Load circuit, SA... Sense amplifier circuit,
M _b ...Double gate type MOS equivalent to a memory cell
Transistors, 17, 18...depression type MOS transistor, 19, 20...enhancement type MOS transistor, 3c...enhancement type MOS transistor.

Claims (1)

[Claims] 1. A row line, a memory cell consisting of a transistor having a floating gate structure that is selectively driven by the row line, a column line for receiving data from the memory cell, and a column selection memory cell. a transistor, a load circuit connected to the column line via the column selection transistor, a sense amplifier circuit that detects the potential of the column line by comparing it with a reference potential, and a reference potential generator that generates the reference potential. The reference potential generating means includes a transistor equivalent to the memory cell, a transistor equivalent to the column selection transistor, and a load means equivalent to the load circuit, The reference potential is generated by making the conduction resistance or voltage bias condition of at least one of the transistors or transistors constituting load means equivalent to the load circuit different from those of the column selection transistor or the transistor constituting the load circuit. A nonvolatile semiconductor memory device characterized in that it is configured to. 2. The reference potential generating means is a non-volatile device according to claim 1, wherein the dimensions or voltage bias conditions of the transistor that determine the conduction resistance are set so that the transistor equivalent to the memory cell operates as a triode. semiconductor memory device. 3. In the reference potential generation means, the gate potential of a transistor equivalent to the column selection transistor is set to a value lower than the gate potential when the column selection transistor is selected, and the voltage bias conditions are varied. A nonvolatile semiconductor memory device according to claim 1. 4. The load circuit and the load means in the reference potential generation means each include a first transistor having at least one of its source and drain connected to the column selection transistor or an equivalent transistor, and the other connected to a power supply. and a second transistor, one of the source and drain of which is connected to the column selection transistor or an equivalent transistor, and the other of which is connected to the power supply via a third transistor. A nonvolatile semiconductor memory device according to scope 1. 5. Claims in which the voltage bias conditions are made different by setting the gate potential of the second transistor in the load means lower than the gate potential of the corresponding second transistor in the load circuit. The nonvolatile semiconductor memory device according to item 4. 6. The nonvolatile semiconductor according to claim 4, wherein the conduction resistance of the third transistor in the load means is set to be smaller than the conduction resistance of the corresponding third transistor in the load circuit. Storage device. 7. The nonvolatile semiconductor memory device according to claim 6, wherein a gate of a transistor equivalent to the memory cell in the reference potential generation means is set to a power supply potential.