JPS6232628A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS6232628A JPS6232628A JP60172039A JP17203985A JPS6232628A JP S6232628 A JPS6232628 A JP S6232628A JP 60172039 A JP60172039 A JP 60172039A JP 17203985 A JP17203985 A JP 17203985A JP S6232628 A JPS6232628 A JP S6232628A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- wiring layer
- external lead
- gold
- germanium
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/485—Material
- H01L2224/48505—Material at the bonding interface
- H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
- H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/48617—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950 °C
- H01L2224/48624—Aluminium (Al) as principal constituent
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
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- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
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- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体素子と、その半導体素子に連結し且つ
遊端にパッド部を有する配Ｉ！ＩＩ層とを形成している
半導体基板を有し、その配線層のパッド部に、外部導出
用線の一端が圧溶接されている半導体装ｎの改良に関す
る。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device and a semiconductor device connected to the semiconductor device and having a pad portion at a free end. The present invention relates to an improvement in a semiconductor device n, which has a semiconductor substrate forming a layer II and has one end of an external lead line pressure-welded to a pad portion of the wiring layer.
半導体装Ｕとして、従来、第３図を伴なって次に述べる
構成を有するものが提案されている。Conventionally, a semiconductor device U having the configuration described below with reference to FIG. 3 has been proposed.
すなわら、半導体索子（図示せず）と、その半導体水子
に連結し且っ遊端に上外部に露？しているパッド部３を
右する配線層２とを形成している例えばシリコンでなる
半導体基板１を有し、その半導体基板１が、底板部６と
、側壁部７と、上板部８とを有する例えばセラミックの
ような絶縁材でなるケース体５内に封入されている。That is, a semiconductor cable (not shown) is connected to the semiconductor cable and the free end is exposed to the outside. It has a semiconductor substrate 1 made of silicon, for example, which forms a wiring layer 2 on the right side of a pad section 3, and the semiconductor substrate 1 has a bottom plate section 6, a side wall section 7, a top plate section 8, and a wiring layer 2 on the right side. It is enclosed in a case body 5 made of an insulating material such as ceramic.
この場合、ケース体５には、その底板部６の内面中央位
置から側壁部７を貫通し、そして下方に折曲って延長し
ているｌ１７ｉ面り字状の外部連結用端子片つと、底板
部６の内面側方位前がら同様に側壁部７を貫通し、そし
て下方に折曲って延長している断面逆り字状の複数の外
部連結用端子片１０が設けられている。In this case, the case body 5 has a l17i-shaped external connection terminal piece that extends from the center of the inner surface of the bottom plate part 6 through the side wall part 7 and is bent downward, and the bottom plate part A plurality of external connection terminal pieces 10 having an inverted-shaped cross section are provided which penetrate the side wall portion 7 in the same manner as shown in FIG.
しかして、半導体基板１が、その底面を、外部連結用端
子９に、ケース体５の内面側のパッド部としての水平部
１１において、熱溶着されていることによって、ケース
体５内に固定されている。また、半導体基板１に形成さ
れている配線層２が、それに、そのパッド部３において
。The semiconductor substrate 1 is fixed in the case body 5 by thermally welding its bottom surface to the external connection terminals 9 at the horizontal part 11 serving as a pad on the inner surface of the case body 5. ing. Further, the wiring layer 2 formed on the semiconductor substrate 1 and the pad portion 3 thereof.
外部導出用線１２の一端が圧溶接され、一方、外部導出
用線１２の他端が、外部連結用端子片１０に、ケース体
５の内面側のパッド部としての水平部１３において、圧
溶接されていることによって、パッド部３と、外部導出
用線１２と、外部連結用端子片１０とを介して、外部に
導出されている。One end of the external lead wire 12 is pressure welded, and the other end of the external lead wire 12 is pressure welded to the external connection terminal piece 10 at the horizontal part 13 as a pad part on the inner surface side of the case body 5. As a result, it is led out to the outside via the pad portion 3, the external lead wire 12, and the external connection terminal piece 10.
また、半導体装置として、従来、第４図を伴なって次に
述べる構成を有するものも提案されている。Further, as a semiconductor device, a device having the configuration described below with reference to FIG. 4 has been proposed.
すなわち、第３図で上述した半導体装置の場合と同様の
、半導体素子と、パッド部３を有する配線層２とを形成
している半導体基板１を有し、その半導体基板１が、合
成樹脂材２１によって埋設されている。That is, it has a semiconductor substrate 1 on which a semiconductor element and a wiring layer 2 having a pad portion 3 are formed, similar to the case of the semiconductor device described above in FIG. It is buried by 21.
この場合、第３図で上述した半導体装置の場合と同様の
外部連結用端子片９及び１０を有し、しかして、半導体
基板１が、第３図の場合と同様に、その底面を、外部連
結用端子片９に、そのパッド部としての水平部１１にお
いて、熱溶着され、また、半導体基板１に形成されてい
る配Ｐｉ１層２が、それに、そのパッド部３において、
外部導出用ｌ！ａ１２の一端が圧溶接され、一方、外部
導出用線１２の他端が、外部連結用端子片１０に、その
パッド部としての水平部１３に圧溶接されている状態で
、外部連結用端子片９及び１０のパッド部としての水平
部１１及び１３及び外部導出用線１２とともに、合成樹
脂材２１によって、埋設されている。In this case, the semiconductor substrate 1 has terminal pieces 9 and 10 for external connection similar to those of the semiconductor device described above in FIG. The connecting terminal piece 9 is thermally welded at the horizontal portion 11 as a pad portion thereof, and the wiring Pi1 layer 2 formed on the semiconductor substrate 1 is attached thereto at the pad portion 3.
For external derivation l! One end of a12 is pressure welded, while the other end of the external lead wire 12 is pressure welded to the horizontal part 13 as a pad part of the terminal piece 10 for external connection, and the terminal piece for external connection is It is buried with a synthetic resin material 21 together with the horizontal parts 11 and 13 as pad parts of 9 and 10 and the external lead wire 12.
以上が、従来提案されている半導体装置の構成である。The above is the configuration of a conventionally proposed semiconductor device.
このような構成を有する半導体装置によれば、半導体素
子に、外部から、外部連結用端子片１０を介して、所要
の電源を供給することができ、また、その状態で、半導
体素子に、外部連結用端子片１０を介して、信号を供給
し、また、半導体素子から外部連結用端子片１０を介し
て、信号を出力させることができる。According to the semiconductor device having such a configuration, the required power can be supplied to the semiconductor element from the outside via the external connection terminal piece 10, and in this state, the semiconductor element can be supplied with the required power from the outside. A signal can be supplied via the connection terminal piece 10, and a signal can be outputted from the semiconductor element via the external connection terminal piece 10.
従って、第３図及び第４図に示す従来の半導体装置によ
れば、外部連結用端子片１０を介して、半導体装置とし
ての動作を（りることができる。Therefore, the conventional semiconductor device shown in FIGS. 3 and 4 can operate as a semiconductor device via the external connection terminal piece 10.
発明が解決しようとする問題点
第３図及び第４図で上述した従来の半導体装置の場合、
半導体素子が、その配ｔＩＡ層２のパッド部３と、外部
導出用線１Ｑとを介して、外部連結用端子片１０に連結
されていることによって、上述したように、外部連結用
端子片１０を介して、半導体装置としての動作が１９ら
れるが、この場合、配線層２は、比抵抗が十分低い、半
導体素子に悪影響を与える不純物を十分低い濃度しか含
まないものとして容易に半導体基板１に形成することが
できる、などの理由から、アルミニウムでなるのを普通
としていた。Problems to be Solved by the Invention In the case of the conventional semiconductor device described above in FIGS. 3 and 4,
As described above, the semiconductor element is connected to the external connection terminal piece 10 via the pad portion 3 of the TIA layer 2 and the external lead-out line 1Q. In this case, the wiring layer 2 can be easily transferred to the semiconductor substrate 1 as having a sufficiently low specific resistance and containing a sufficiently low concentration of impurities that adversely affect the semiconductor element. Aluminum was commonly used because it could be formed.
また、配線層２のパッド部３に圧溶接される外部導出用
線１２は、比抵抗が十分低い、半導体素子に悪影響を与
える不純物を十分低い濃度しか含まないものとして容易
に用窓することができ、また、このため、配線層２のパ
ッド部３に圧溶接したときに半導体素子に悪影響を与え
ない、配線層２のパッド部３への圧溶接を容易に行うこ
とができる、などの理由から、金でなるのを踏通として
いた。In addition, the external lead wire 12 pressure-welded to the pad portion 3 of the wiring layer 2 has a sufficiently low specific resistance and contains only a sufficiently low concentration of impurities that adversely affect the semiconductor element, so that it can be easily used. Moreover, for this reason, there is no adverse effect on the semiconductor element when pressure welding is performed to the pad portion 3 of the wiring layer 2, and the pressure welding to the pad portion 3 of the wiring layer 2 can be easily performed. Since then, he has always believed in making money.
さらに、外部連結用端子片１０は、比抵抗が十分低い、
強固である、金でなる外部導出用線１２が容易に圧溶接
される、などの理由から、モリブデン、モリブデン・マ
ンガン合金などでなる端子片本体１３の表面に、ニッケ
ルでなる中間層１４を介して、金または銀でなる表面層
１５が形成されている構成を有しているのを普通として
いた。Furthermore, the external connection terminal piece 10 has a sufficiently low specific resistance.
For reasons such as strength and easy pressure welding of the external lead-out wire 12 made of gold, the surface of the terminal piece body 13 made of molybdenum, molybdenum-manganese alloy, etc. is coated with an intermediate layer 14 made of nickel. Therefore, it is common to have a structure in which a surface layer 15 made of gold or silver is formed.
ところで、外部導出用線１２と外部連結用端子片１０と
の間の連結は、外部導出用線１２が金でなり、外部連結
用端子片片１０が金または銀でなる表面層を有していて
、その金でなる外部導出用線１２が、外部連結用端子片
１０の金またはそれと同じような性質を有り−１る銀で
なる表面層に圧溶接しているため、半導体装置に熱１ノ
イクルが与えられても、比較的長い使用期間に亘って、
安定な状態を保っている。By the way, the connection between the external lead wire 12 and the external connection terminal piece 10 is such that the external lead wire 12 is made of gold and the external connection terminal piece 10 has a surface layer made of gold or silver. Since the external lead-out wire 12 made of gold is pressure-welded to the surface layer of the external connection terminal piece 10 made of gold or silver having similar properties, heat 1 is applied to the semiconductor device. Even if Noicle is given, over a relatively long period of use,
It remains in a stable condition.
しかしながら、半導体基板１に形成されている配線層２
と、外部導出用線１２との間の連結は、配線層２がアル
ミニウムでなり、外部導出用線１２が金でなることによ
り、その金でなる外部導出用線１２が、アルミニウムで
なる配線層２のパッド部３に圧溶接して、アルミニウム
と金とが合金化して得られており、そして、その合金化
が、外部導出用線１２を構成している金と配ＩＦＷ２を
形成しているアルミニウムとが比較的反応し易いことか
ら、比較的短い使用期間で比較的大ぎく進行し、その合
金化層に比較的大なる内部応力が蓄積し、このため、半
導体装置が熱サイクルを受けることによって、不安定な
状態になったり、断線状態になったりするという、欠点
を有していた。However, the wiring layer 2 formed on the semiconductor substrate 1
The wiring layer 2 is made of aluminum and the external lead line 12 is made of gold, so that the external lead line 12 made of gold is connected to the wiring layer 12 made of aluminum. It is obtained by pressure welding to the pad portion 3 of 2 and alloying aluminum and gold, and this alloying forms the gold and wiring IFW 2 that constitute the external lead wire 12. Because it is relatively easy to react with aluminum, it progresses to a relatively large extent in a relatively short period of use, and a relatively large internal stress accumulates in the alloyed layer, which causes the semiconductor device to undergo thermal cycles. This has the drawback of causing an unstable state or a disconnection state.
因みに、第３図で上述した従来の半導体装置の場合、そ
の２４個について、長時間、１７５℃の温度に加熱した
状態で動作させたところ、１６０００時間で１個、１８
０００時間で３個、２００００時間で６個の累積故障数
が生じた。Incidentally, in the case of the conventional semiconductor device shown in FIG.
The cumulative number of failures was 3 in 000 hours and 6 in 20000 hours.
また、第４図で上述した従来の半導体装置の場合、その
２７個について、同様の状態で動作させたところ、２５
００時間で１個、３０００時間で５個、３５００時間で
１４個の累積故障数が生じた。Furthermore, in the case of the conventional semiconductor device described above in FIG. 4, when 27 of them were operated under the same conditions, 25
The cumulative number of failures was 1 at 00 hours, 5 at 3000 hours, and 14 at 3500 hours.
１皿ｍ翌見災工Ａよ及ｌ
よって、本発明は、上述した欠点のない新規な半導体装
置を提案せんとづるものである。Therefore, the present invention proposes a novel semiconductor device that does not have the above-mentioned drawbacks.
本発明による半導体装置は、第３図及び第４図で上述し
た従来の半導体装置の場合と同様に、半導体素子と、そ
の半導体素子に連結し且つ遊端にパッド部を４ｉ”ｌる
配線層とを形成して（′Ｘる半導体基板を有し、その配
線層のパッド部に外部導出用線の一端が圧溶接されてい
る、という構成を有する。The semiconductor device according to the present invention, as in the case of the conventional semiconductor device described above with reference to FIGS. It has a structure in which a semiconductor substrate is formed and one end of an external lead wire is pressure welded to a pad portion of the wiring layer.
しかしながら、本発明による半導体装置は、このような
構成を右する半導体装置にＪ３いて、その外部導出用線
が金でなり、また、配線層が、少なくともパッド部にお
いて、ゲルマニウムを０．０５〜３０ａ【０ＩＩ１％、
望ましくは０．１〜２５ａｔｏｍ％含んでいるアルミニ
ウムでなる、という構成を有づる。However, the semiconductor device according to the present invention is a semiconductor device having such a structure, and its external lead wire is made of gold, and the wiring layer is made of germanium of 0.05 to 30 μm at least in the pad portion. 0II1%,
The structure is preferably made of aluminum containing 0.1 to 25 atom%.
作 用
このような構成を有する本発明による半導体装置によれ
ば、それが、第３図及び第４図で上述した従来の半導体
装置において、その半導体装置が、少くともそのパッド
部に対応するパッド部において、ゲルマニウムを０．０
５〜３０ａｔｏｎ＋％、望ましくは０ 、１〜２５ ａ
ｔｏｍ％含んでいるアルミニウムでなる配線層に置換さ
れていることを除いて、第３図及び第４図で上述した従
来の半導体装置の場合と同様の構成を有するので、第３
図及び第４図で上述した従来の半導体装置の場合と屑様
に、半導体装置としての動作を得ることができる。According to the semiconductor device according to the present invention having such a configuration, in the conventional semiconductor device described above in FIGS. 3 and 4, the semiconductor device has at least a pad corresponding to the pad portion. In the part, germanium is 0.0
5 to 30 aton+%, preferably 0, 1 to 25 a
The structure is similar to that of the conventional semiconductor device described above in FIGS. 3 and 4, except that the wiring layer is replaced with a wiring layer made of aluminum containing aluminum.
The operation as a semiconductor device can be obtained in the same manner as in the case of the conventional semiconductor device described above with reference to FIGS.
しかしながら、この場合、半導体基板に形成されている
配線層と、外部導出用線との間の連結は、配線層が、少
くともパッド部において、ゲルマニウムを０．０５〜３
０ａｔｏｍ％、望ましくは０．１〜２５ａｔｏｍ％の量
含んでいるアルミニウムでなり、外部導出用線が金でな
ることにより、その金でなる外部導出用線が、ゲルマニ
ウムを０．０５〜３０８ｔＯ！１％、望ましくは０．１
〜２５ａｔｏｍ％の徂含んでいるパッド部に圧溶接して
、アルミニウムと、ゲルマニウムと、金とが合金化して
得られて′おり、そして、その合金化は、外部導出用線
を構成している金とパッド部を構成しているアルミニウ
ムとが、反応し易いとしてもゲルマニウムを有している
ので、比較的長い期間使用しても、その進行が、ゲルマ
ニウムによって抑圧され、このため、半導体装置が、比
較的長い使用期間において、熱サイクルを受けても、第
３図及び第４図で上述した従来の場合のように、配線層
と外部導出用線との間の連結が、比較的短い使用期間で
、不安定な状態になったり、断線状態になったりするこ
とがない。However, in this case, the connection between the wiring layer formed on the semiconductor substrate and the external lead-out line is such that the wiring layer contains 0.05 to 3% germanium at least in the pad portion.
0 atom%, preferably 0.1 to 25 atom% of aluminum, and the external lead wire is made of gold, so that the external lead wire made of gold contains germanium in an amount of 0.05 to 308 tO! 1%, preferably 0.1
It is obtained by pressure welding to the pad portion containing ~25 atom% and alloying aluminum, germanium, and gold, and this alloy constitutes the wire for external lead-out. Even though gold and aluminum forming the pad portion easily react with each other, they contain germanium, so even if used for a relatively long period of time, the progress of this reaction is suppressed by germanium, which causes the semiconductor device to deteriorate. , even if it is subjected to thermal cycles during a relatively long period of use, as in the conventional case described above in FIGS. 3 and 4, the connection between the wiring layer and the external lead line is There will be no instability or disconnection during the period.
なお、配線層が、少くともパッド部にＪ３いて、ゲルマ
ニウムを３０ａｔｏｍ％以上のネ○んでいるアルミニウ
ムの場合は、上述した効果は得られても、パッド部が比
較的太なる硬度を有プるため、パッド部への外部導出用
線の圧溶接に困難を伴い、また、ゲルマニウムを０．０
５ ａｔ。In addition, if the wiring layer is made of aluminum containing J3 at least in the pad part and containing 30 atom% or more of germanium, even though the above-mentioned effect can be obtained, the pad part has a hardness that is relatively thick. Therefore, it is difficult to pressure weld the external lead wire to the pad part, and germanium is 0.0
5 at.
ｍ％以下の聞しか含んでいないアルミニウムの場合は、
上述した効果が顕著に１ｑられない。また、その意味に
Ｊ５いて、配線層は、少くともそのパッド部において、
ゲルマニウムを０．１〜２５ａｔｏｍ％の晶含んでいる
のが望ましい。In the case of aluminum containing only m% or less,
The above-mentioned effects are not significantly improved. In addition, in J5, the wiring layer is at least in its pad part.
It is desirable that the crystal contains germanium in an amount of 0.1 to 25 atom%.
発明の効果
従って、本発明による半導体装置によれば、半導体装置
としてのＩＪＪ作が、第３図及び第４図ｒト述した従来
の半導体装置の場合に比し、格段的に長い使用期間にお
いて、安定に１ｑられる。Effects of the Invention Therefore, according to the semiconductor device according to the present invention, the IJJ operation as a semiconductor device can be used for a much longer period of time than in the case of the conventional semiconductor device shown in FIGS. 3 and 4. , stable 1q.
実施例１
第１図は、本発明による半導体装置の第１の実施例を示
１゜
第１図において、第３図との対応部分には同一符号を付
して、詳細説明を省略する。Embodiment 1 FIG. 1 shows a first embodiment of a semiconductor device according to the present invention. In FIG. 1, parts corresponding to those in FIG.
第１図に示す本発明による半導体装置は、次の事項を除
いて、第１図で上述した従来の半導体装置と同様の構成
を有する。The semiconductor device according to the present invention shown in FIG. 1 has the same configuration as the conventional semiconductor device described above in FIG. 1, except for the following points.
寸なわら、外部導出用線１２が、第１図で上述した従来
の半導体装置の場合と同様に、金でなる外部導出用線１
２でなるが、外部導出用線１２がその一端において圧溶
接される半導体基板１に形成されている配線層２が、少
なくともそのパッド部３に対応しているパッド部３′に
おいて、ゲルマニウムを０．０５〜３０ａｔｏｍ％、望
ましくは０．１〜２５ａｔｏｍ％の慴含んでいるアルミ
ニウムでなる配線層２′に置換されている。However, as in the case of the conventional semiconductor device described above in FIG. 1, the external lead wire 12 is made of gold.
2, the wiring layer 2 formed on the semiconductor substrate 1 to which the external lead wire 12 is pressure welded at one end is free of germanium at least in the pad portion 3' corresponding to the pad portion 3. The wiring layer 2' is made of aluminum containing 0.05 to 30 atom %, preferably 0.1 to 25 atom %.
なお、少なくともパッド部３′において、ゲルマニウム
を０．０５〜３０ ａｔｏｍ％、望ましくは０．１〜２
５ａｔｏｍ％の母含んでいるアルミニウムでなる配線層
２′は、半導体基板１上に、ゲルマニウムを含んでいる
アルミニウム、またはアルミニウムとゲルマニウムとの
合金を蒸着させて配線層２′を形成することによって、
また、半導体基板１上にアルミニウムを蒸着させ、次に
、またはその曲にゲルマニウムを蒸着させ、次に熱処理
を行って、配線層２′を形成することによって、もしく
は、アルミニウムを蒸着させてアルミニウムでなる層を
形成し、次に、その遊端部上にマクスを用いて、ゲルマ
ニウムを蒸着させ、次に、熱処理を行うことによって、
形成することができる。At least in the pad portion 3', germanium is contained in an amount of 0.05 to 30 atom%, preferably 0.1 to 2 atom%.
The wiring layer 2' made of aluminum containing 5 atom% is formed by depositing aluminum containing germanium or an alloy of aluminum and germanium on the semiconductor substrate 1.
Alternatively, aluminum can be deposited on the semiconductor substrate 1, germanium can be deposited next or on the semiconductor substrate 1, and then heat treatment can be performed to form the wiring layer 2'. By forming a layer of and then depositing germanium on the free end using a max, and then performing a heat treatment,
can be formed.
以上が、本発明による半導体装置の第１の実施例の構成
である。The above is the configuration of the first embodiment of the semiconductor device according to the present invention.
このような構成を有Ｊ−る半導体装置によれば、それが
、上述した事項を除いて、第３図で上述した従来の半導
体装置の場合と同様の構成を有するので、詳細説明は省
略するが、第３図で上述したと同様に、外部連結用端子
ハ１０を介して、半導体装置としての動作を（りること
ができる。A semiconductor device having such a configuration has the same configuration as the conventional semiconductor device described above in FIG. 3, except for the above-mentioned matters, so a detailed explanation will be omitted. However, as described above with reference to FIG. 3, it can operate as a semiconductor device via the external connection terminal 10.
また、第３図で上述した従来の半導体装置の場合と同様
に、外部導出用線１２が金でなり、一方、外部連結用端
子片１０が金または銀でなる表面層を有し、そして、金
でなる外部導出用線１２が、金または銀でなる表面層を
有する外部連結用端子片１０に圧溶接されているので、
詳細説明は省略するが、外部導出用線１２と外部連結用
端子片１０とが、比較的長い使用期間に亘って、熱サイ
クルが与えられても、安定な状態を保っている。Further, as in the case of the conventional semiconductor device described above with reference to FIG. 3, the external lead wire 12 is made of gold, while the external connection terminal piece 10 has a surface layer made of gold or silver, and Since the external lead wire 12 made of gold is pressure welded to the external connection terminal piece 10 having a surface layer made of gold or silver,
Although detailed explanation will be omitted, the external lead wire 12 and the external connection terminal piece 10 maintain a stable state over a relatively long period of use, even when subjected to thermal cycles.
また、外部導出用線１２が金でなり、一方、その一端が
圧溶接される半導体基板１に形成された配線ｍ２’のパ
ッド部３′が、ゲルマニ「クムを０．０５〜３０ａｔＯ
ＩＩ１％、望ましくは０゜１〜２５ａｔｏ１％の…含ん
でいるアルミニウムでなるので、「作用」及び「発明の
効果」で述べたところから明らかであろうから、詳細説
明は省略するが、配線層２′と外部導出用線１２とが、
第３図で上述した従来の半導体装置の場合に比し、格段
的に長い使用期間に亘って、安定な状態を保っている。Further, the external lead wire 12 is made of gold, and the pad portion 3' of the wiring m2' formed on the semiconductor substrate 1, one end of which is pressure welded, is made of germanium "Kum" at 0.05 to 30 atO.
Since it is made of aluminum containing 1% II, preferably 0.1 to 25ato1%, the wiring layer 2' and the external lead-out line 12,
Compared to the conventional semiconductor device described above in FIG. 3, it maintains a stable state over a much longer period of use.
よって、第３図で上述した従来の半導体装置の場合に比
し、長い使用期間に亘って、半導体装置としての動作が
安定に（りられる、という特徴を有する。Therefore, compared to the conventional semiconductor device described above with reference to FIG. 3, the semiconductor device has a feature that the operation as a semiconductor device is stable over a long period of use.
実施例２
第２図は、本発明による半導体装置の第２の実施例を示
す。Embodiment 2 FIG. 2 shows a second embodiment of the semiconductor device according to the present invention.
第２図において、第４図との対応部分には同一符号を付
して、詳細説明を省略する。In FIG. 2, parts corresponding to those in FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted.
第２図に示す本発明による半導体装置は、次の事項を除
いて、第４図で上述した従来の半導体装置と同様の構成
を有する。The semiconductor device according to the present invention shown in FIG. 2 has the same configuration as the conventional semiconductor device described above in FIG. 4, except for the following points.
すなわち、外部導出用線１２がその一端において圧溶接
される半導体基板１に形成されている配線層２が、少な
くともそのパッド部３に対応しているパッド部３′にお
いて、第１図で上述した本発明による半導体装置の場合
と同様に、ゲルマニウムを０．０５〜３Ｑａｔｏｍ％、
望ましくは０，１〜２５ａｔＯＩｌ１％の母含んでいる
アルミニウムでなる配線層２′に置換されている。That is, the wiring layer 2 formed on the semiconductor substrate 1 to which the external lead wire 12 is pressure welded at one end is at least in the pad portion 3' corresponding to the pad portion 3, as described above in FIG. As in the case of the semiconductor device according to the present invention, germanium is added in an amount of 0.05 to 3 Qatom%.
It is preferably replaced with a wiring layer 2' made of aluminum containing 1% of 0.1 to 25 atOIl.
以上が、本発明による半導体装置の第２の実施例の４７
４成である。The above is the 47th embodiment of the second embodiment of the semiconductor device according to the present invention.
It is four generations.
このような構成を右する半導体装置によれば、それが、
−［述した事項を除いて、第４図で上述した従来の半導
体装置の場合と同様の構成を有し、ぞしで、外部連結用
端子片１０が金または銀でなる表面層を右し、また、外
部導出用線１２が金でなり、さらに、その一端が圧溶接
される半導体基板１に形成された配線層２′のパッド部
３′が、ゲルマニウムを０．０５〜３０ ａｔｏｍ％の
吊含んでいるアルミニウムで４ｒるので、詳細説明は省
略するが、第１図でＬｉｆｆ１した本発明による半導体
装置の場合と同様の慢れた作用効采が１０られる。According to a semiconductor device that has such a configuration, it is
- [Except for the above-mentioned matters, the structure is similar to that of the conventional semiconductor device described above in FIG. Further, the external lead-out wire 12 is made of gold, and the pad portion 3' of the wiring layer 2' formed on the semiconductor substrate 1 to which one end thereof is pressure welded is made of germanium in an amount of 0.05 to 30 atom%. Although a detailed explanation will be omitted since the amount of aluminum contained therein is 4r, the same arrogant functions and effects as in the case of the semiconductor device according to the present invention shown as Liff 1 in FIG. 1 can be obtained.
第１図は、本発明による半導体装置の第１の実施例を示
す路線的断面図である。
第２図は、本発明による半導体装置の第２の実施例を示
す路線的断面図である。
第３図及び第４図は、それぞれ従来の半導体装置を示す
路線的断面図である。
１・・・・・・・・・・・・・・・半導体基板２．２′
・・・・・・配線層
３．３′ ・・・・・・パッド部
５・・・・・・・・・・・・・・・ケース体６・・・・
・・・・・・・・・・・底板部７・・・・・・・・・・
・・・・・側壁部８・・・・・・・・・・・・・・・上
板部９．１０・・・・・・外部連結用端子片１２・・・
・・・・・・・・・・・・外部導出用線２１・・・・・
・・・・・・・・・・合成樹脂材出願人 日本電信電
話株式会社
第１図
第２図FIG. 1 is a cross-sectional view showing a first embodiment of a semiconductor device according to the present invention. FIG. 2 is a cross-sectional view showing a second embodiment of the semiconductor device according to the present invention. FIGS. 3 and 4 are sectional views showing conventional semiconductor devices, respectively. 1... Semiconductor substrate 2.2'
・・・・・・Wiring layer 3.3' ・・・・・・Pad part 5・・・・・・・・・・・・Case body 6...
・・・・・・・・・・・・Bottom plate part 7・・・・・・・・・・・・
...Side wall part 8...Top plate part 9.10...Terminal piece for external connection 12...
......External lead-out line 21...
......Synthetic resin material applicant Nippon Telegraph and Telephone Corporation Figure 1 Figure 2
Claims (1)
部を有する配線層とを形成している半導体基板を有し、
上記配線層のパッド部に、外部導出用線の一端が圧溶接
されている半導体装置において、 上記外部導出用線が金でなり、 上記配線層が、少なくともそのパッド部において、ゲル
マニウムを０．０５〜３０ａｔｏｍ％の量含んでいるア
ルミニウムでなることを特徴とする半導体装置。[Scope of Claims] A semiconductor substrate having a semiconductor element and a wiring layer connected to the semiconductor element and having a pad portion at a free end,
In a semiconductor device in which one end of an external lead-out line is pressure-welded to a pad portion of the wiring layer, the external lead-out line is made of gold, and the wiring layer contains 0.05% germanium at least in its pad portion. A semiconductor device comprising aluminum containing aluminum in an amount of ~30 atom%.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60172039A JPS6232628A (en) | 1985-08-05 | 1985-08-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60172039A JPS6232628A (en) | 1985-08-05 | 1985-08-05 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6232628A true JPS6232628A (en) | 1987-02-12 |
Family
ID=15934392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60172039A Pending JPS6232628A (en) | 1985-08-05 | 1985-08-05 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6232628A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63278343A (en) * | 1987-05-11 | 1988-11-16 | Hitachi Ltd | Solid state electronic device |
| JPH04150044A (en) * | 1990-10-12 | 1992-05-22 | Nec Corp | Semiconductor device |
-
1985
- 1985-08-05 JP JP60172039A patent/JPS6232628A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63278343A (en) * | 1987-05-11 | 1988-11-16 | Hitachi Ltd | Solid state electronic device |
| JPH04150044A (en) * | 1990-10-12 | 1992-05-22 | Nec Corp | Semiconductor device |
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