JPS6232620B2 - - Google Patents

Info

Publication number
JPS6232620B2
JPS6232620B2 JP60054454A JP5445485A JPS6232620B2 JP S6232620 B2 JPS6232620 B2 JP S6232620B2 JP 60054454 A JP60054454 A JP 60054454A JP 5445485 A JP5445485 A JP 5445485A JP S6232620 B2 JPS6232620 B2 JP S6232620B2
Authority
JP
Japan
Prior art keywords
heat
heat generating
cap
heat sink
thermally conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP60054454A
Other languages
Japanese (ja)
Other versions
JPS60220953A (en
Inventor
Bunichi Tagami
Fumyuki Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP5445485A priority Critical patent/JPS60220953A/en
Publication of JPS60220953A publication Critical patent/JPS60220953A/en
Publication of JPS6232620B2 publication Critical patent/JPS6232620B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/42Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
    • H01L23/433Auxiliary members in containers characterised by their shape, e.g. pistons
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Description

【発明の詳細な説明】 本発明は、半導体集積回路素子等を搭載する回
路パツケージに係り、特に素子で発生する熱を熱
伝導により外部へ放散する回路パツケージに関す
る。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit package on which a semiconductor integrated circuit element or the like is mounted, and more particularly to a circuit package that dissipates heat generated in the element to the outside by thermal conduction.

半導体素子の高集積化に伴い、素子外部との接
続点数が増大してきた。一方、半導体素子を用い
た電子装置の小型化及び高速化への要請は強く、
半導体素子をより高密度に実装する必要がある。
フリツプチツプ方式は、半導体素子の外部端子数
の増大化及び配線基板上に高密度実装を施すため
に有効な手段として知られている。
As semiconductor devices become more highly integrated, the number of connection points with the outside of the device has increased. On the other hand, there is a strong demand for smaller and faster electronic devices using semiconductor elements.
It is necessary to package semiconductor elements with higher density.
The flip-chip method is known as an effective means for increasing the number of external terminals of a semiconductor device and for high-density mounting on a wiring board.

しかし、フリツプチツプ方式は半導体素子と配
線基板との接続が半田バンプ部に限定されるため
半導体素子の裏面全体を金シリコン共晶合金等で
基板に直接取り付ける方法と比較すると熱放散性
が悪いという欠点がある。
However, in the flip-chip method, the connection between the semiconductor element and the wiring board is limited to the solder bump area, so the disadvantage is that heat dissipation is poor compared to a method in which the entire back surface of the semiconductor element is directly attached to the board using gold-silicon eutectic alloy, etc. There is.

上記欠点のために大発熱量の半導体素子をフリ
ツプチツプ方式で基板に搭載することができず、
高速素子を高密度に実装することができなかつ
た。
Due to the above drawbacks, it is not possible to mount semiconductor elements that generate a large amount of heat on a board using the flip-chip method.
It was not possible to package high-speed devices with high density.

上記欠点を補い良好な熱放散性を確保するため
の手段として、特開昭53―31968で示される方法
がある。上記方法では、熱発生素子あるいは熱伝
導性キヤツプの一方の表面に金属塊を治金的に接
着して他方の面に押しつけることで熱伝導路を形
成している。この方法では、金属塊を一方の面に
あらかじめ固着させる必要がある。金属塊を素子
側に固着させることは、素子製造工程を一層複雑
にして歩留低下を招くことになる。また、多数の
素子を基板に搭載する場合には、欠陥素子を交換
したり接続の補修がしばしば必要となる。このた
めキヤツプ側に金属塊を固着させた場合には再処
理のたびにキヤツプを交換する必要が生じる。こ
れは金属塊が既に変形しているため、再利用する
と素子表面との十分な接触が保証されないためで
ある。
As a means to compensate for the above drawbacks and ensure good heat dissipation, there is a method disclosed in Japanese Patent Application Laid-Open No. 53-31968. In the above method, a metal block is metallurgically bonded to one surface of a heat generating element or a heat conductive cap and pressed against the other surface to form a heat conduction path. This method requires that the metal block be pre-fixed to one side. Fixing the metal lump to the element side further complicates the element manufacturing process and causes a decrease in yield. Furthermore, when a large number of elements are mounted on a substrate, it is often necessary to replace defective elements or repair connections. For this reason, if a metal lump is attached to the cap side, it becomes necessary to replace the cap every time the cap is reprocessed. This is because the metal block has already been deformed, and therefore sufficient contact with the element surface cannot be guaranteed if it is reused.

本発明の目的は、変形可能で良好な熱伝導性シ
ートを熱発生素子に密着させ良好な熱放散性を有
する回路パツケージを提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a circuit package which has good heat dissipation properties by closely adhering a deformable and good heat conductive sheet to a heat generating element.

フリツプチツプ方式等により基板に装着された
半導体素子等の熱発生素子から外部に熱を放散さ
せるためには、熱発生素子に熱伝性物質を直接密
着させ熱伝導により熱を放熱部に導くことが有効
である。一体成形されたヒートシンクを一括して
熱発生素子に押しつけることは、該素子を支持す
る基板の反り及び該素子と基板を接続する半田接
続部の高さばらつき等により、素子あるいは半田
接続部の破損を引き起したり逆に接触しない等の
不都合が生する。
In order to dissipate heat to the outside from a heat generating element such as a semiconductor element mounted on a board using the flip-chip method, it is necessary to directly attach a heat conductive material to the heat generating element and guide the heat to the heat dissipating part by thermal conduction. It is valid. Pressing an integrally formed heat sink against a heat generating element at once may cause damage to the element or the solder connection due to warping of the board supporting the element and variations in the height of the solder connection that connects the element and the board. This may cause inconveniences such as causing a problem or not making contact.

熱発生素子及び半田接続部に損傷を与えず、か
つ密着性を確保するために、従来は素子毎にピス
トン状のヒートシンクをスプリングで押しつけた
りあるいはヒートシンク側に軟質金属を固着させ
る方法を用いていた。上記方法では、ピストン等
の機構部品を多量に使用するため小型化が計れず
またあらかじめ軟質金属を固着させる工程が必要
であつた。
In order to prevent damage to heat generating elements and solder connections and to ensure adhesion, conventional methods used methods such as pressing a piston-shaped heat sink against each element with a spring or fixing soft metal to the heat sink side. . In the above method, a large number of mechanical parts such as pistons are used, so miniaturization cannot be achieved, and a step of fixing soft metal in advance is required.

上記不都合点を改良するため、ヒートシンク側
の熱伝性キヤツプ表面と熱発生素子表面の間に基
板の反り及び接続部の高さばらつきを吸収できる
軟質で変形な熱伝導性シートを含む手段を挿入し
て、該キヤツプと該基板を相対的に押しつけるこ
とで素子及び接続部に損傷を与えることなく上記
両表面との密着を計り良好な熱伝導路を形成す
る。
In order to improve the above disadvantages, a means including a soft and deformable thermally conductive sheet that can absorb the warpage of the board and the height variation of the connection part is inserted between the surface of the thermally conductive cap on the heat sink side and the surface of the heat generating element. By pressing the cap and the substrate relative to each other, the cap and the substrate are brought into close contact with both surfaces without damaging the element or the connecting portion, thereby forming a good heat conduction path.

以下、本発明の一実施例を第1図により説明す
る。第1図に於て10は半導体素子、11は半田
20は配線基板、21は外部接続用のピン、22
はフランジ、30は熱伝導性キヤツプ、31は軟
質金属の熱伝導性シート、32はシート位置決め
用のガイドピン、40は冷却液を示す。
An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, 10 is a semiconductor element, 11 is solder 20 is a wiring board, 21 is an external connection pin, 22
30 is a flange, 30 is a thermally conductive cap, 31 is a soft metal thermally conductive sheet, 32 is a guide pin for sheet positioning, and 40 is a cooling liquid.

半導体素子10は、通常セラミツクで形成され
た多層配線基板20の一方の面に半田11を用い
たフリツプチツプ法により装着されている。上記
配線基板の他方の面には接続用のピン21が設け
られており、このモジユールを上位レベルのボー
ドに接続する。キヤツプ30はフランジ22を介
して基板20に取り付けられる。キヤツプはアル
ミニウム若しくは銅等の熱伝導率の良い材料で作
られており、キヤツプまで伝導された熱はキヤツ
プ内部に管部を含み、この管部を流れる冷却液に
より外部に放散される。キヤツプ内壁には位置決
め用のピン32が設けられており、ピン32に熱
伝導性シート31が取りつけられる。シート31
はインジウム等の軟質金属で形成されており、フ
ランジにキヤツプを取りつける際の圧力により変
形して半導体素子及び半田接続部に損傷を与える
ことなく半導体素子表面及びキヤツプ内壁表面に
密着して間隙を埋める。上記のごとく半導体素子
とキヤツプの間隙が軟質金属で充填されること
で、良好な熱伝導路が形成され、半導体素子で発
生した熱はシート31を介した熱伝導により効率
良くキヤツプ30に導かれる。また、シートの半
導体素子との接触面は半導体素子表面より小さい
凸状の面に成形されている。これは、基板20と
キヤツプ30の熱膨脹率の違いによる歪が、半田
接続部11に過度に印加されないようにしたもの
で、第2図に示すごとく平行平板のシートを使用
した場合は圧力を加えて変形させるという半導体
素子がシートに埋め込まれた状態となり上記歪が
直接半田接続部に加わり半田が破損する恐れがあ
る。
The semiconductor element 10 is mounted on one surface of a multilayer wiring board 20, which is usually made of ceramic, by a flip-chip method using solder 11. Connecting pins 21 are provided on the other side of the wiring board to connect this module to a higher level board. Cap 30 is attached to substrate 20 via flange 22. The cap is made of a material with good thermal conductivity, such as aluminum or copper, and the heat conducted to the cap includes a tube section inside the cap, and is dissipated to the outside by a cooling liquid flowing through the tube section. A positioning pin 32 is provided on the inner wall of the cap, and a thermally conductive sheet 31 is attached to the pin 32. sheet 31
The cap is made of a soft metal such as indium, and deforms due to the pressure when attaching the cap to the flange, so that it adheres tightly to the surface of the semiconductor element and the inner wall of the cap without damaging the semiconductor element or the solder connections, filling the gap. . As described above, by filling the gap between the semiconductor element and the cap with soft metal, a good heat conduction path is formed, and the heat generated in the semiconductor element is efficiently guided to the cap 30 by heat conduction through the sheet 31. . Further, the contact surface of the sheet with the semiconductor element is formed into a convex surface smaller than the surface of the semiconductor element. This is to prevent strain caused by the difference in thermal expansion coefficients between the board 20 and the cap 30 from being excessively applied to the solder joint 11. When a parallel flat sheet is used as shown in Figure 2, pressure is applied. The semiconductor element becomes deformed by being embedded in the sheet, and the above-mentioned strain is applied directly to the solder connection part, and there is a risk that the solder may be damaged.

本発明によれば、半導体素子及び半田接続部に
損傷を与えることなく半導体素子と熱伝導性キヤ
ツプとの間に挿入した熱伝導性シートを素子の表
面に密着させることができ、半導体素子で発生し
た熱を熱伝導により効率良くヒートシンク(熱伝
導性キヤツプ)に導くことができる。
According to the present invention, the thermally conductive sheet inserted between the semiconductor element and the thermally conductive cap can be brought into close contact with the surface of the element without damaging the semiconductor element or the solder connection part. The generated heat can be efficiently guided to the heat sink (thermal conductive cap) by thermal conduction.

また、複雑な機構や工程を必要とせず、装置の
小型化や作業の簡略化が計れる。
Further, the device does not require any complicated mechanism or process, and the device can be made smaller and the work can be simplified.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は基板にキヤツプを取りつけた本発明の
装置の断面図、第2図は平行平板シートを用いた
ときの従来の部分拡大断面図である。 10……半導体素子、11……半田、20……
配線基板、30……熱伝導性キヤツプ、31……
熱伝導性シート、40……冷却液。
FIG. 1 is a cross-sectional view of the device of the present invention in which a cap is attached to a substrate, and FIG. 2 is a partially enlarged cross-sectional view of a conventional device using parallel flat sheets. 10...Semiconductor element, 11...Solder, 20...
Wiring board, 30... Thermal conductive cap, 31...
Thermal conductive sheet, 40...Cooling liquid.

Claims (1)

【特許請求の範囲】[Claims] 1 複数の熱発生素子を支持する基板と、ヒート
シンクと、上記ヒートシンク表面と上記複数の熱
発生素子表面との間に配置され、上記複数の熱発
生素子側の表面であつて、上記基板状の複数の熱
発生素子の夫々の表面に対向する位置に、当該対
向する熱発生素子の表面形状よりも小さい形状を
有する頂上表面を持つ凸状起が成形された軟質で
変形可能な熱伝導性シートを含む手段を有し、上
記熱伝導性シートを含む手段の各凸状起頂上表面
を上記対向する上記各熱発生素子に密着圧力を加
え変形させると伴に、上記熱伝導性シートを含む
手段の上記ヒートシンク側の表面を上記ヒートシ
ンクに固着し、上記熱発生素子で発生した熱を熱
伝導により上記ヒートシンクへ導くことを可能に
した回路パツケージ。
1. A substrate supporting a plurality of heat generating elements, a heat sink, and a surface disposed between the surface of the heat sink and the surface of the plurality of heat generating elements, the surface facing the plurality of heat generating elements; A soft and deformable thermally conductive sheet in which a convex shape having a top surface having a shape smaller than the surface shape of the opposing heat generating element is formed at a position facing the surface of each of the plurality of heat generating elements. and deforming each convex raised surface of the means including the thermally conductive sheet by applying contact pressure to each of the opposing heat generating elements, and the means including the thermally conductive sheet. A circuit package in which a surface on the heat sink side of the circuit package is fixed to the heat sink so that heat generated by the heat generating element can be guided to the heat sink by thermal conduction.
JP5445485A 1985-03-20 1985-03-20 Package for circuit Granted JPS60220953A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5445485A JPS60220953A (en) 1985-03-20 1985-03-20 Package for circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5445485A JPS60220953A (en) 1985-03-20 1985-03-20 Package for circuit

Publications (2)

Publication Number Publication Date
JPS60220953A JPS60220953A (en) 1985-11-05
JPS6232620B2 true JPS6232620B2 (en) 1987-07-15

Family

ID=12971126

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5445485A Granted JPS60220953A (en) 1985-03-20 1985-03-20 Package for circuit

Country Status (1)

Country Link
JP (1) JPS60220953A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS566460A (en) * 1979-06-29 1981-01-23 Ibm Multi chip module

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57146347U (en) * 1981-03-06 1982-09-14

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS566460A (en) * 1979-06-29 1981-01-23 Ibm Multi chip module

Also Published As

Publication number Publication date
JPS60220953A (en) 1985-11-05

Similar Documents

Publication Publication Date Title
US7005743B2 (en) Semiconductor device using bumps, method for fabricating same, and method for forming bumps
US5430611A (en) Spring-biased heat sink assembly for a plurality of integrated circuits on a substrate
US7440282B2 (en) Heat sink electronic package having compliant pedestal
US4034468A (en) Method for making conduction-cooled circuit package
JP3196762B2 (en) Semiconductor chip cooling structure
US7413926B2 (en) Methods of making microelectronic packages
JP3150351B2 (en) Electronic device and method of manufacturing the same
JP5983032B2 (en) Semiconductor package and wiring board unit
JP3259420B2 (en) Flip chip connection structure
GB2279807A (en) A heat sink assembly for a multi-chip module
JPH11354677A (en) Method and structure for mounting semiconductor device
US20050274882A1 (en) Optical device and method for fabricating the same
JPH06196598A (en) Mounting structure for semiconductor chip
JPH1032305A (en) Multichip module
JPH11121662A (en) Cooling structure for semiconductor device
JP4415988B2 (en) Power module, heat sink, and heat sink manufacturing method
JPS6232620B2 (en)
JPH04315458A (en) Multilayered wiring board
JP3113400B2 (en) Electronic circuit device
JP3134860B2 (en) Hybrid integrated circuit device
JPH07142532A (en) Circuit component mounting structure
JP4770528B2 (en) Electronics
JPH07115153A (en) Mounting structure of module
JPH088563A (en) Mounted radiating device for ic package and electronic device using the same
JPH098185A (en) Package with electronic-component cooling structure and its manufacture