JPS6232400Y2 - - Google Patents

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to the improvement of RAM (random access memory) circuits.

<Prior art> As described in Japanese Patent Laid-Open No. 53-45939, as a static RAM circuit consisting of a CMOS configuration, a write circuit is connected between an inverter circuit In ₁ and a power supply -V and ground as shown in FIG. Switching elements T _N3 , T to which timing signals W, are input
A circuit connecting _P3 has been put into practical use. FIG. 5 shows an operation timing chart of the RAM circuit.

According to the RAM circuit shown in FIG _. 4 above, the output inverter circuit In ₁ of the RAM cell is provided with MOS transistors T _N3 and T _P3 that are turned off during writing. It is only necessary to apply the output potential to the input terminal of the second inverter circuit In ₂ in the cell, and therefore to the transistors of the write inverter circuit In ₃ and the transistors T _P1 , T _P2 , T _P3 , T _N1 , T in the RAM cell. There are many advantages such as there is no need to consider the resistance ratio of _N2 and T _N3 , and since no DC path is formed, power consumption can be reduced.

<Problems to be solved by the invention> However, in the above RAM circuit, the bit line L is usually configured by interconnecting a large number of RAM cells, so the bit line wiring is smaller than the point A in each cell. The capacity has a fairly large value. Therefore, immediately after the digit selection signal Row becomes high level, the transmission gate TR becomes conductive, and the RAM cell is selected, the potential at point A within the cell becomes -
V _A =-VR _P2 +R _P3 /R ₁ +R _P2 +R _P3 . However, each resistance in the above formula is as shown in the equivalent circuit diagram in Figure 6.
R ₁ : On-resistance of MOS transistors T _P1 and T _N1 of transmission gate TR, combined resistance of R _P1 and R _N1 , R _P2 and R _P3 indicate on-resistance of MOS transistors T _P2 and T _P3 , and This shows the potential when the bit line L is charged to -V while the RAM cell information is at a high level.

Therefore, even if the RAM cell information is originally in a state where a high level must be transmitted to the bit line L, depending on the relationship between the inversion level of the second inverter circuit _In2 and the potential at point A -V _A , As shown by the broken line in FIG. 5, the potential at each point is affected by the previous potential, and there is a risk that the contents stored in the cell may be destroyed. To prevent this, the transmission gate
Regarding the on-resistance R ₁ of the TR and the on-resistances R _P2 and R _P3 of the first inverter circuit, it is necessary to satisfy the following condition: R ₁ >>R _P2 +R _P3 . Furthermore, the first inverter circuit
The MOS transistors T _N2 and T _N3 of In ₁ also need to satisfy the same conditions as the transmission gate TR. In order to satisfy these conditions in terms of the circuit, the MOS transistors T _P2 ,
On-resistance of T _P3 , T _N2 , T _N3 R _P2 , R _P3 , R _N2 ,
This is achieved by lowering R _N3 , but for this purpose, MOS transistors T _P2 , T _P3 , T _N2 , T _N3
On the other hand, increasing the on-resistance _R1 of the transmission gate TR would have a negative effect on the readout speed, which is undesirable. In any case, in conventional RAM circuits, actual RAM circuits were designed taking into account the read speed and the shape and dimensions of the RAM cells. Therefore, the circuit design becomes extremely complicated, and it is difficult to design a circuit that fully satisfies both conditions.

The present invention provides a RAM circuit which can eliminate the drawbacks of the conventional circuits described above by simply adding a simple configuration and can obtain stable write and read operations.

<Means for solving the problem> A memory circuit configured by connecting an input inverter circuit and an output inverter circuit in a CMOS configuration in a ring, a bit line, and an input point between the bit line and the input inverter circuit ( That is, a transmission gate consisting of a MOS transistor connected between the output point of the output inverter circuit and turned on during reading and writing, and a writing CMOS inverter whose output point is connected to the bit line. The output inverter circuit comprises a first N-channel MOS transistor to which the output of the input inverter circuit is input to its gate, and a control signal which is at a low level at least during writing is input to its gate. second N-channel
N channel connected in series with MOS transistor
a MOS transistor circuit, a first P-channel MOS transistor to which the output of the input inverter circuit is input to its gate, and a second P-channel MOS transistor to which a control signal that is at a high level at least during writing is input to its gate. and a P-channel MOS transistor circuit connected in series between the first and second power supply potentials, and the N-channel MOS transistor circuit and the P-channel MOS transistor circuit
In a RAM circuit having a configuration in which a connection point with a channel MOS transistor circuit is an output point, a means is provided for setting the bit line to a predetermined potential before a read operation.

<Operation> With the above configuration, the first and second
One of the N-channel MOS transistor circuit and the P-channel MOS transistor circuit connected between the power supply potential of the output inverter circuit and the output point of the output inverter circuit is It is possible to eliminate the need to consider the on-resistance ratio.

<Example> Next, a detailed explanation will be given with reference to examples.

In Figure 1, the RAM cells are composed of a first inverter circuit In ₁ and a second inverter circuit consisting of a CMOS configuration.
A flip _- flop circuit is formed by connecting the input and output lines to each other, and a transmission gate TR is connected between the output inverter _In1 and the bit line L. Especially the first inverter circuit In ₁
An N-channel MOS transistor T _N11 is connected between the power supply and V, and a P-channel MOS transistor is connected between the ground and the
A MOS transistor T _P11 is connected, a write timing signal W is applied to the gate of the P channel MOS transistor T _P11 , and a transmission gate is applied to the gate of the N channel MOS transistor T _N11 .
The digit selection signal R _{OW r} inputted to the TR is commonly inputted, and the number of signals introduced to the RAM cells is reduced compared to the above-mentioned conventional circuit.

A large number of RAM cells with the circuit configuration described above are connected to share the bit line L, and the bit line L is further connected to a write inverter circuit In ₃ to which a write signal Din is applied, and a timing signal for reading out the potential of the bit line L. A read inverter circuit _In4 leading to the output line Dout is connected to R. As shown in FIG. 3, both inverter circuits are constructed by connecting a CMOS inverter circuit consisting of a pair of N-channel MOS and P-channel MOS to a switching element whose gate receives a write timing signal W or read timing signal R. ing.

A precharge N-channel MOS transistor T _N0 is connected between the bit line L and the power supply -V, and its gate is supplied with a clock signal φ _r generated at the timing described below.

Next, using the timing chart in Figure 2,
Explain the operation of RAM circuit.

Before instructing the access operation of the RAM cell, first, in order to make the RAM cell connected to the bit line L into a non-selected state, an AND output of the digit selection signal _ROW and the clock signal _r is applied to the digit selection line. Turn off each transmission gate TR. While the transmission gate TR is kept off, the precharge MOS transistor T _N0 is made conductive by the clock signal φ _r and the bit line L is charged to the level of the power supply -V. Therefore, the precharge of the bit line by the above clock signal _φr is
Since it is executed prior to the read and write operations in the RAM cell, the clock signal φ _r is applied to the precharge MOS transistor T _N0 before the read operation or after the write operation is completed.
Following the precharge above, the next to be selected is
A high-level digit selection signal R _O is applied to the digit selection line of the RAM cell.
_W is applied to access the RAM cell in a readable state. While the digit selection signal _ROW is kept at a high level, the read timing signal R
Subsequently, the write timing signal W is sent to the read inverter circuit In 4 and the write inverter circuit In ₄ , respectively.
The contents of the RAM _cell are read out to the output line Dout via the bit line, and the contents applied to the input line Din are written to the RAM cell.

In the read and write operations of the RAM cell, the bit line L is charged to the level of the power supply -V in advance prior to the access operation of the RAM cell.
Consideration of the on-resistance value between MOSs is important for the output inverter.
Only the MOS transistors T _P11 and T _P12 and the transmission gate TR of In ₁ are required, and there is no need to consider the other MOS transistors T _N11 and T _N12 , which are turned off while the cell is in the selected state. You may do so. In this example,
Since the R _{OW r} signal is input to the gate of the MOS transistor T _N11 , it is in an off state while it is selected. During the write operation, the MOS transistors T _P11 and T _N11 , which are switching elements connected to the output inverter circuit, are both in the off state, so there is no need to consider the ratio with the write inverter circuit _In3 .

<Effects of the Invention> According to the RAM circuit of the present invention, by providing a means for setting the bit line to a predetermined potential in advance prior to the read operation, the resistance ratio is an element that must be taken into consideration during circuit design. This makes it easier to design, and the restrictions on cell size are relaxed, resulting in miniaturization. In addition, by lowering the on-resistance of the MOS transistors T _P11 and T _P12 , it is possible to lower the on-resistance of the transmission gate.
It is possible to speed up the write operation.

It should be noted that the same implementation can be achieved even if the P-channel MOS and N-channel MOS circuits of the embodiment are respectively reversed.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment according to the present invention, Fig. 2 is a signal waveform diagram for explaining the embodiment, Fig. 3 is a circuit diagram of the main part of the embodiment, and Fig. 4 is a conventional main part.
FIG. 5 is a signal waveform diagram for explaining the operation of FIG. 4, and FIG. 6 is an equivalent circuit diagram of the main part of FIG. 4. Explanation of symbols, In ₁ : Output inverter circuit, In ₃ :
Inverter circuit for writing, In ₄ : Inverter circuit for reading, TR: Transmission gate, T _N
0 : Precharge MOS transistor, L: Bit line, W: Write timing signal, R: Read timing signal.

Claims (1)

[Claims for Utility Model Registration] A memory circuit configured by connecting an input inverter circuit and an output inverter circuit of CMOS configuration in a ring shape, a bit line, and an input point between the bit line and the input inverter circuit (i.e., a transmission gate consisting of a MOS transistor connected between the output point of the output inverter circuit and turned on during reading and writing, and a write CMOS inverter circuit whose output point is connected to the bit line. and the output inverter circuit includes a first N-channel MOS transistor whose gate receives the output of the input inverter circuit, and whose gate receives a control signal that is at a low level at least during writing. An N-channel MOS transistor circuit in which a second N-channel MOS transistor is connected in series, and a first P-channel MOS transistor circuit whose gate is inputted with the output of the input inverter circuit.
A P-channel MOS transistor circuit in which a P-channel MOS transistor is connected in series with a second P-channel MOS transistor whose gate receives a control signal that is at a high level at least during writing is connected between first and second power supply potentials. connected in series with the above N-channel MOS transistor circuit and P
In a RAM circuit having a configuration in which a connection point with a channel MOS transistor circuit is an output point, the first and second The N connected between the second power supply potential and the output point of the output inverter circuit
Channel MOS transistor circuit and P channel
For one of the MOS transistor circuits,
MOS that constitutes the above transmission gate
A RAM circuit characterized by eliminating the need to consider the on-resistance ratio with the transistor.