JPS5853083A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To avoid rewrite, by constituting a source terminal of an FET is connected to a data bus, drain and gate terminals are connected to input terminals of an RAM drive circuit and the drive circuit is floated with an input signal at the gate terminal. CONSTITUTION:When a word line is selected and an RAM cell 24 is not bit-set or bit-reset, a gate input 32 of a TR 33 goes to high level and no data is inputted from a data bus 34. Since a high level of the gate input 32 is an input of a 2-NORs 35, 36, outputs 30, 31 of each drive circuit are floated, the potential balancing of bit lines 26, 27 is not disturbed, the content written in the RAM 24 before is held and rewrite is made unnecessary.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit for driving a random access memory (hereinafter referred to as RAM).

FIG. 1 shows an example of a conventional RAM drive circuit.

The transistor shown in FIG. 1 is assumed to be a P-channel field effect transistor (hereinafter referred to as an MDS transistor or simply a transistor).

In the circuit of FIG. 1, the RAM selected by word line 5
For example, when writing data 1 only to the RAM cell 4 of the cell group (hereinafter referred to as pit set), each gate input 15.13 of the transistor 16.14 becomes a low level, and the data bus 18 is input.

Data 1 is input and RAM drive inverter 11゜12
Accordingly, the signal is transmitted to the pit line 7.8 and written into the RAM cell 4 at the low level timing g63f shown in FIG. Also, the RAM selected by word line 5
Among the cells, other than RAM cell 4 (D, for example, R, AM cell 20, RAM cell 4)
Against, Bi, Tose.

If not, transistor 16 is non-conductive.

Since the transistor 17 is in a conductive state and the transistor 14 is in a conductive state and the word line 5 is selected, the previously written contents are written in the RAM cell 4, and the contents are written in the RAM cell 4. 8, and at the low level timing of 525 shown in Figure 2,
The signal is input to the RAM drive transistors 11 and 12, and rewritten to the RAM cell 4 at the low level timing of φ shown in FIG.

In this way, in the circuit of FIG. 1, the word line is selected Q9R
Among the AM cells, for RAM cells that do not have pits set, 7 is used to rewrite the previously written contents.
1-Docair was required.

The above discussion applies when writing data O to a RAM cell (
Hereinafter, this will be referred to as bit reset. ) is also similar.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit that overcomes these drawbacks.

According to the present invention, a source terminal or a drain terminal of a field effect transistor is connected to a data node, and a drain terminal or a source terminal of the field effect transistor is connected to an input terminal of a random access memory driving circuit, and The gate terminal of a field effect transistor is
A semiconductor integrated circuit having a structure connected to an input terminal of the random access memory driving circuit, and having a structure in which the random access memory driving circuit becomes floating in response to a signal input from the gate terminal of the field effect transistor. The circuit is obtained.

FIG. 3 shows one embodiment of a RAM drive circuit according to the present invention. The present invention is a pit set or a pit set.

There is no need to rewrite previously written contents to RAM cells whose bits are not reset.

The purpose is to prevent the contents of the RAM cell from being destroyed.

In FIG. 3, word line 25 is selected and RAM cell 24
However, when the pit is not set or set, the gate voltage 32 of the transistor 33 is at a high level V, and no data is input from the data bus 34. Furthermore, since the high level of the gate power 32 becomes the input to the 2NORs 35 and 36, the R and AM drive circuit outputs 30 and 31 are in a floating state. Therefore, at the low level of the west, transistors 21°22 conduct, and Bi,)i11126.27
is charged to the power supply voltage, and even though the transistors 28 and 29 are turned on at a low level, each RAMAM drive circuit 31 is in a floating state, so the potential of the bit lines 26 and 27 is not balanced. The R,AM cell 24 can retain previously written contents without disturbing the memory.

The above description has been made regarding a P-channel type MO8 transistor, but the same applies to an N-channel type MO8 transistor or a complementary MOS transistor.

As described above, according to the present invention, a word line is selected. R
There is no need to rewrite previously written contents to RAM cells in the AM cell group that are not pit-set, bit-set, or tri-set.

It has the feature that it does not destroy the contents of the RAM cell.

The present invention is particularly effective when pit setting or bit resetting is performed on a RAM cell in a circuit in which the input to the RAM and the output from the RAM are separated.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional R/AM drive circuit. FIG. 2 is an internal timing diagram used in the circuits of FIGS. 1 and 3. It is a diagram showing one embodiment of an AM drive circuit according to the third company's present invention.

Claims (1)

[Claims] Source terminal or source terminal of a field effect transistor. A drain terminal is connected to the data bus, a drain terminal or a source terminal of the field effect transistor is connected to an input terminal of the random access memory driving circuit, and a gate terminal of the field effect transistor is connected to the random access memory driving circuit. The random access memory drive circuit has a structure connected to an input terminal of the
By inputting a signal to the gate terminal of the field effect transistor. A semiconductor integrated circuit characterized by having a floating structure.