JPS6227474B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit, and more particularly to an integrated circuit including a random access memory (hereinafter referred to as RAM) and its driving circuit.

FIG. 1 shows an example of a conventional RAM drive circuit. The transistor shown in Figure 1 is a P-channel field effect transistor (hereinafter referred to as
Also called MOS transistor or simply transistor. ).

The memory circuit shown in FIG. 1 has a one word/multiple bit configuration in which a plurality of cells are commonly connected to one word line. That is, 1
A plurality of cells 4, 20 (here 2
) are connected,
The cell 4 writes data sent via the data line 18, and reads the written data onto the data line 19. On the other hand, other cells 20 connected to the same word line 5 write data sent through the data line 21 and read the written data to the data line 22. With this configuration, by selecting one word, data can be simultaneously written to multiple cells connected to it.
Data can also be read simultaneously. Therefore, it is generally used as a memory for display data or print data used in display processing or print processing that handles data of multiple bits.
In such a memory circuit, buses 18 and 21 for transferring write data and buses 19 and 22 for transferring read data are provided separately and independently, so that write processing and read processing can be independently controlled. .

Now, when writing data to all cells connected to word line 5 simultaneously, all bit line pairs 7, 8 and 7', 8' are precharged simultaneously. Therefore, the transistors 1, 2, 1', 2' connected to the power supply line 3 receive the precharge signal.
₁ , all bit lines 7, 8,
7' and 8' are simultaneously precharged to the power supply level. Next, the data to be written is transferred to the data line 18, 21 corresponding to each cell, and transistors 14, 16, 14', 16' are connected to each data line and each corresponding cell 4, 20. It turns on in response to signals 13, 15, 13', and 15'.
As a result, the data to be written is transferred to inverter 1.
1 and 11' to transistors 9 and 9', while inverted data is supplied to inverters 12 and 11'.
It is supplied to transistors 10, 10' through 12'. These transistors 9, 9', 10, 1
0' is turned on by the write clock signal ₃ , and true complementary signals are applied to bit lines 7, 8 and 7', 8', respectively. As a result, data is written into each cell 4, 20 in parallel.

Note that each cell 4, 20 connected to the word line 5
When simultaneously reading data from the bit lines 7, 8, 7', and 8', first, the bit lines 7, 8, 7', and 8' are precharged to the power supply level according to the precharge signal ₁ , and then the read transistors 6 and 6' are simultaneously activated by the read clock signal ₂ . It is turned on, and the data of each cell is simultaneously read out to the corresponding data lines 19 and 22.

By configuring the circuit as shown in Figure 1, it is possible to read and write multiple bits at the same time, and by separating the read bus and write bus, the read processing can be performed easily. and write processing can be controlled independently. However, display processing and printing processing require processing to change at least one bit of data in data consisting of a plurality of bits. In order to satisfy this requirement, the following control circuit is added.

In the circuit shown in FIG. 1, when writing, for example, data "1" to only one RAM cell 4 of the RAM cell group selected by the word line 5 (hereinafter referred to as bit set), the bit line 7 , 8 are precharged, the respective gate input signals 15, 13 of transistors 16, 14 go low and the data bus 1
Data 1 sent from RAM cell 8 is input and transmitted to bit lines 7 and 8 via RAM drive inverters 11 and 12 at the low level timing of write clock signal ₃ shown in FIG. “1” is written. However, since the memory circuit shown in FIG. 1 can simultaneously write data to all cells connected to the word line 5, data can be written to the cell 20 that does not need to be written. Lines 7' and 8' are precharged, and write transistors 9' and 10' are both turned on in response to write clock ₃ . In this state, the transistor 16' is off, so the data line 21 and the cell 20 are disconnected, but the write buffer circuit 1
The outputs of bit lines 1' and 12' are connected to bit lines 7' and 8'. Since the output of the write buffer circuit becomes unstable with the passage of time, there is a risk that the indefinite data of the buffer circuit may be destroyed in cells 20 that do not originally need to be written. Therefore, in order to avoid this, a transistor 17' is provided, and the data written in the cell 20 is read out once through the read transistor 6', and then written in the cell 20 again. has been done. As a result, write clock ₃
Even if the buffer circuits 11' and 12' are connected to the bit lines 7' and 8', the correct data held in the cell 20 is input to the buffer circuit via the transistor 17'. Therefore, the correct data is rewritten into cell 20,
Destruction of stored data can be prevented. Note that this rewrite operation must be performed on all cells whose bits have not changed, so that the data of all cells containing changed bits will be clocked.
It is read at ₂ . However, since the transistor (17 in the above example) of the cell whose bit is to be changed is off and the read data line 19 and write data line 18 are separated, there is no problem.

In this way, arbitrary bits can be changed using the function of simultaneously reading and writing a plurality of bits. However, conventional memory circuits have the disadvantage that transistors 17, 17' required for rewriting are required for each bit line pair. Furthermore, since a data read operation is required before rewriting, it is not suitable for increasing speed. Note that the above discussion applies to the case of writing data 0 to a RAM cell (hereinafter referred to as bit reset).
The same is true.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit having a RAM that does not require rewriting other bits when any bit is changed.

The present invention relates to an integrated circuit having a memory circuit in which a plurality of cells are connected to one word line and whose input (write) bus and output (read) bus are separated. Each cell is connected to a separate write data line via a separate bit line, write control transistor, and write control circuit, and is connected to a read data line independent of the write data line via a read control circuit. The data from the corresponding write data line is sent only to the cell whose contents are to be changed among the cells connected in parallel to the word line via the write control circuit, write control transistor, and bit line. The data to be changed is applied, and for cells whose contents are not changed, the buffer is left in a floating state after the write control circuit outputs the data, and the read/write control circuit and the bit line are electrically disconnected. .

Hereinafter, one implementation of the present invention will be described with reference to the drawings.

In FIG. 3, a circuit similar to that in FIG. 3 may be applied to one cell in particular among a plurality of cells connected to one word line 25.

One end of the cell 24 (which may be the same as the conventional one) connected to the word line 25 is connected to a bit line 26 and the other end to a bit line 27, and these bit lines 26 and 27 are turned on by the precharge signal ₁ . Power supply line 23 via transistors 37 and 38
Precharged from. Furthermore, the cell 24 is connected to a data write line 34 via a write control circuit, and to a data read line 39 via a read control circuit.

The write control circuit includes write transistors 28, 29 responsive to write clock ₃ and a write buffer circuit. The write buffer circuit has transistors 43, 44 and 45, 46 connected in series between the power supply line 23 and ground after output, and intermediate connection points 30, 31 of these transistor series circuits.
are connected to corresponding bit lines 26 and 27 via write transistors 28 and 29, respectively. After inputting the write buffer circuit, write data line 3
4, and the data input through the transistor 33 is NOR
It is applied to transistor 45 via gate 36 and inverter 42 as a true signal. On the other hand, it is inverted by the inverter 40 and NOR is used as a complementary signal.
It is applied to the transistor 43 via the gate 35 and the inverter 41. A control signal 32 for the transistor 33 is input to the transistors 44 and 46 and the NOR gates 35 and 36 respectively.

In addition, the read control circuit is connected to the read clock signal.
It includes a read transistor 47 and an inverter 48 which are turned on at ₂ , and is connected to the read data line 39. This read control circuit may be connected to either bit line 26 or 27. Furthermore, a sense up which amplifies and extracts the potential difference between the bit lines 26 and 27 may be used as a read control circuit. Since the present invention is particularly characterized by the write control circuit, a detailed explanation of the read control circuit will be omitted.

In FIG. 3, when writing data to all cells connected to the word line 25 at the same time, the bit line pairs for each cell are first precharged. At this time, the bit lines 26 and 27 are of course also precharged. Next, put data corresponding to each cell on the write data line corresponding to each cell. Then, transistors connected to each data line are turned on simultaneously. As a result, transistor 33 for cell 24 is turned on. Since the signal 32 that turns on this transistor 33 is at a low level,
NOR gates 36 and 35 receive data input through transistors and their inverted data, respectively, and drive transistors 45 and 43 through inverters 42 and 41, respectively. For example, in the case of write data "1", the output of the NOR gate 35 is "1", the output of the NOR gate 36 is "0",
The input of the transistor 43 becomes "1" and the input of the transistor 45 becomes "0". As a result, the transistor 43 is turned off and the transistor 45 is turned on, so that the charge precharged in the bit line 26 is discharged through the transistor 44, while the bit line 27 is supplied with charge from the power supply through the transistor 45. Logic "1" is held. When the write data is "0", only the opposite phenomenon occurs on the bit lines 26 and 27. In this way, data is written in parallel to all cells connected to word line 25, respectively.

When reading the written data from all cells simultaneously, a read clock ₂ is generated to turn on the read transistors. As a result, the contents of cell 24 are output via read transistor 47 to read data line 38. Regarding other cells,
Similarly, they are simultaneously output to their corresponding read data lines.

Now, in the memory circuit of FIG. 3, when data is to be changed to the illustrated cell 24 among the cells connected to the word line 25, an operation similar to the write operation described above is executed to change the data to be changed. It can be sent from line 34. On the other hand, when selecting the contents of another cell, the contents of the illustrated cell 24 must be saved. However, since write clock ₃ is commonly applied to all bit line pairs, transistors 28 and 29 are naturally turned on even for cell 24 whose contents are not changed. Therefore, in the past, a circuit was required to first read data from the cell 24, write data to the cell whose contents were to be changed, and simultaneously rewrite the read data to the cell 24.

On the other hand, in the present invention, by the signal 32 going high and turning off the transistor 33,
After outputting the signal 32, the buffer transistor 4
I try to turn off all 3 to 46. Therefore, for cell 24, even if the write clock
₃ , even if both transistors 28 and 29 are turned on, the intermediate connection points 30 and 3 of the output stage buffer
1 are both in a floating state. Therefore, unstable data does not flow into the cell 24 from the write control circuit. That is, according to FIG. 3, even without reading out the contents of the cell 24 at a glance,
The data within the cell 24 will not be destroyed. Therefore, even if write clock ₃ is applied to each cell at the same time, the contents of only any cell can be changed. Moreover, since a write control circuit having a floating state is used to electrically isolate the bit line and the write buffer, there is no need to provide a rewrite circuit for feedback as in the conventional case.

The above explanation was about P-channel type MOS transistors, but N-channel type MOS transistors
The same applies to transistors or complementary MOS transistors.

As described above, according to the present invention, among the RAM cells whose word line has been selected, the previously written contents can be written to the RAM cells whose bits have been set or whose bits have not been reset, without having to rewrite them.
It has the feature that it does not destroy the contents of RAM cells.

The present invention is particularly effective when selectively bit-setting or bit-resetting any RAM cell in a circuit in which the input bus to the RAM and the output bus from the RAM are separated.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional integrated circuit. Second
The figure is a timing diagram of each control clock for precharging, reading, and writing. FIG. 3 is a main part circuit diagram showing an embodiment of an integrated circuit according to the present invention. 23...Power line, 24...RAM cell, 25...
...Word line, 26, 27... Bit line, 28, 2
9... Write transistor, 30, 31... Output end of output buffer, 32... Control signal, 33... Transistor coupled to data bus,
34...Write data line, 35, 36...2
Input NOR gate, 37, 38... pre-charred transistor, 39... read data line, 4
0-42, 48...Inverter, 43-46...
Output buffer transistor, 47...Reading transistor.

Claims (1)

[Claims] 1. In a semiconductor integrated circuit having a memory circuit in which multiple cells are connected in parallel to a common word line and each cell has an independent bit line, the bit line corresponding to each cell has a write transistor and a write control circuit. The cell is connected to separate write data lines through the word line, and connected to separate read data lines via a read transistor and a read control circuit, and any cell among the cells connected to the word line When changing the contents of only
The write transistors of all cells connected to the selected word line are turned on, and the write control circuit, the write transistor, and the bit line are used to write only those cells whose contents are to be changed. 1. A semiconductor integrated circuit in which data to be changed is written, and cells whose contents are not changed are electrically disconnected from a bit line by setting the output end of a write control circuit in a floating state.