JPS6232319Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an improvement of a speech synthesis device using waveform encoding.

Conventionally, as a speech synthesis device using so-called waveform encoding, which converts this kind of analog signal into a digital signal, for example, PCM (pulse code modulation)
There were various methods. For example, in a PCM voice synthesis device, a calculator such as a counter outputs an address signal to a ROM based on the input of a clock pulse, and the ROM outputs a pre-stored digital voice signal corresponding to the address signal.
This signal is converted into a signal through a D/A converter, filter, amplifier, and speaker and output as audio. Therefore, in such a device, when a ROM having a small storage capacity is used, noise is likely to be included in the sound generated from the speaker, and the sound is not clear.

This invention was devised to eliminate the above-mentioned drawbacks, and by configuring an adder between the calculator and ROM (read-only memory), it generates sound with echo sound added from the speaker. It is an object of the present invention to provide a novel speech synthesis device that is designed to output speech that is clear and easy to hear.

EMBODIMENT OF THE INVENTION Hereinafter, one embodiment of the speech synthesis device according to the present invention will be described in detail based on the drawings.

Reference numeral 1 denotes a calculator, which is composed of, for example, a counter, and is provided with an input terminal connected to a clock signal terminal CL and a reset terminal R. Reference numeral 2 denotes an adder, which simultaneously inputs the clock pulse from the clock signal terminal CL and the output signal from the calculator 1, and outputs the addition result as an address signal. Process bits. 3 is a ROM (read only memory) into which address signals output from the calculator 1 and adder 2 are introduced. The ROM
3 stores digital audio signals in advance at each address corresponding to the address signal. 4 is D/
This is an A converter that converts the digital audio signal derived from the ROM 3 into an analog audio signal. 5 is a filter, and D/A converter 4
This is to remove high frequency components of the analog audio signal output from the . Reference numeral 6 denotes an amplifier, which amplifies the analog audio signal output from the filter 5 and causes the speaker 7 to generate audio.

Next, the action will be explained.

From the clock signal terminal CL to the reference period, e.g. 125
[μsec] is introduced into the input terminal of the calculator 1. On the other hand, a signal from the clock signal terminal CL is also introduced into the adder 2.

Therefore, as shown in FIG. 1, the calculator 1 inputs the upper 7 digit bit signals of the 13 bits of the output signal to the adder 2, and also inputs the lower 9 digit bit signals to the ROM 3 as part of the address signal. It has been introduced to
Further, the adder 2 combines two types of input signals by addition, and introduces the output signal into the ROM 3 as an upper four-digit address signal. Then,
Of the address signal consisting of 13 bits, ROM 3 introduces the signal obtained by adding the upper 4 digits from adder 2 using clock pulses, and the lower 9 digits from adder 2.
The digital audio signal at the address corresponding to the 13-bit address signal is read out and derived. Therefore, the D/A converter 4 converts the digital audio signal into an analog audio signal. next,
A filter 5 removes high frequency components from the analog audio signal and outputs it to an amplifier 6. Therefore, amplifier 6
amplifies the analog audio signal and generates audio from the speaker 7.

By the way, adder 2 receives the upper four digit input address signal (hereinafter referred to as "A") introduced from calculator 1.
and a clock pulse (hereinafter referred to as ``B'') to derive an output address signal (hereinafter referred to as ``S''). Thus, adder 2 outputs address signal S=A when clock pulse B=0.
+“0000”, and when the clock pulse B=1, the output address signal S=A+“1111” is output. Note that "0000" and "1111" are expressed in binary numbers. Therefore, ROM3 is the same as the calculator 1 above.
In other words, when the clock pulse B=0, the 13-bit output address signal (hereinafter referred to as ``S''') from the calculator 1 is introduced as a 13-bit address signal (hereinafter referred to as ``S'''). D"), and the clock pulse B=1
In this case, the following signal will be introduced.

S′=D+“1111000000000” This becomes as follows due to the carry function of calculator 1.

S′=D−“0001000000000” In the above equation, the binary number “0001000000000” is
Since it corresponds to the decimal number 512, S'=D-512.

Therefore, when clock pulse B=1, ROM3 introduces the address signal 512 samples before the current time and reads out the digital audio signal at the corresponding address, which is delayed by the delay time TD' shown by the following equation. This means that an address earlier than the current address has been specified.

TD′=125×512=64 [msec] Accordingly, echo sound is added to the sound generated from the speaker 7. This is shown in a signal output waveform diagram in FIG. 2, where the horizontal axis is time and the vertical axis is signal output. In this case, in Figure 2
TS is the current signal output time, TD is from the current time
This is the signal output time corresponding to the address 512 samples ago, and is 125 μsec for TS and TD.

As described above, according to the speech synthesis device according to the present invention, by configuring an adder connected between the calculator and the ROM, the speaker generates speech with echo sound added, so that the speech is clear and
Noise can be removed.

[Brief explanation of the drawing]

FIG. 1 is an electrical circuit diagram showing an embodiment of a speech synthesis device according to the present invention, and FIG. 2 is an output signal waveform diagram to which an echo is added. 1...Calculator, 2...Adder, 3...ROM,
4...D/A converter, 5...Filter, 6...
Amplifier, 7...speaker.

Claims (1)

[Scope of utility model registration request] A calculator connected to the clock signal terminal and outputting one of the output signals to the adder and the other to the ROM, and an adder inputting the clock signal and the output signal from the calculator to perform arithmetic processing and deriving the output signal. ,
a ROM that derives a digital audio signal based on a composite signal of each signal from the calculator and the adder;
An audio device characterized by comprising a D/A converter that converts a signal from a ROM into an analog audio signal, and a speaker that generates audio using the output signal from the D/A converter through a filter and an amplifier. Synthesizer.