JPS6231482A - Picture processor - Google Patents

Abstract

PURPOSE:To attain the conversion of pictures with high picture quality by giving the quick interpolation processing to the picture element data on the pictures obtained through a converting process based on the picture element data on an original picture in a production mode. CONSTITUTION:A result picture position register 45 advances synchronously with the picture signal pulse applied to an arithmetic circuit. Thus the result picture positions advance one by one. Here 'n' and 'M' are stored in a divisor register 42 and an increment register 43 respectively. Then the arithmetic circuit 41 divides the value obtained by adding 'M' to the values of both registers 42 and 43 and the picture element output 'm' set immediately before replacement by 'n'. Then a clock phi30 is delivered to advance the position of the original picture as long as the quotient is not equal to '0'. Thus an original picture position register 46 advances and therefore the original picture position also advances by one. Then the enlargement processing is through in the 1-dimensional direction and therefore the density of each picture element has the extremely smooth transition at sampling points after the end of said enlargement processing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device, and in particular to an image processing device that can enlarge or reduce an image.
The present invention relates to an image processing device that performs rotation.

[Prior Art] Conventionally, this type of device for performing image conversion processing such as enlarging/reducing or rotating images has been applied to double images, particularly black and white binary images. For this reason, for example, in Figure 1 (
In a case where the original image data indicated by the white circle in a) is enlarged by 1.5 times, the pixels shown in (2) are not at the exact position and value when enlarged, and for example, after enlargement ( 3)
, (4) are simply substituted with the pixel values shown in (2).

This will be explained in more detail using FIG. In FIG. 3, the horizontal axis represents the position in the main scanning direction, the white circles represent sampling points, and the vertical axis represents the value of multivalued data such as pixel density.

FIG. 3(b) shows the result of enlarging the original image data shown in FIG. 3(a) by 1.5 times.

[Problems to be Solved by the Invention] For this reason, when a conventional device is adapted to a processing device that requires high image quality such as multi-value (multi-gradation) color image processing, the outline of the image becomes noticeable. This has the disadvantage that the smoothness may be lost.

[Means for solving the problem J As a means for solving this problem, for example, the magnification (M
/n), calculates each time the output image position changes, and outputs a signal indicating the change in the original image position used for interpolation processing and a parameter that determines the interpolation ratio of the original image data. It includes a calculation means and an interpolation means that performs interpolation processing using the output of the @ calculation means.

[Operation] In this configuration, the pixel data of the converted image generated by the one-image conversion process is interpolated at high speed from the pixel data of the original image at the time of generation.

[Embodiment] Hereinafter, an embodiment of the present invention will be described in detail with reference to one drawing.

In this embodiment, for example, one
．． When the conversion is performed such that the centers of each pixel do not overlap, as in the case of 5x enlargement processing, in other words, when the sampling points of the original images of the two digital images are different. It consists in resampling the image-converted digital image from the original digital image so that when the conversion is performed, the two digital images are faithful to the original image.

There are several methods for this resampling, but in this example, the digital values of the two pixels are weighted based on the distance from the pixel center of the two original digital images including the pixel center of the image-converted digital image. This is the average.

"First Embodiment" First, FIG. 1 shows a block diagram of an embodiment according to the present invention that executes one-dimensional enlargement processing.

In the figure, 31 and 32 are latches, and 33 is (man)
Arithmetic circuit, 34 is (1-man) arithmetic circuit, 35.36
is a product circuit, and 37 is an adder circuit.

The operation when the original digital image shown in FIG. 4(a) is enlarged by 1.5 times using the above configuration will be described below.

In FIG. 4, the horizontal axis represents the position in the main scanning direction, the white circles represent sampling points, and the vertical axis represents the value of multivalued data such as pixel density.

The case of finding enlarged pixels of the sampling point 23 shown in FIG. 4(b) will be explained as an example. The pixel data shown at 21 in FIG. 4(a), which is the previous original pixel, is stored in the latch 31.
Pixel data shown at 22, which is the next original pixel, is latched in each latch 32.

That is, when the data of the sampling point 22 is supplied to the latch 32 and the data of the sampling point 22 is supplied to the latch 32, the data of the previous sampling point 21 is latched in the latch 32, and the data of the sampling point 22 is supplied to the arithmetic circuits 33 and 34. The value m(
When clock Φ30 comes when m is a value that can be said to be a fractional part of the sampling point of a pixel) is given.

Data of sampling point 22 in latch 32, latch 31
The data at the sampling point 21 is latched, and the value (m/n), (1-m/n) determined from the sampling interval n of the original digital image and the amount of deviation m is calculated by the arithmetic circuit 33 and (1-m/n). -m/n) is determined and held by the arithmetic circuit 34.

The image data at the sampling point 21 and the calculated value (1-m/n) from the (1-m/n) calculation circuit 34 are multiplied by the product circuit 36. Also, the data of sampling point 22 and (
m/n) calculation value (m/n) from the calculation circuit 33 is also multiplied by the product circuit 35, and the two products are added by the addition circuit 37, resulting in the value of the sampling point 23 to be obtained.
10, resulting in a digital image value.

Note that the pixel center shift m corresponding to the pixel before enlargement after execution of the enlargement process shown in FIG. 4 may be obtained as follows.

First, the enlargement magnification α (α=n/M) is input by the operator. Here, n, m, and M are each integer values, and α is a rational number. If the input format allows specification in units of 1% as a percentage (M=100), then n=α.

The m, n position updating unit shown in FIG. 5 calculates the corresponding m position from the values obtained in this way.

In FIG. 5, 41 is an arithmetic circuit, 42 is a divisor register, 43 is an increment register, 44 is an m latch, 45 is a result image position register that holds the image position as a result of image conversion processing, and 46 is a register that holds the original image position. This is the original image position register.

The arithmetic circuit 41 includes an addition circuit 41a and a division circuit 41b. The adder circuit 41a performs the calculation (M + m) every time an image progression pulse is input.

Furthermore, the division circuit 41b divides (M+
m)/n is calculated, and the quotient of the division circuit 41b indicates the step amount of the original image position, and the remainder indicates the amount of shift between the output image position and the original image position.

In the above configuration, when an image signal pulse is applied, the resultant image position register 45 advances in synchronization with the pulse;
The resulting image positions advance one by one. In this example, the divisor register 42 stores "n°", the increment register 43 stores "M", and the arithmetic circuit 41 stores the values of both registers and the pixel output "m" immediately before being updated. The value obtained by adding M' is divided by "n", and if the quotient is not "0", a clock Φ30 is outputted to advance the original image position.

When the clock Φ30 is output, the original image position register 46
is incremented, and the original image position also advances by one.

The above processing completes the one-dimensional enlargement processing. As a result, each pixel density of the sampling point after the enlargement process is
As shown in FIG. 4(b), there is a very smooth transition.

In the above explanation, M and n are free integers, but the operation is
If you are doing it in base numbers, there is a certain amount of .

If n is set to a power of 2, allowing for errors, the division will be reduced to a shift operation, and the cost of the device can be reduced.

On the other hand, similar control can be used when performing reduction processing as one image conversion processing. However, in this case, a large number of original image advancing pulses Φ30 may be generated with respect to the image signal pulse.

In the embodiments described above, the pulses that advance the position of the resulting image are identical to the original pulses.

Therefore, the pulses that advance the original image are not always output at the same intervals with respect to the original pulses. In the case of a device in which original images are always sent at a fixed rate, it is possible to insert a buffer so that processing can be performed regardless of the transfer rate of the original images. The reason for this configuration is that it is simple and requires only one interpolation process for each original pulse. However, it is also possible to perform processing by synchronizing the original pulse and the original image pulse, and in this case, contrary to the above case, there is a possibility that a plurality of resultant image pulses are compared during the enlargement process. In this case, the calculation may be performed in a time-sharing manner, or it is also possible to provide a plurality of calculation units and perform the calculation in parallel.

For example, if the magnification rate α is 5 and α≦6, then M added to the one-pixel center deviation m is set so that n 76 M =α, and high-speed processing is possible by operating six arithmetic units simultaneously.

In addition, (m/n) arithmetic circuit 33 in the above explanation
A look-up table (hereinafter referred to as LUT) may be provided in place of the product circuit 35, the (1-+w/n) arithmetic circuit 34, and the product circuit 36. By using an LUT, an output for an input can be obtained immediately, high-speed processing is possible, and there is no need to use an expensive product circuit, so the cost can be reduced.

[Second Example] The above is an example of one-dimensional expansion φ reduction.
The invention can be extended to two dimensions.

FIG. 6 shows an example of re-sampling points and sample points of the original image for two-dimensional enlargement/reduction in an embodiment in which the present invention is expanded (enlarged) in two dimensions.

The triangles in the figure indicate sample points of the original image, and the white circles indicate sample points of the resulting image.

In the example, four triangles 52, 53 surrounding the white circle 51 position
, 54. The values of the original image above 55 are X52 , X53 ,
Assuming that X54 and X55, the value Y5t of the resulting image at the point 51 to be determined is expressed by the following formula (1)% Formula% A block diagram of a pixel value calculation circuit when performing this two-dimensional image conversion process is shown in FIG.

Original image advance lock latches 601, 602.60
The pixel data captured in 3,604 was carried out using "ml" and "m2°' determined by two systems of m and n position update units similar to those described above. (m1/n
t) Arithmetic circuit 608 and (1-m 1 / nt )
Multiplication processing is performed with the calculation result of the calculation circuit 609. That is, the calculation is performed by the product circuits 612 to 615, the results are added by two adders 620 and 621, and the respective addition results are latched in the latch 605 and the latch 606. Furthermore, the values latched in the latch 605 and the latch 606 and the (m2/n2) arithmetic circuit 610 and (1-m2/n
2) The calculation results of the calculation circuit 611 are multiplied by the product circuits 616 and 61.
7 performs a multiplication operation, the result of the operation is added by an adder 622, and is latched into a lunch 607. This allows the value of equation (1) to be determined.

Further, it is also possible to configure the arithmetic circuits 608 to 611 (coefficient determination circuits) and the product circuits 612 to 617 with LUTs. FIG. 8 shows an example in which the above embodiment is configured using an LUT. In FIG.
The image data of two adjacent pixels during the first main scan latched at 01 and 702 are stored in the LUT 705 and 706 together with the decimal part 712 of the address obtained by the m and n position update units.
sent to. The data converted by each LUT is added to the data similarly calculated during the second main scan by an adder 709 and output.

Further, at this time, the contents of each LUT 705 to 708 may be the same, and in that case, only one LUT may be read and the address may be supplied in a time-division manner.

Further, although FIG. 8 shows an example in which interpolation is performed from four neighboring pixels, interpolation from nine pixels or 25 pixels is also possible. At this time, the contents of each LUT may not be the same.

As explained above, according to this embodiment, when performing image conversion processing such as enlarging or reducing multi-tone image data, the resulting digital image is resampled from the original digital image, and the distance from the pixel center is used as a weight. By taking the weighted average of the digital values of the two pixels, a high-quality converted image that is faithful to the original image can be obtained. By performing image interpolation using the decimal part (the amount of deviation between samplings) in this way, a high-quality converted image can be obtained.

[Effects of the Invention] As explained above, according to the present invention, a processed image that is faithful to the original image can be obtained even when image conversion processing is performed. Furthermore, the configuration is simple and the conversion process can be performed at high speed.

[Brief explanation of the drawing]

Figure 1 is a block diagram of an embodiment according to the present invention, Figure 2 is a diagram showing the positional relationship of sampling points when an original image is enlarged 1.5 times, and Figure 3 is the result of conventional enlargement processing. FIG. 4 is a diagram showing an example of the results of enlargement processing according to this embodiment. FIG. 5 is a block diagram of the m and n position update unit of this embodiment. FIG. 6 is a two-dimensional enlargement according to this embodiment. The figure which shows the example of a process. FIG. 7 is a block diagram of another embodiment according to the present invention, and FIG. 8 is a block diagram of still another embodiment according to the present invention. In the figure, 33, 34, 41, 608-611... arithmetic circuit, 35, 36, 612-617... product circuit, 37.
620-622.709...addition circuit, 31.32,
801-604.607, 701-704... Latch, 42... Divisor register, 43... Increment register,
44...m latch, 45...result image position register, 46...original image position register, 705-708...
・It is an LUT. Patent applicant Canon Co., Ltd. Figure 3 Figure 4ml -

Claims (1)

[Claims] (1) In an image processing device that enlarges, reduces, rotates, etc. an original image to obtain an output image, input numerical values M and n indicating the magnification (M/n) of the output image with respect to the original image in the direction of change of the output image position. and a calculation means that performs calculation every time the output image position changes and outputs a signal indicating a change in the original image position used for interpolation processing and a parameter that determines the interpolation ratio of the original image data, and the output of the calculation means is used. An image processing device comprising: an interpolation unit that performs interpolation processing.