JPS6231261A - Coding device for picture signal - Google Patents

Abstract

PURPOSE:To execute the coding of a picture signal at a high speed and without delay to the input of the picture signal to be coded by forecasting and storing the coding code beforehand and reading and generating this, in the coding of the picture signal of the long run length to need plural codes. CONSTITUTION:Each time the counting value of a run length counter 203 comes to be 63+64XN (positive integer of N=0, 1, 2...n), when the changing point is not detected, next, it is foreseen that the make-up value occurs, and the make-up code of 64(N+1) and the code length are temporarily stored (latched) to a latch B208. If the changing point is not detected when the value of the counter 203 comes to be 63+64n, it can be foreseen that the run length comes to be 64n or above while the run length is counted presently, and therefore, the code and the code length of a run length 64(n+1) are read, and stored temporarily to a latch A207. Simultaneously, the stored contents of the latch B208 are made invalid once, and the counting value of the counter 203 is returned to the initial value 1. Namely, the code, for which the occurrence can be foreseen, is returned to a temporary memory circuit (latches A and B).

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to an image signal encoding device used for facsimiles, image electronic files, and the like.

[Prior art]

Conventional image transmission devices such as facsimiles and recent image file devices using optical disks, magnetic disks, etc. reduce the amount of data by encoding image signals and increasing the speed and efficiency of transmission or a7Vt operation. is planning to change.

For example, in the field of facsimile, the Modified Huffman (MH) method is generally used for one-dimensional encoding, the Modified Read (MR) method is used for two-dimensional encoding, and the modified modified read (MMR) method is used for high-efficiency two-dimensional encoding. There is.

Regarding the mutual relationship between these MH, MR, and MMR methods, the MMR method includes methods that are very similar to the MH method, and the MMR method is a partially modified version of the MR method.

Furthermore, the images to be encoded and the rules of the encoding method are, in a nutshell, based on T4 and T6 recommended by the CCITT (Consultative Committee for International Telegraph and Telephone).

Furthermore, the above-mentioned encoding method was developed in March 1985 for the MMR method.
The MH method is announced as a high-efficiency two-dimensional encoding method in the recommended communication method for facsimile group 4 type equipment (Postal Service - Migami) on page 52 or less of the Official Gazette (Extra Issue No. 29) dated August 22nd. Both the original encoding method and the MH method were used as two-dimensional encoding methods in accordance with Ministry of Posts and Telecommunications Notification No. 1013 of 1982.
It is announced in the number.

In such image signal encoding, the number of consecutive pixels of the same color image signal, that is, the run length is expressed by a code. That is, a terminating code representing a run length from 1 to 63 and 64,128°192, -----. 64 X
The run length is represented by a make-up code representing the run length of M, ----, 2560. Therefore, in order to represent a relatively long run length, a plurality of codes are required, and generating them at one time places a burden on the encoding circuit and requires time to generate them.

Therefore, for example, it is difficult to perform a code transitive operation without delay in inputting a serial image signal obtained by photoelectrically reading an original image.

[11] The present invention has been made in view of the above points, and an object of the present invention is to enable encoding of image signals to be performed at high speed and without delay in inputting the image signals to be encoded. and a means for counting the number of pixels between changing points of an image signal inputted serially, and a count value of the counting means is 64n+63 (n=o,
means for storing a first encoded code representing 64 (n+1) when the pixel is not a change point when the pixel becomes 1.2--);

and means for generating a second encoded code representing a count value of less than 64 of the counting means, and reads out the first encoded code stored in the storage means at the time when a change point pixel is reached. The present invention also provides an image signal encoding device that causes the generating means to generate a second encoded code.

Next, reference numeral 101 denotes a coding line (encoding) An example of the configuration of an encoding circuit to which the present invention is applied is shown in the circuit block diagrams of FIGS.
This will be explained using FIG. 2, FIGS. 3 to 5, etc.

The signal indicated by 121 in FIG. 1 is an image signal to be encoded supplied from an external device such as an image scanner, an image file, or a computer, and is O"° or "'l" (for example, "0" = white, It is given as serial data of a binary signal of “1°°=black pixel). Further, the signal indicated by 134 is a clock supplied from an external device in synchronization with the input of the image signal 121, and the signal indicated by 136, which is 1 clock per pixel, is a synchronization signal and is synchronized with the input of the image signal 121. 1
Several kinds of synchronization signals indicating 21 horizontal sections, vertical sections, etc. are shown.

That is, in this embodiment, the image signal 121 to be encoded is provided as a scanning image signal that is a serial image signal for each main scan, similar to a signal provided to a laser printer or the like.

This is a circuit that forcibly creates a change point so that the next pixel (=virtual pixel) after the final pixel of the real image on the target image (one tree in the main scanning direction) is always the change point. It is called "change point generation circuit A". However, the above-mentioned "virtual change point generation circuit A" has a structure that does not give any change to the real image on the coding line.

102 is a line buffer memory A, and 103 is a line buffer memory B, each of which is a RAM (Random Access Memory) capable of independently writing or reading operations, and each of which has a capacity for one coding line. It has a capacity (number of main scanning pixels) that can store a binary image.

Further, the line φ buffer memory AlO2 and the line buffer memory B103 are controlled so that when one of them is executing a write operation, the other one is executing a read operation. That is, these two line buffer memories constitute a set of double line buffer memories.

A memory address counter 111 is a counter that counts a clock 134 corresponding to the number of pixels of a coding line. The count value of the counter 111 is commonly given as a memory address signal 135 to both the line buffer memory AlO2 and the line stand buffer memory B102. In addition, the memory address counter 111 returns to the initial value for each coding line and returns the counting operation to green. Therefore, the binary image of each line written to the line buffer memory is different from that of the newly input line. is read out for each pixel in correspondence with the pixel position of the image signal 121.

104 is a selector, which is a line stand buffer memory A.
Of lO2 or line buffer memory B103,
This circuit operates selectively in response to a select signal 901 in order to obtain read data from whichever one is executing the read operation.

The data selectively obtained by this selector 104 is given to the next stage as a reference line 125, that is, as reference data (image) of the coding line.

105 is a circuit that forcibly creates a change point so that the last pixel of the real image on the reference line and the next pixel (virtual pixel) always become the change point, and is called "virtual change point generation circuit B".
”.

However, the virtual change point generating circuit B105 has a structure that does not give any change to the real image on the reference line.

10B is a circuit for detecting a pixel serving as a changing point on the real image and virtual pixel on the reference line, and is referred to as a "changing point detection circuit A."

Further, 107 is a circuit for detecting changing points on the real image and virtual pixels on the coding line, ``changing point detection circuit B''.
It is called.

108 is A register, 109 is B register, 110 is C
Each register is a 4-bit shift number register. Also, the signals indicated by 126 are signals representing the real image and virtual pixels on the reference line, and the signals indicated by 127 are the signals representing the real image and virtual pixels on the reference line. It is a change point signal on an image and a virtual pixel. Signals indicated at 128 are change point signals on the real image and virtual pixels on the coding line.

A timing circuit 112 receives a clock 134 and a synchronization signal 136, and based on these, forms various timing signals 137 for timing the operation of each circuit block.

The operation of the circuit block of FIG. 1 described above will be explained using an example in which an actual image (an image to be encoded) as shown in FIG. 4 is given and is encoded by the MMR method.

First, in the image shown in FIG. 4, one line has 32 pixels (number of main scanning pixels = 3232 pixels) to simplify the explanation.
This is an extremely simple image consisting of pixels and one page consisting of two lines in total (number of sub-scanning lines=2).

To actually encode the first line shown at 402 in FIG. 4, as shown in FIG. 5, the virtual line shown at 401 in FIG. do.

When the second line 403 in FIG. 4 is encoded, the first line 402 in FIG. 4 is used as a reference line and the second line 403 is used as a coding line, as shown in FIG. 6.

Below, it is assumed that one page consists of main scanning of 3 or more lines,
Even if the 3rd line, the 4th line, -11111, etc. continue, encoding will continue regardless of the number of sub-scanning lines if the relationship between the reference line and the coding line is sequentially lowered as described above. can.

FIG. 3 is a timing chart when the image illustrated in FIG. 4 is applied to the circuit block illustrated in FIG. 1.

In FIG. 3, a vertical synchronizing signal 136-1 indicates an image section in the sub-scanning direction, that is, an input period of one page of images. 136-2 is a horizontal synchronizing signal, which is an image section in the main scanning direction;
That is, it shows the input period of the image of the ■ line. 134 is an image clock, 121 is a signal waveform representation of the image to be encoded illustrated in FIG. 4, and black pixel = "" 1 "
= "H", white pixel = "0" = "I,". That is, in the image shown in the third figure, the section T
1 image is the first line 402 shown in the fourth figure to be encoded.
, and the image of section T2 is the real image of the second line 403 shown in FIG. 4 to be encoded.

Furthermore, in an image printed on an actual paper, the virtual line 401 shown in the fourth figure corresponds to the so-called margin in the F direction of the paper, or the area outside the paper, and in the MMR method, , is defined as a blank line (all pixels in one line are white pixels). Therefore, the virtual line 401 shown in the fourth figure does not appear on the image signal 121 shown in the third figure.

FIG. 5 is a timing chart showing the encoding operation of the first line 402, and shows the relationship between the virtual line 401, which is a reference line, and the first line 402, which is coding.

First, when the image of the first line 402 shown in FIG. 5 is given to the virtual change point generation circuit A101, a virtual change point (virtual pixel) 302 is added as shown at 122 (coding φ line) in FIG. It becomes an image. That is, in the interval T1, the actual image remains unchanged, but as shown in the figure, the last pixel 301 of the first line and the next pixel 302 have contradictory colors (white→black). Also, virtual change point (virtual pixel) 302
The virtual several pixels following 302 are kept as pixels of the same color as the virtual change point (virtual pixel) 302 so that they do not become change points for reasons described later.

Now, the coding contest line signal 122 in FIG.
As shown in FIG.
The data is given to the buffer memory AlO2 and the line buffer memory B103 as write data.

On the other hand, the address counter 111 counts the image clock 134 only in the interval T1 in FIG. 3, and outputs a count value as shown at 135 in FIG. Memory AlO
2 and line φ/header memory B103.

Furthermore, although not shown in the figure, assuming that the line buffer memory AlO2 is controlled to write mode and the line buffer memory B103 is controlled to read mode.
The data on the coding command line 122 is sequentially written to the address indicated by the memory address 135 in the line-buffer memory AlO2. Also, at this time, the line buffer memory B 103 is in the read mode as described above, so if all "0" is written in the initial state, the line buffer memory B 103 will read 0 from the address specified by the memory address 135.
124 in FIG. Read signal B shown as
This is selected by the selector 104 and becomes the data of the reference line 125.

Reference numeral 125 in FIG. 3 indicates the data signal waveform of the reference line, which is 110 IT in the interval Tl. This means that the virtual line 40 as shown in FIG.
1 on the circuit as an ``all-white'' reference line.

The coding line 122 is also provided to the change point detection circuit B107 as described above. The detection circuit B107 detects a change point (pixel) in the applied data input, and sets the change point pixel to "1".

All pixels that are not changing points are output as “°0′
° Output. 128 in FIG. 1 is the output.

Virtual change point generation circuit B105 and change point detection circuit A10
6, as its name suggests, is the coding line 1 mentioned above.
Circuits 101 and 107 with the same name that operate on 22
The following operations are performed on the reference line 125 read from the line buffer memory.

Eventually, the signal on the reference line 125 is converted by the virtual change point generating circuit B105 into a signal in which a virtual pixel of a color different from that of the final pixel is added to the PX of the final pixel, as shown at 126 in FIG.

The signal 128 generated from the change point detection circuit B107 is sequentially shifted into the A register 108 by the clock 134. Symbols A1 to A4 of the A register 108 each indicate a parallel 4-bit output of the register, which is always output. The output signal waveforms of the A register 108 are shown at 129-1 to 129-4 in FIG.

Therefore, the pixel of interest on the coding line is A register 1.
If it is shifted to output A4 of 08, output 1 indicates whether there is a change point in the data for 3 pixels following that pixel of interest.
This can be determined based on 29.

Similarly, 130-1 to 130-4 in Figure 3 and 1 in Figure 3
31-1 to 131-4 show the output signal waveforms of the B register 109 and the C register 110. That is, B register 10
The change point signal and color signal of the pixel of the reference line corresponding to each pixel position stored in the A register 108 are stored in the 9 and C registers 110. Therefore, if the output A4 of the A register 108 is the pixel of interest on the coding line, the B register 109 and the C register 1
10, it is possible to determine whether there is a change point within the three pixels following the pixel position of interest on the reference line and its color.

To encode the second line, the second line 403 in FIG.
When input as the image signal 121, the line buffer memory Al02 is in the write mode, and the line buffer memory B103 is in the read mode.

That is, the first line 4 written in the line buffer memory B103 during the coding operation of the first line 402
02 becomes the reference line, and the second input line
Line 403 is the coding. Then, the same operation as in the first line is executed.

Each signal waveform in the 403rd m2 line is shown in section T2 in FIG. The data on line 402 is read out.

The above is the specific operation of the circuit block shown in the first diagram.

Next, the circuit block shown in the second diagram will be explained.

201 is a symbol detection circuit which, as shown in the first figure, receives signals 129,
130, 131, and detects necessary symbols aO+a1+a2, bl, b2, etc. in the MMR encoding method. The definitions of these symbols are as follows.

aQ=pixel on the coding line that is the starting point for encoding.

al=first change point (pixel) on the coding line to the right of aQ.

a2=first change point (pixel) on the coding line to the right of a1.

b1 = A changing point (pixel) on the reference line to the right of a□, the opposite color to aQ, and the first changing point.

b2 = first change point (pixel) on the reference line to the right of b1.

However, the right here is the same as the relationship between the left and right of each pixel shown in 4r:g4, for example.

Next, 202 is a B register, which inputs the change point signal b1 shown at 222 in FIG.
The 3-bit shift signal is sequentially input into the shift tube by
It is a register.

Therefore, the change point signal b detected by the symbol detection circuit 201
1 is held for three consecutive clock periods, and the position of the change point signal b1 relative to the pixel of interest can be determined.

203 is a run length counter, which usually corresponds to pixel a
It is a binary counter that counts the number of pixels (run length) from Q to pixel a1 or from pixel a1 to pixel a2, and has a 12-bit output, and the maximum is 2 in decimal notation.
This counter can count up to 559.

The signal shown at 228 in FIG. 2 is the run length e counter 2.
These are the lower 6 bits of the count value output of 03. or,
The signal shown at 227 in FIG.
These are the upper 6 bits of the count value output of 03.

204 is a ROM table A, which mainly contains codes for pass mode (P mode) and vertical mode (V mode).
This is a ROM (read only memory) that stores the codes and the number of bits (code length) of each code ', and can output the codes and code lengths in parallel according to the input input.

Further, 205 is a ROM table B, which is a ROM that mainly stores make-up codes and code lengths for the horizontal mode (H mode), and selects the code and code length to be output using the signal 227 as an address. Output.

Reference numeral 206 denotes a ROM table C, which is a ROM that mainly stores H mode termination codes and code lengths, and selects and outputs the code and code length to be output using the signal 228 as an address.

207 and 208 are latch circuits that temporarily store the make-up code and code length output from each of the ROMs. Further, 209 is a latch circuit that temporarily stores the terminating code and code length output from the ROM.

210 is a buffer memory for sequentially receiving the code and code length in the latch circuit C209 and temporarily storing it.

Here, I will explain the encoding rules of the MMR method a little more. In this encoding method, the symbols &
Q, al, a2 are on the coding line, and
Similarly, the symbols b1 and b2 are on the reference number. And each of these symbols a0, L1+a2 group and bl.

Based on the relative position (distance) of the group b2, it is specified that the encoding mode is uniquely selected from the following three modes and encoding is performed.

(1) Pass mode (P mode) When b2 is to the left of al (there is only one generation code) (
2) Vertical mode (V mode) When lalb11≦3 (A total of 7 types of generation codes differ depending on the distance) (3) Horizontal mode (H mode) At times other than (1) and (2) above (run- (according to length code table) Format: H+M(a□a1)+M(ala2) where,
H is a code indicating H mode, M(aoaz) is a white or black 1aoa11 run length code, M(a1a2
) is a black or white 1ala21 run-length code.

However, if two or more of the above (1), (2), and (3) are satisfied at the same time, (1) P mode 14> (2) V%-do> (3) H- E
--Priority is given in order of code.

The code determination circuit 21 controls this priority output operation.
2, and the code determination circuit 212 selects the latch.

Next, the operation of encoding the first line image 402 in FIG. 4 will be described.

First, in this embodiment, at the time 320 in FIG.
Let be the encoding start time.

That is, time 1 (,) is the time when the first pixel of the reference φ line and the coding line appears at the C4 output of the C register 110 or the A4 output of the A register 108 in FIG. 2, respectively.

That is, at time 1 (, the outputs of the C register 110, B register 109, and A register 108 are reference
The states of the first pixel of the line and coding line and the three pixels following the first pixel are output in parallel. Also, aO
is the initial value ° as shown in 221 AO (ao) in Figure 3.
“It is set to 0pa (white pixel = virtual).

The run range counter 203 starts from the initial value O to time 1 (
, the image clock 134 starts counting.

The count value output of the counter 203 at each time is
It is shown at 322 in the figure.

At time 1o, signal 129-4 in FIG. 3 is not set to 1, that is, A shift φ register 1 in FIG.
There is no change point in the A4 output of 08, and similarly there is no change point in the B4 output of the B shift register 109.Therefore, there is no cause for generating a code, so just increment the count value of the run length counter by 1. Then, the process advances to the next time t1, but the state at time t1 is the same as that at time to.

Next, when proceeding to time t2, the signal 129-4 in FIG.
′′ is standing. This means that A register 1 in FIG.
The A4 output of 08 becomes 1, indicating that a change point exists at that position on the coding line. Since this change point is the first change point to the right of the current starting point aQ (corresponding to a later time), the symbol detection circuit 201 in FIG. 2 determines that it is the symbol a1.

Note that the detection state of this symbol a1 is stored as Fal.

At this time t2, 130-1 to 130- in FIG.
4, there is no °l" in any of them. This means that there is no change point b1 within 3 times from time t2. Also, when the symbol detection circuit 201 detects bl, bl is shifted into the B shift register 202 so that it does not disappear for three times.

The symbol detection circuit 201 also has a circuit for storing that bl has already been detected.

As a result, in the single case, there is no change point pixel b1 within 3 pixels to the left and right of change point pixel &1, and from the starting point aO
Until then, it can be determined that there is no bl (therefore, there is no b2 either). Therefore, although al was detected at time t2, P
It is determined that the conditions of mode (b2 must already be detected) and mode (2) (condition: lalbll<3) are not satisfied, and therefore the mode becomes H mode.

At this time, the value of the run length counter 203 is
As shown in 22, &Q indicates the number of pixels of al, and “2
It's Pa. Also, the run length color is initially set to “0”.
= Remains white. Therefore, the run length counter 203
The run length value and color etc. are output by the output 228 etc. of RO.
The code is given to the M table C206, and the corresponding code and code length are outputted to the ROM206. In this case, a code of "white run 2" is output. That is, M(aoax)=
White is 2.

At this time, it is determined that it is the first code of H mode, and the code "001" indicating H mode is changed to the code "001" of white run 2.
The code length is controlled to be output at the same time as 11'', that is, at the l block.Furthermore, the code length is also output at the same time as a binary number or the like.

Next, the run length counter 203 is set to an initial value of 1 (O
(Note that this is not the case.) and moves on to counting from pixel a1 to pixel a2. However, pixel a1, that is, time t2
Then, only preparations for setting the initial value are made, and the initial value is set in the counter and the count is started from the next time t3. Furthermore, from this time t3, the color of AO is also inverted.

(Time t2 = “0” → Time t3 = “1”) From then on, when time 1n advances, eventually at time t4, A register 1
A turning point of 1° appears on the A4 output of 08. Since the symbol detecting circuit 201 remembers that the changing point a1 has already passed and has been detected (Fa1=1), the symbol detecting circuit 201 determines that the changing point is a2. Note that this detection state of a2 is stored as Fa2.

Now, at time t4, the value of the run length counter 203 is 2.
Therefore, AO=“l”=black. Also, it is already time t2
Since it is confirmed that it is in H mode, a2
is detected, the state of the reference line, that is, 131-1 to 131-4 in FIG. 3 and 130- in FIG.
References to 1 to 130-4 are unnecessary, and are not in this case.

Even if bl, b2, etc. are present on the reference line, they are controlled to be ignored.

As a result of the above, the M (a 1 . a 2) = black "2" code and code length are output in the same way as in the case of M (ao, al). At this time, unlike the case of M(a□, al), the code °'001'' indicating the H mode is not added.

Next, after time t4, ie, at time t5, the run-length counter 203 is set to the initial value 1. or,
AO (=ao) is inverted.

Then, the change point a2 at time t4 is the starting point aQ of the next mode.
considered to be.

Through the above operations, the code generated by encoding the first line 402 becomes as shown at 501 in FIG.

Also, at time t30 in FIG. 3, the run-length counter value is 9, and at this time, the symbol fx (=at) is detected, but there is a change point 6'l after two pixels on the reference line. At time t30, the output 130-2 of the B register 109 and the output 131-2 of the C register 110 in FIG.
It is judged from etc. Therefore, the condition of 1alb11!3 is satisfied and it is not P mode (b2 is required), so it is determined to be V mode by definition and VL (2) code (aX is b
2 pixels to the left of l) is output.

At this time, a code with a run length of φ white 9 in H mode could have occurred, but according to the definition of priority between each mode mentioned earlier, mode ■ became the valid code, and the code in H mode becomes invalid. Due to the occurrence of the Zara V mode code, the run length counter 203
The count value up to time t30 is cleared and controlled to be newly preset to 1. Further, after the code of the ■ mode is generated, the color of the starting point aQ symbol is inverted. (However, the ■ mode code is generated at the same time as the change point detection of the a1 symbol (time t30).)Also, although it has not been explained so far, if the symbol b1 is detected before the symbol a1 for.

The detection signal of symbol b1 is shifted into the register as an input signal of the B register 202, and is input for three times thereafter.
The output of the B register 202 shifts in the order of B5-B6→B7, and then disappears. Further, when the symbol b1 has already passed through the B4 output of the B register 109 and no code is generated yet, the actual value is stored as shown by the output Fbl of the storage detection circuit 201.

Next, specific circuits of each functional block of the circuit block shown in the first diagram will be explained.

The virtual change point generation circuit Al0I and the virtual change point generation circuit B105 in FIG.
2 is a flip-flop, 703 is an AND gate, 704
is an OR gate, and 705 is an inversion circuit (inverter).

The operation of the circuit shown in FIG. 7 is shown in the timing chart of FIG. 8. That is, the numbers of the parts in FIGS. 7 and 8 correspond to the numbers in FIGS. 1 and 3. However, Figures 7 and 8
The signal indicated by 701 in the figure is, for example, the position (timing) of the last pixel of the l line obtained by decoding the count value of the memory address counter 111 shown in the first figure.
This is a signal indicating. That is, at the time when the signal 701 is generated, the flip-flop 702 is set to the same color as the last pixel of the coding line in synchronization with the clock 134, and after that time, that is, after the horizontal synchronization signal 136-2 is deenergized, the flip-flop 702 is The Q output of 122 is set as the 122 signal, and before that time, that is, while the horizontal synchronization signal 136-2 is being output, the image 121
is configured to output the signal as a 122 signal.

The selector 104 in FIG. 1 is realized by the circuit shown in FIG. 9, in which 902 is an AND gate, 903 is an OR gate, and 904 is an inverter. 123.1 in Figure 9
24 is the output 12 of the line buffer memories A and B in FIG.
3°124, but the signal 901 in FIG.
This is a select signal whose level is inverted for each line, and is generated by the horizontal synchronizing signal 136-2 in FIG. The output to signal 125 is switched by the select signal 901.

Change point detection circuit A106 and change point detection circuit B in Fig. 1
Reference numeral 107 designates a circuit of the same type, and FIG. 10 shows a typical configuration of the change point detection circuit B107. In the figure, 1002 is a flip-flop, 1003 is an exclusive OR gate, and 100
4 is a -inverter.

That is, as shown in the timing chart of FIG.
By taking R), it is detected that the colors of adjacent pixels are different, and this is used as a change point signal.

Next, specific circuits of various functional blocks in the circuit block of FIG. 2 will be explained.

FIG. 11 is a circuit for detecting the symbol a1 or a2 on the aforementioned coding line and the FAL signal indicating that the aforementioned al has been detected, and is the symbol detection circuit 2 shown in the second diagram.
It is within 01. In the figure, 1102 is a flip-flop, 1
104 is an AND gate, and 1105 is an IN gate.

Now, the numbers of each part in FIG. 11 correspond to the numbers in FIG. 1, etc. The signal shown at 1101 in FIG. 11 returns the flip-flop 1102 to its initial state (i.e., Q output =
This is a control signal that prohibits the Q output from being set to "°0") or to Q output = "1", and is normally at the level of "°l'°".

The same applies to the RESET signal 1103. Here, when the change point A4 (129-4 signal) arrives first, A4
= “1”. In this case, flip-flop 1102
Q output = “°1°” and control signal 1101 = ”
1″, so a 1 = ” 1°゛ is output,
Symbol a1 is detected. This a1 detection signal sets the flip-flop 1102 so that Q output = "1°", and it is remembered that al has already been detected (that is, Q output =
F a 1 = “1”), then in this state A4 =
When it becomes "1", a 2 = "1" and symbol a2 is detected.

Next, the circuit for detecting the symbol bl etc. is shown in FIG. 12, in which 1201 is an exclusive OR gate;
03 is a flip-flop, 1204 is an AND gate, 1
205 is an inverter. The number of each part is numbered 11th.
This is the same as the case shown in the figure. However, aQ can be bl.
Because of the condition that the color is opposite to that of the signal, the circuit uses the signal obtained by exclusive ORing the change in the reference line and the aQ multiplied signal using the exclusive OR gate 1201. The circuit shown in FIG. 12 is included in the symbol detection circuit 201 shown in FIG.

The specific configuration of the run-length counter 203 in FIG. 2 is shown in FIG. (decimal) to 25
60-1 (2559 in to base), and the counter 203 has a preset function, a clear function, etc.
It can be constructed from IC., model name 74F163, etc.

Furthermore, the count value output of the counter 203 is 1O base 2
559 and generates the MKI signal.
301 and the value obtained by decoding the lower 6 bits of the output is 1
The circuit 1302 detects that the decimal number is "63°" and generates an MK2 signal.

Furthermore, the structure is such that the value to be set by the preset function can be selectively preset to 0° (decimal) or 1° (decimal).

The operation of the run-length counter 203 will be explained. First, for each coding line, the initial value is preset (or cleared) to 11011 at a position outside the left edge of the image.In the 0-order image area, the count is sequentially advanced pixel by pixel. Counter 20
3 is returned to "I II" by the preset function.

That is, (1) when change point a1 or a2 is detected, (2) when the count value reaches 2559, (3) when P-mode fist code or V-mode good code occurs, however, the encoding method According to the rule, if the change point al is set to A2 on a virtual pixel outside the rightmost end of the coding line, the counter value is returned to "Ooo" when al is detected.

Next, the configuration of the ROM table A204 in FIG. 2 will be described. The ROM table A204 is used to generate a total of eight types of codes, P mode and V mode, and the code lengths. As is clear from the configuration principle of this embodiment and the above explanation, the configuration described here is based on the relative relationship between the changing point positions of the coding red line and the reference line, and especially when the changing point b2 on the reference line is in the B register 1.
09, or when the change point a1 on the coding line appears as the A4 output of the A register 108, the state of the symbol detection circuit 201, the A register 108, the B register 109, The configuration is such that the status of each output of the C register 110 and the B register 220 can be determined simultaneously and in parallel. Therefore, the combinations of the word output states are naturally finite, and at the time of judgment, they can be treated as static states. Therefore, since the P mode or V mode code and code length to be output for each combination can be determined, it can be configured as the ROM table.

Since the specific contents of the ROM table are too redundant here, as an example, FIG. 14 illustrates a case where a P mode code and code length are generated by a logic circuit equivalent to a ROM. In the figure, 1409 is an inverter, 1410 is a timing circuit, 1411 is a Nant gate, and 1412 is a NOR gate. That is, 140 in FIG.
The signal indicated by 1 is a signal indicating that the symbol detection circuit 201 in FIG. 2 has detected the change point b2 on the reference line.

That is, this means that the B4 output of the B register 109 in FIG. 1 has a changing point as b2. Similarly, the a1 signal indicated by 1402 in FIG. 14 is the a1 change point as the A4 output of the A register 108 in FIG. Furthermore, the Fa1 signal shown at 1403 in Fig. 14 has reached the second level by the current time.
This is a signal indicating that the graphic symbol detection circuit 201 has already detected the change point as al.

The logic circuit shown in FIG. 14 means that at the time when b2 is detected, the P mode is determined because the al or Fal signal is not "true". That is, it means that there is no a1 change point after the starting point aQ until the time when b2 is detected. That is, on the image, there is no a1 change point between the starting point aQ and directly below the b2 change point.

Therefore, by definition, it is in P mode. 140 in Figure 14
4 is a P mode detection signal, 1405 is a specific code of P mode, and 1406 is a binary number representing the code length of the P mode code. Further, 1407 is a signal indicating that a P mode code has been generated. The above is the determination method for P mode, but the same method can also be applied to ■mode. The ROM table A204 is configured by this method.

After all, the code and code length of the P mode or V mode are determined by applying the status signals of each register etc. as input data to the ROM table A204 in FIG. 2 based on the above method at the time when the b2 or a1 symbol is detected. In some cases, it is generated instantaneously at a time of 1 clock.

ROM table B2O5 and ROM table C in Figure 2
Since the ROM table 206 has a similar structure, the ROM table 0206 will be explained with reference to FIGS. 15 and 16 as a representative.

First, 206 is a ROM with at least 11 bits of address input and 21 bits of parallel output;
The human power corresponds to the 228 signal in FIG. That is, they are the lower 6 bits of the run length counter 203 in FIG. Further, 1502 manual input in FIG. 15 is a signal specifying the color of the run length, and in this example, white=0 and black=1.

Also, 1503 human power is a code indicating H mode (=OO1)
This is a signal that specifies whether to add or not. In this example, required = 1
, unnecessary=O. That is, if 1503 manpower is 1, H
The code (001) added to the first run length code of the mode code is output in one clock.

A chip enable signal 1504 controls whether the output of the ROM 206 is enabled or disabled. 150
7 manpower is EOL<1507 manpower is EOL+ 1.150
8 are address inputs that control the reading of each of EOL+O, and by inputting pulses to these inputs, the delimiter code of the corresponding line is read. or,
1505 is the code output of the address specified by the input and is 1
Similarly, 506 is the code length of the code.

FIG. 16 is a diagram showing the correspondence between the addresses AO to A10 in FIG. 15 and the stored contents (data).

The code determination circuit 212 of FIG. 2 is specifically explained with reference to FIG. 17. In FIG. 17, 1706 is an AND gate;
is an inverter.

As can be seen from the principle of the code generation method in this example,
ROM table 204 and 205 or 206 shown in the second diagram
etc., P mode.

In the stage before each mode and H mode code is finally determined as the code to be generated, two or more codes may be output from the ROM table at the same time. However, the priority of two or more codes is defined as described above.

FIG. 17 shows a circuit for determining the code to be uniquely generated according to the definition.

In other words, if the codes of P mode, ■ mode, and H mode can occur simultaneously, the need of the mode that acquired the debt lien will eventually occur depending on the order of P mode>■ mode>H mode as described above. Should be determined as the code.

Codes for other modes are invalid and cannot be used as generation codes.

Note that the signal 1708 causes the present encoding circuit to have an MI (modulus, i.e., −
This is a mode signal for selecting whether to use for dimensional encoding or for MMR or MR two-dimensional encoding, and is L level when executing -dimensional encoding; on the other hand, when executing two-dimensional encoding. In this case, it becomes H level.

Therefore, when performing -dimensional encoding.

The generation of P mode codes and V mode codes is prevented,
Only H mode codes, ie codes representing run length, are always valid.

Next, the roles of the latch A207, latch B2O3, etc. in FIG. 2 will be described. Latch A207 and latch B2O
Reference numeral 3 denotes a circuit for temporarily storing the H mode make-up code and code length that are generated during coding until it is determined whether the H mode is valid or invalid. If it is determined that the H mode is valid, the contents of the latch are transferred to the next stage circuit.

Taking f@ of latches A207 and B2O3 in FIG. 2 as an example, a case where the run length in which the make-up code is generated is long will be explained using, for example, run length 2972. At this time, according to the encoding regulations, the code is divided into a total of three run-length codes, two make-up codes and one terminating code, and output as follows.

That is, Makeup code l = Run length 2560 code (common for white and black) Makeup code 2 = Run length 384 code (white or black) Terminating code = Run length 28 code (white or black) In this way, 2560 + 384 + 28 When one run length is expressed by multiple codes such as =2972, first, the count value of the ten length counter 203 in FIG. 2 is 63+64XN (N=0.1.2...
・A positive integer), at that point A4 of the A register
If the output is not at the a1 change point, it is predicted that a make-up value will occur next, and the value of the upper 6 bits of the counter 203 (corresponding to N) indicates a make-up value of RO the make-up code and code length of
The contents of the latch B2O3 are outputted from the M table B2O5 and temporarily stored (latched) in the latch B2O3.Then, each time the previous value count value advances by 64 (that is, each time N advances by 1 in the above-mentioned formula 63+64XN), the contents of the latch B2O3 are , will be updated.

Then, the value of the run length counter 203 is 2559.
(In other words, if the change point a1 is not detected at the time when N = 39 in the formula 63 + 64 Read the code and code length of 2560 and latch A2.
Temporarily stored in 07. At the same time, the stored contents of latch B2O3 are temporarily invalidated. Further, the count value of the run length counter 203 is returned to the initial value l. Subsequently, as the count progresses, the storage of the make-up code, etc. to the latch B2O3 is resumed in the same manner for each of the above-mentioned formulas 63+64XN.

When the change point a1 is detected, the competitive relationship with other P mode or V mode is determined, and when the H mode is determined, the run length counter 2 at the time of the change point a1 is determined.
The termination code and code length of the run length indicated by the value of the lower six bits of 03 (0 to maximum 63) are temporarily stored in latch C209. Furthermore, as already described above, the contents of latch A207 and latch B2O3 also become valid.

However, if V mode etc. occurs at the time of change point a1, H mode itself will not occur, and naturally latch A20
7 and the contents of latch B20g are invalidated, and the contents of latch C
209 instead of the above-mentioned terminating code.
Mode code is latched as valid code.

Makeup code 1 and makeup code 2 above
FIG. 18 shows a circuit for controlling the generation and storage of the data, etc., and this circuit is included in the timing circuit 112. Timing chart of this circuit (run length is <2 as mentioned above)
972) is shown in FIG. In the figure, 180
1.1802 is a flip-flop, 1803 is an AND gate, and 1804 is an inverter.

MKI and MK2 are signals output from the 2559 detection circuit 1301 and the 63 detection circuit 1302, respectively, of the run length counter 203 shown in FIG. The flip-flop 1802 is set by the input of the MK2 signal and generates the MK2 presence signal, and the flip-flop 1801
is set by the input of the MKI signal and generates the MKI presence signal. Note that the flip-flop 1802 is reset by inputting the MKI signal.

With the above configuration, the run length counter 203
When the count value becomes 64 or more, the MK2 signal becomes high level, and when the count value becomes 2560 or more, the MK2 signal becomes high level.
Only the KI presence signal or both the MK2 presence signal and the MK2 presence signal become high level. The levels of the MKL signal and MK2 signal determine whether the code representing the run length is only a termination code, a combination of a termination code and a makeup code, and whether the number of makeup codes is 1 or 2. You can determine if there is. Therefore, H
When generating a code in this mode, the backing circuit 211 determines the levels of the MKI present signal and the MK2 present signal, selects the valid one among the three latches A, B, and C, and outputs the latch data. Take in.

In this way, when the make-up code is generated, by predicting the generation of the code at least one time in advance and sending the code to the temporary memory circuit (latches A and B), the change point a1 is reached. This has the effect of preventing an increase in the number of output codes and the number of bits that must be processed at the same time.
Extremely effective.

That is, by temporarily storing the required make-up code and code length out of the numbers counted by the latch A207 and the latch B2O3 Heran length counter 203 before deciding on the H mode, the terminating code and code length are stored when the H mode is decided. Since it is only necessary to process the H-mode code to be output at the time of a1 detection, all the H-mode codes to be output are available, and the subsequent encoding operation can be executed without delay.

207, 208, 209 latches A, B.

The order in which the contents of C are sent to the next stage circuit is latch A207>
Controlled to maintain the order of latch B2O3 > latch C209 (21O buffer) (omitted when the contents are invalid,
ignore).

The reason why the contents of the latch C209 are stored in the -H buffer memory 210 is because the next encoding operation starts from the time after the encoding mode is determined, and the next encoded data is stored in the latch C209 from the ROM table for several clocks. (at least l clocks). Therefore, after the mode is determined, the contents of the latch C209 are sent to the buffer memory 210 so that the next encoded data can be latched, and then output from the buffer memory 210 to the subsequent stage with proper timing.

Next, a special case in which the change point a1 and the change point a2 are set on the same pixel according to the encoding method will be described.

FIG. 20 illustrates the above case. That is,
In Fig. 20, 2001 is the reference L/ance line,
2002 is a coding line. Further, 2003 is the final pixel of the coding line, and 2004 is a virtual change point (pixel).

Now, in Fig. 20, if we assume that the starting point aQ is at the position shown in the figure as a result of encoding from the left, the next code to be generated is as shown in Fig. 21: [H mode code + white 12 terminator code + black O-terminated code]. Here, the code shown in FIG. 21(1) can be treated as one code by the above-described means at the time of the change point a1, and there is no problem. However, the code in Figure 21 (2) originally had a change point a2.
This is the code that should be generated at the time of the change point a2 when the change point a1 comes at a different time. However, in this case, it is clearly not detected as the change point a2 by the symbol detection circuit 201 and the like.

Therefore, in this case, the following processing is performed by the circuit shown in FIG. 22 provided in the symbol detection circuit 201. FIG. 23 is a timing chart of the operation of this circuit. In FIG. 22, 2201 is a signal indicating that the image has entered the virtual area (
2202 is an a1 change point detection signal, and 2203 is a signal indicating up to the generation of the first termination code in H mode. The signals 2201 to 2 are monitored by the AND gate 2207.
The state shown in FIG. 20 is detected by taking the AND of the 203 signals, and the 2204-1 signal is created (that is, the time is
), first output the code shown in FIG. 20 (1) using the method described above. Next, predetermined processing such as clearing the run length counter to 0 is performed, and the signal 2205-1, which is obtained by delaying the signal 2204-1 shown in FIG. Generates a black 0 termination code.

The backing circuit 211 in FIG. 2 receives as input the code and code length obtained by the method described above, and the length of each code (the number of bits of the code) generated by this division is not constant. However, even if the H mode code (-001) is added, the maximum length is 16 bits), and the circuit is sequentially grouped into 16-bit units, and in this embodiment, each 16-bit bit is transferred in parallel to the next external circuit. This is what we do.

The signal 238 in FIG. 2 is a code compiled into 16 bits by the backing circuit 211, and the signal 239 is a signal for reporting this fact to the next stage external circuit. Note that the backing circuit 211 is a code length addition circuit and a bit shifter.

This can be easily realized by combining well-known circuits such as multiplexers and latches.

Next, there is an RTC (Re turn) indicating the end of one page.
The To Control) signal will now be described. MM
In the case of the R method, RTC code=EOL code×2 times.

That is, the RTC signal is (000000000001)X2=
000000000001.000000000001
It is expressed as Also, in this embodiment, as described above, the structure is such that up to 16 bit codes can be output in one clock time. Therefore, in order to output the RTC signal, the end of one page is detected by monitoring the vertical synchronization signal 136-1 shown in FIG. By giving the address signal 1507 of the ROM table C206 (shown in FIG. You can get it next.

Next, Table 1 lists the differences between the three encoding methods described above.

Therefore, the encoding method of the MH method is almost the same as the case where the H mode of the MMR method described above is repeated, but differs in the following points.

That is, (1) H mode code (001) is not required in the MH method (2) It is not necessary to pair white runs and black runs in the MH method (3) Inserting an EOL code for each line in the MH method (4) Differences in RTC and in the case of the MR method: (1) One-dimensional lines are the same as the MH method (2) Two-dimensional lines are the same as the MMR method (3) Line separation is EOL + 1 = 0000000000011 or EOL + 0 = OOO0000000010 (4) RTC
Difference (5) Due to the K parameter, one-dimensional lines and two-dimensional lines coexist.

After all, switching between the three encoding methods can be easily realized by controlling the operation of the circuit for the MMR method described above using a method selection signal for the MR method or the MH method.

First, Figure 24 shows an example of a circuit that controls the differences between lines, delimiters, and codes. In Figure 24, 2407 is a line counter;
408 is Nantes Gate, 2409 is And Gate, 24
10 is an inverter. That is, 2401 in FIG. 24 is a pulse signal at time t-1 shown in 320 in FIG. 3, which is repeated for each coding line. At time t-1, a code is generated due to image encoding Shinai. This t-11
The 11% pulse signal is obtained by decoding the value of the address counter 111. Also, 2402 and 240
3 is an encoding method selection signal from outside the circuit of this embodiment, such as a CPU, which specifies the encoding method. Also, the 136-2 signal corresponds to the 136-2 signal in FIG.
07 is a signal indicating how the barometer advances in the MR method, 13
6-2 is counted and monitored as a line counter.

Signals 2404 to 2406 obtained by the logic in FIG.
were used as address inputs for the ROM table C206 in Figure 2 (1507 to 1508 in Figure 15), each specifying a specific address, and the code and code length required for the specific address were stored. By outputting something, you can get the desired line, break, or code.

Furthermore, the one-dimensional line encoding method of the MH method is described in the 17th
The selection signal 1708 may be used to control the mode determination circuit of the MMR method shown in the figure so that the H mode can always be given priority.

In addition, in the MH method, the H mode command code (001) is always controlled to be unnecessary, and this is also achieved by setting the address signal A7 of the ROM table C206 to O.

Also, the difference in the number of EOLs in RTC is ROM table C.
This is achieved by varying the number of pulses applied to 206 depending on the mode.

In this embodiment, as shown in FIG. 3, etc., it operates in synchronization with the (image) clock 134, but it is not related to the interval (period) of the clock. Therefore, as shown in Figure 25,
A pause period can be easily provided between images or lines by masking the clock 134 with an image gate signal, so to speak.

That is, in FIG. 25, 2501 is the image gate signal
This is a signal indicating that the operation is suspended during the power level.

Further, 2502 is the gate signal 2501 and the clock 134.
If this clock 2502 is sent to the actual internal circuit of this embodiment in place of the aforementioned clock 134, the state of this embodiment can be changed only by the clock signal. Because it is possible8
The shaded area in Figure 25 is clearly in the rest state.

This pause control controls, for example, the output speed of the image signal of the source of the image signal to be encoded.

There is no restriction on the operation of the encoding circuit. Conversely, even if the image signal for one page is output intermittently, for example when the image source is an image file with a disk, the encoding circuit will not be able to synchronize with the intermittent output. Encoding operations can be performed intermittently. Therefore, the image signal from the output source can be sequentially encoded without requiring a large buffer memory for time adjustment between the image signal output source and the encoding circuit.

Next, a method of supplying images to be encoded to the circuit of this embodiment in a parallel format will be described with reference to FIGS. 26 and 27. That is, 2601 in FIG. 26 is a parallel-to-serial change shift register which can input 8-bit parallel data and output it to 2602 as 1-bit serial data.

As shown in FIG. 27, after loading the image signal to be encoded into the register 2602 as 8-bit parallel data,
The signal is serially shifted by a clock, and a serial image signal 2602 as shown in FIG. 27 is obtained. At the same time, the number of clocks during the serial shift is counted, and a gate signal 2702 indicating the actual data section is generated. Also, a clock 2702 corresponding to actual data can be obtained in the same way.

As described above, the word signal as shown in FIG. 27 is in a format that can be encoded as described above in this embodiment by the pause method described in FIG. 25. The operation for parallel input of this image is Cp
This is extremely effective when an image is provided by u, etc.

In one or more embodiments, MH, MR, and MMR encoding has been described, but it goes without saying that other encoding methods can also be applied. Furthermore, the image signal to be encoded is input from a device that photoelectrically reads an original image, a computer, etc., and the encoded code is transmitted to a remote location via a transmission line or the like, or is stored in an image file. Although the present invention has been described above based on preferred embodiments, the present invention is not limited to this configuration, and various modifications may be made within the scope of the claims.

Needless to say, changes are possible.

Table 1 [Effects] As explained above, according to the present invention, in encoding a long ten-length image signal that requires a plurality of codes, the encoded code is predicted and stored in advance, and the encoded code is read out. Therefore, the burden of the encoding operation at the time of outputting the code can be reduced, and the encoding operation can be executed without delaying the input of one image value code.

[Brief explanation of drawings]

Figures 1 and 2 are block diagrams showing the configuration of an encoding device to which the present invention is applied, Figure 3 is a timing chart showing the encoding operation, and Figures 4, 5, and 6 are reference line diagrams. 7 is a diagram showing a configuration example of a virtual change point generation circuit, FIG. 8 is a timing chart diagram showing the operation of the circuit shown in FIG. 7, and FIG. 9 is a configuration example of a selector. Figure 10 is a diagram showing an example of the configuration of a change point detection circuit, Figures 11 and 12 are diagrams showing an example of the configuration of the symbol detection circuit, and Figure i13 is a diagram showing an example of the configuration of a ten-length counter. 14 is a diagram showing an example of the circuit configuration of ROM table A, and FIG. 15 is a diagram showing an example of the circuit configuration of ROM table A.
FIG. 16 is a diagram showing an example of the contents of ROM table C, FIG. 17 is a diagram showing an example of the configuration of the code determination circuit, and FIG. 18 is a configuration example of the make-up code generation and storage circuit. 19 is a timing chart showing the operation of the circuit shown in FIG. 18, FIG. 20 is a diagram showing the relationship between the beam reference line and the coding line, and FIG.
Figure 22 is a diagram showing a configuration example of a delay circuit at a virtual change point, Figure 23 is a timing chart diagram showing the operation of the circuit shown in Figure 22, and Figure 24 is a diagram showing control of generation of line separation codes. Diagram 25 showing an example of the configuration of a circuit for
26 is a timing chart showing a pause control operation of the encoding operation, FIG. 26 is a diagram showing a configuration example of a circuit that serially outputs parallel input of an image signal, and FIG. 27 is a timing chart showing the output state of the circuit shown in FIG. 26. It is a chart diagram, and 10
1 and 105 are virtual change point generation circuits, 106 and 107
is a change point detection circuit, 108 to 110 are registers, 111
is an address counter, 201 is a symbol detection circuit, 203 is a run length counter, and 207 to 209 are latches. Fig. 7: Fig. 8 刹5e fig.

Claims (1)

[Claims] A means for counting the number of pixels between changing points of an image signal inputted serially, and a count value of the above-mentioned counting means is 64n+63(n
= 0, 1, 2---), if the pixel is not a change point, means for storing a first encoded code representing 64 (n+1), and a count value of less than 64 of the counting means; means for generating a second encoded code representing a pixel, and reads out the first encoded code stored in the storage means at the time when a change point pixel is reached, and also causes the generation means to generate a second encoded code. An image signal encoding device characterized by generating a code.