JPS6231166A - Buried gate type semiconductor element - Google Patents

Abstract

PURPOSE:To improve dielectric strength while improving current durability by a method wherein emitter layers are extended to main current conduction layers provided between buried gate layers and are connected as a whole by a diffused layer. CONSTITUTION:Gallium is diffuses from the whole surfaces of both sides of an N-type silicon substrate to form P1-N1-P2 layers. Then boron and phosphorus are selectively diffused into the surface of the P2 layer individually to form high concentration layers P2<++> and N2 layers in main current conduction layers between the high concentration layers P2<++>. Then a P-type epitaxial layer P2 is formed on the surface where the P2<++> layers and the N2 layers are formed and N22 layers are formed in that P2 epitaxial layer at the positions facing the N2 layers. Then phosphorus is diffused into the whole surface to form an N-type layer N23 and N2, N22 and N23 layers are linked together to form a cathod N2 layer. After that, electrodes A, K and G are connected to compose a GTO thyristor. With this constitution, widths omega of the N2 layers can be narrowed while circumference lengths of P2-N2 junctions being shortened so that current durability and a dielectric strength can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Field of Industrial Application This invention relates to a gate-embedded semiconductor device in which a low-resistance gate layer is embedded in a gate layer.

B9 Summary of the Invention The present invention provides a buried gate semiconductor device having a structure having an emitter layer extending to a main current conduction layer sandwiched between buried gate layers and connected to the entire surface by a diffusion layer. This makes it possible to improve the withstand voltage while improving the current withstand capacity.

C1 Conventional technology FIG.
It is formed of 4 layers and 3 junctions of N, PJz and low resistance gate layers P and ++ buried in 22 layers. In the SIRISK having the structure shown in FIG.
A gate electrode G is provided on a predetermined surface of the ,+++ layer.

Since the operation of the thyristor described above is well known, a detailed explanation of the operation will not be given.Here, the turn-off operation of the thyristor in question will be described. When the thyristor is in a conductive state, current flows in the direction from the anode electrode A to the cathode electrode through a region sandwiched between the 27 P and +4 layers facing the cathode N2 layer. At turn-off, this current flows from the P2++ layer through the gate electrode G to an external circuit (not shown), and transitions to an OFF, ie, cutoff, state in a short time. The conduction area is usually formed in a rectangular shape, and is generally about 0.3 mm x 5 mm. ω in FIG. 5 indicates the narrow side (corresponding to 0.3 mm) of the conduction region. It is known that when the conduction width ω is changed, the turn-off current It is also changed, and this relationship is illustrated in FIG. 6. In FIG. 6, an experimental unit thyristor having 10 rectangular sections was fabricated and measured. 6th
As can be seen from the figure, when only the width ω is changed, the smaller ω is, the more the turn-off current IT increases, but if ω is too small, it tends to be saturated. From this, it has been found that in order to manufacture a silisk capable of large current turn-off, the width ω should be made as small as possible. The reason for this is that when the width ω is made smaller as described above, the conduction region, that is, the lateral direction of ω/2 (p
This is considered to be because the resistance (toward the t'' side) becomes smaller.However, it was also found that the increase rate of the turn-off current IT was lower than the previously predicted value (the dotted line in FIG. 6).

D1 Problems to be Solved by the Invention The reason why the turn-off current IT becomes lower than the predicted value (dotted line shown in FIG. 6) as described above arises from the following reasons. As shown in FIG. 7, the width ω of the conduction region is p
The width is narrowed by approximately 2Δω due to crystal defects d generated from the end face of the t+++ layer during the evixaxial growth process. If the width is narrowed by Δω in this way, the gate current cannot be sufficiently swept to the P1 layer due to the existence of the lateral resistance r of p,li. From this result, it was found that there was a problem in that the rate of increase in turn-off current was low. In addition, A- during current conduction
There is also a problem that the inter-mold pressure drop value becomes larger than the expected value because the area of the conduction region is reduced by a portion corresponding to 2Δω.

In order to solve these problems, as shown in FIG. 8 (A) showing a cross section of the main part and FIG. A conceivable structure is to place it on the same plane as the That is, the high concentration P2++ layer and the N2 layer are selectively separated and diffused from the surface of the P1 layer, and the P, +
The surface of the + layer is covered with an oxide film SiO2, including the ends of the N2 layer, and aluminum A12 is deposited on the entire surface to form a cathode electrode. At this time, as shown in FIG. 8(B), a segment structure is formed in which the P and +4 layers are connected and the N2 layer is distributed.

With such a structure, the occurrence of defective layers, which is the problem shown in FIG. 7, is eliminated, and the width ω of the N2 layer can be narrowed as necessary.

However, since the N2 layer is placed separately, the N7 layer and the
The interface between the three layers, that is, the perimeter of the junction, becomes very long, and N2F2
There is a problem that a high reverse breakdown voltage of the junction cannot be obtained.

Means and Effects for Solving Problem E9 This invention comprises an emitter layer formed by diffusion to extend to the main current conduction layer sandwiched between the buried gate layers, and whose entire surface is bonded by the diffusion layer, and which is composed of a P2N2 layer. The purpose is to obtain a structure in which the width ω of the N7 layer is narrowed without shortening the junction peripheral length.

F. Example FIG. 1 is a sectional view of a main part showing an embodiment of the present invention.

High concentration buried layers P and ++ are diffused and formed in a predetermined pattern in the base 22 layer. A cathode N is provided in the base 23 layer (main current, conduction layer) sandwiched between the buried layers P2++.

The N3 layer is formed by diffusion so that the layer extends from the base 2.
The two layers are connected by a cathode N9 layer, which is a thin diffusion layer formed on the entire surface.

Such a structure is realized by the procedure described below with reference to FIG.

Gallium is completely diffused from both sides of an N-type silicon substrate to form a P
, N, P layers (surface concentration I x 10 layers about 7) are formed. Next, boron and phosphorus are individually and selectively diffused onto the surface of the P7 layer to form an N1 layer in the high concentration layers P and ++ and the main current conducting layer therebetween (FIG. 2a). At this time, the surface concentration is 9 or more layers of 5 x 10 layers for boron and 5 x 1 layer for phosphorus.
The width ω of the N2 layer can be made narrower if necessary, but the spacing between the N2 layer and the P and +4 layers should be approximately 5 μm or more. Also, the width of the P2++ layer should be set according to the buried resistance. The thickness is usually 200 to 300 μm.

Next, 5 to 10μ
A P-type epitaxial single crystal layer P having a thickness of about m is grown (FIG. 2b). Next, in the single crystal layer P, an N22 layer is formed at a position opposite to the N1 layer with a diffusion depth of 5 μm9 and a surface concentration of 5×10” (Fig. 2C). Next, the entire surface is covered with IX
Diffuse phosphorus at about 1020, N,, N2. , N
, , are connected to form the cathode N3 layer (FIG. 2d).

Therefore, the p, +4 layer has a shape in which half of its surface is surrounded by the N7 layer. After this, as shown in FIG. 1, the necessary electrodes A and G are connected to form a GTO cyrisk.

What should be noted here is that when forming an epitaxial layer on the surface of the high concentration buried layer P, the width Δω of the conventional defect layer can be reduced by reducing the growth thickness of the layer. I can do it. Therefore, it is desirable that the growth thickness on the high-concentration P, ++ layer is 10 μm or less, and under this condition, Δω will grow to at most 5 μm, and ω will be significantly shortened, greatly increasing the current withstand capacity. Furthermore, the reverse breakdown voltage can be increased by reducing the N, P, and bonding surface lengths.

FIG. 3 shows the change in the blocking property of the thyristor prototyped based on the present invention, and it is clear that the withstand capability can be greatly improved by reducing ω=t, OC design value 200 μ). Further, even if ω is made small, the reverse breakdown voltage of the N, P, and junctions can be easily obtained at a value close to the design value without being complicated as in the conventional case shown in FIG.

In addition, in the example, P is used as the pretreatment in FIG.
A high resistance epitaxial layer P, - is formed on the surface of the first layer (fourth
By doing so, the reverse breakdown voltage of the N, P junction can be further increased.

In addition, 1. Although the embodiment has been explained in the case of GTO Cyrisk, the present invention is not limited to this, but can be applied to other methods in which a high concentration layer is partially buried using epitaxial technology and this is used as a control electrode. It goes without saying that the present invention can also be applied to self-extinguishing elements such as static induction transistors and static induction transistors to obtain similar effects.

G1 Effects of the Invention As described above, according to the present invention, the emitter layer is formed to extend to the main current conducting layer sandwiched between the high concentration buried gate layers, and the entire surface is bonded by the diffusion layer. , P2
N2 Do not shorten the junction peripheral length.

The layer width ω can be narrowed, and an element with improved current resistance and voltage resistance can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional structural diagram of main parts showing one embodiment of the present invention;
The figure is a process diagram showing an example of the manufacturing method for obtaining the structure shown in Figure 1, Figure 3 is a characteristic diagram of conduction layer ω versus turn-off current IT in the present invention, and Figure 4 is another embodiment of the present invention. 5 is a sectional view of a conventional gate turn-off side risk, and FIG. 6 is a sectional view of ω vs. I in FIG. 5.
T characteristic diagram, FIG. 7 is an enlarged sectional view for explaining the problems of the conventional example, and FIGS. 8(A) and 8(B) are sectional views showing other conventional structures and A-A. ' is a plan view taken along. P, +4...high concentration layer, N2...emitter layer, K.
... Cathode electrode, A... Anode electrode. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5

Claims (3)

[Claims] (1) forming a low-resistance impurity diffusion layer in a predetermined pattern on the base layer, using the diffusion layer as a control electrode to conduct between the main electrodes;
A buried-gate semiconductor device that obtains a blocking state, characterized by comprising an emitter layer that is formed by diffusion to extend to the main current conducting layer sandwiched between the diffusion layers, and that is bonded to the entire surface by the diffusion layers. A buried-gate semiconductor device. (2) A buried gate type semiconductor device according to claim 1, characterized in that the epitaxial growth layer between the diffusion layer and the emitter layer is formed thinly. (3) The buried-gate semiconductor device according to claim 1 or 2, wherein the base layer has a structure in which a portion where the diffusion layer and the emitter layer are formed is a high-resistance epitaxial growth layer.