JPS6230541B2 - - Google Patents
Info
- Publication number
- JPS6230541B2 JPS6230541B2 JP55145496A JP14549680A JPS6230541B2 JP S6230541 B2 JPS6230541 B2 JP S6230541B2 JP 55145496 A JP55145496 A JP 55145496A JP 14549680 A JP14549680 A JP 14549680A JP S6230541 B2 JPS6230541 B2 JP S6230541B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- oscillation
- terminal
- intermediate frequency
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000010355 oscillation Effects 0.000 claims description 40
- 230000003321 amplification Effects 0.000 claims description 11
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
- H04B1/26—Circuits for superheterodyne receivers
- H04B1/28—Circuits for superheterodyne receivers the receiver comprising at least one semiconductor device having three or more electrodes
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stereo-Broadcasting Methods (AREA)
- Noise Elimination (AREA)
Description
【発明の詳細な説明】
本発明はFM中間周波増幅器を含むPLL
（Phase Locked Loop）方式のFMステレオ復調
回路用半導体集積回路、あるいはFM中間周波増
幅器を含むPLL方式のFM検波回路用半導体集積
回路に用いて好適な信号処理回路に関するもので
ある。FM中間周波増幅回路とPLL回路を同一チ
ツプ上に内蔵する半導体集積回路においては、
AM放送を受信するときに、内部発振周波数によ
るノイズあるいは発振周波数の高周波によるビー
ト妨害をさけることが必要なときがある。そこ
で、従来のこの種の半導体集積回路では、この発
振停止のために専用の制御端子を設けていた。し
かし、半導体集積回路においては外部端子数に制
限があるので、上記専用の制御端子を設けること
は問題であつた。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a PLL including an FM intermediate frequency amplifier.
The present invention relates to a signal processing circuit suitable for use in a semiconductor integrated circuit for a (Phase Locked Loop) type FM stereo demodulation circuit or a PLL type FM detection circuit including an FM intermediate frequency amplifier. In semiconductor integrated circuits that incorporate an FM intermediate frequency amplifier circuit and a PLL circuit on the same chip,
When receiving AM broadcasts, it is sometimes necessary to avoid noise due to the internal oscillation frequency or beat interference due to the high frequency of the oscillation frequency. Therefore, in conventional semiconductor integrated circuits of this type, a dedicated control terminal is provided for stopping this oscillation. However, since there is a limit to the number of external terminals in a semiconductor integrated circuit, providing the above-mentioned dedicated control terminals has been problematic.
この発明はこのような点に鑑みてなされたもの
で、発振制御回路を設けて、中間周波増幅回路の
信号入力端子に対するレフアレンス端子を上記発
振制御回路の制御信号入力端子として共用し、こ
の端子が所定電位になつたとき発振回路の発振動
作が停止するようにすることにより、上記発振停
止のための専用の外部端子を設ける必要がなく、
半導体集積回路化するに好適な信号処理回路を提
供することを目的とする。 The present invention has been made in view of these points, and includes an oscillation control circuit, in which a reference terminal for the signal input terminal of the intermediate frequency amplification circuit is shared as a control signal input terminal of the oscillation control circuit, and this terminal is By stopping the oscillation operation of the oscillation circuit when a predetermined potential is reached, there is no need to provide a dedicated external terminal for stopping the oscillation.
It is an object of the present invention to provide a signal processing circuit suitable for fabrication into a semiconductor integrated circuit.
第１図は本発明の原理的構成を示すブロツク
図、第２図はその具体的構成の一例を示す回路図
である。第１図において、１は中間周波（IF）
増幅回路、２は発振制御回路、３は発振回路、４
は中間周波増幅回路１の信号入力端子、５は中間
周波増幅回路１のレフアレンス端子と発振制御回
路２の制御信号入力端子を兼ねる端子、６は中間
周波増幅回路１の出力端子、７は発振制御回路２
の動作レベルを定める基準電圧端子、８は前記端
子５と中間周波増幅回路１のレフアレンス端子を
接続する線路、９は前記端子５と発振制御回路２
の入力端子を接続する線路、１０は発振制御回路
２の出力端子と発振回路３の制御入力端子とを接
続する線路を示す。第２図において、中間周波増
幅回路１はNPNトランジスタ１２，１３からな
る差動増幅器であり、NPNトランジスタ１２，
１３のエミツタは抵抗２０を介して接地されてい
る。トランジスタ１２のベースは信号入力端子４
となり、またそのコレクタは電源ライン４０に接
続されている。トランジスタ１３のベースは前記
端子５に線路８を介して接続されると共に、抵抗
１８を介して端子４に接続され、さらに端子５は
コンデンサ２３を介して接地されている。トラン
ジスタ１３のコレクタは抵抗１９を通して電源ラ
イン４０に接続されており、トランジスタ１３の
コレクタと抵抗１９の接点が出力端子６となつて
いる。端子５はまた、発振制御回路２を構成する
PNPトランジスタ３０のベースへ抵抗２９を介し
て接続されており、トランジスタ３０のエミツタ
は基準電圧端子７へ接続され、そのコレクタは抵
抗３５を介してNPNトランジスタ３２のベース
へ接続されている。トランジスタ３２のベースは
リーク電流吸収用の抵抗３６を介して接地され、
そのエミツタは直接接地されている。基準電圧端
子７は抵抗３３を介して電源ライン４１に接続さ
れると共に、ダイオード３１と抵抗３４を直列に
介して接地されている。発振回路３は、抵抗３７
とダイオード３８によるバイアス回路により定常
状態の回路動作が行われるように構成されてい
る。抵抗３７の一端は電源ライン４１に接続さ
れ、他端はダイオード３８を介して接地されてい
る。発振制御回路２の発振制御出力端子であるト
ランジスタ３２のコレクタは、発振回路３の発振
回路制御入力端子であるダイオード３８と抵抗３
７との接点へと線路１０を介して接続されてい
る。 FIG. 1 is a block diagram showing the basic structure of the present invention, and FIG. 2 is a circuit diagram showing an example of the specific structure. In Figure 1, 1 is the intermediate frequency (IF)
Amplifier circuit, 2 is oscillation control circuit, 3 is oscillation circuit, 4
is a signal input terminal of the intermediate frequency amplifier circuit 1, 5 is a terminal that serves both as a reference terminal of the intermediate frequency amplifier circuit 1 and a control signal input terminal of the oscillation control circuit 2, 6 is an output terminal of the intermediate frequency amplifier circuit 1, and 7 is an oscillation control terminal. circuit 2
8 is a line connecting the terminal 5 and the reference terminal of the intermediate frequency amplification circuit 1; 9 is a line connecting the terminal 5 and the oscillation control circuit 2;
10 indicates a line connecting the output terminal of the oscillation control circuit 2 and the control input terminal of the oscillation circuit 3. In FIG. 2, the intermediate frequency amplification circuit 1 is a differential amplifier consisting of NPN transistors 12 and 13.
The emitter 13 is grounded via a resistor 20. The base of the transistor 12 is the signal input terminal 4
and its collector is connected to the power supply line 40. The base of the transistor 13 is connected to the terminal 5 via a line 8 and also to the terminal 4 via a resistor 18, and further, the terminal 5 is grounded via a capacitor 23. The collector of the transistor 13 is connected to a power supply line 40 through a resistor 19, and the contact point between the collector of the transistor 13 and the resistor 19 is an output terminal 6. Terminal 5 also constitutes oscillation control circuit 2
It is connected to the base of a PNP transistor 30 via a resistor 29, its emitter is connected to the reference voltage terminal 7, and its collector is connected via a resistor 35 to the base of an NPN transistor 32. The base of the transistor 32 is grounded via a leakage current absorbing resistor 36.
Its emitter is directly grounded. The reference voltage terminal 7 is connected to a power supply line 41 via a resistor 33, and is grounded via a diode 31 and a resistor 34 in series. The oscillation circuit 3 includes a resistor 37
A bias circuit including a diode 38 and a diode 38 are configured to perform steady state circuit operation. One end of the resistor 37 is connected to the power supply line 41, and the other end is grounded via a diode 38. The collector of the transistor 32, which is the oscillation control output terminal of the oscillation control circuit 2, is connected to the diode 38, which is the oscillation circuit control input terminal of the oscillation circuit 3, and the resistor 3.
7 via a line 10.
第２図の回路において、レフアレンス端子５
は、中間周波増幅回路１によつてある一定電位に
バイアスされている。また、基準電圧端子７の電
位は、抵抗３３，３４、ダイオード３１により、
定常状態ではトランジスタ３０が導通しない電位
に設定されている。トランジスタ３０が非導通で
あればトランジスタ３２もまた非導通であり、発
振回路３は正常にバイアスされている。次に、
AM放送受信時において、端子５を接地すると、
トランジスタ３０が導通し、トランジスタ３２も
また導通する。トランジスタ３２のコレクタは発
振回路３のバイアス点に接続されているため、ト
ランジスタ３２が導通することにより発振回路３
のバイアス点が接地電位に落ち、発振動作が停止
する。また、AM放送受信時に端子５を接地する
ことにより、中間周波増幅回路１の動作もまた同
時に停止するようになつているため、AM放送受
信時において、中間周波増幅回路１における回路
電流の減少及び中間周波増幅回路１より発生する
雑音の減少が可能となる。 In the circuit shown in Figure 2, reference terminal 5
is biased to a certain constant potential by the intermediate frequency amplification circuit 1. Further, the potential of the reference voltage terminal 7 is controlled by the resistors 33 and 34 and the diode 31.
In a steady state, the potential is set so that the transistor 30 is not conductive. If transistor 30 is non-conductive, transistor 32 is also non-conductive, and oscillation circuit 3 is normally biased. next,
When receiving AM broadcasting, if terminal 5 is grounded,
Transistor 30 conducts and transistor 32 also conducts. Since the collector of the transistor 32 is connected to the bias point of the oscillation circuit 3, when the transistor 32 becomes conductive, the oscillation circuit 3
The bias point falls to ground potential and the oscillation operation stops. Furthermore, by grounding the terminal 5 during AM broadcast reception, the operation of the intermediate frequency amplification circuit 1 is also stopped at the same time, so that the circuit current in the intermediate frequency amplification circuit 1 decreases and The noise generated by the intermediate frequency amplification circuit 1 can be reduced.
ここで、発振制御回路２のダイオード３１は、
トランジスタ３０の温度補償の目的で挿入してい
るものであり、ダイオード３１の代わりに抵抗を
用いてもよい。 Here, the diode 31 of the oscillation control circuit 2 is
This is inserted for the purpose of temperature compensation of the transistor 30, and a resistor may be used instead of the diode 31.
以上のようにこの発明によれば、発振停止のた
めの専用の外部端子を設ける必要がないので、半
導体集積回路における外部端子の利用効率が向上
する。 As described above, according to the present invention, there is no need to provide a dedicated external terminal for stopping oscillation, so the efficiency of using external terminals in a semiconductor integrated circuit is improved.
第１図は本発明の概念を示すブロツク図、第２
図はその具体的構成の一実施例を示す回路図であ
る。
図において、１は中間周波増幅回路、２は発振
制御回路、３は発振回路、４は信号入力端子、５
はレフアレンス端子と制御信号入力端子を兼ねる
端子である。なお、図中同一符号は同一または相
当部分を示す。
Figure 1 is a block diagram showing the concept of the present invention, Figure 2 is a block diagram showing the concept of the present invention.
The figure is a circuit diagram showing an example of the specific configuration. In the figure, 1 is an intermediate frequency amplification circuit, 2 is an oscillation control circuit, 3 is an oscillation circuit, 4 is a signal input terminal, and 5 is an oscillation control circuit.
is a terminal that serves both as a reference terminal and a control signal input terminal. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
する中間周波増幅回路と、上記レフアレンス端子
と共通接続された制御信号入力端子を有する発振
制御回路と、この発振制御回路によつて発振動作
が制御される発振回路とを備え、上記レフアレン
ス端子と制御信号入力端子の共通端子が第１電位
のとき、上記発振制御回路は上記発振回路の発振
動作を停止させるように動作し、かつ上記中間周
波増幅回路は中間周波増幅の動作を停止し、上記
共通端子が第２電位のとき、上記発振制御回路は
上記発振動作を停止させる動作を停止し、かつ上
記中間周波増幅回路は中間周波増幅動作を行うよ
うにしたことを特徴とする信号処理回路。1. An intermediate frequency amplifier circuit having a reference terminal for a signal input terminal, an oscillation control circuit having a control signal input terminal commonly connected to the reference terminal, and an oscillation circuit whose oscillation operation is controlled by the oscillation control circuit. When the common terminal of the reference terminal and the control signal input terminal is at a first potential, the oscillation control circuit operates to stop the oscillation operation of the oscillation circuit, and the intermediate frequency amplification circuit operates to amplify the intermediate frequency. When the operation of the oscillation control circuit is stopped and the common terminal is at a second potential, the oscillation control circuit stops the operation of stopping the oscillation operation, and the intermediate frequency amplification circuit performs an intermediate frequency amplification operation. Characteristic signal processing circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14549680A JPS5768935A (en) | 1980-10-16 | 1980-10-16 | Signal processing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14549680A JPS5768935A (en) | 1980-10-16 | 1980-10-16 | Signal processing circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5768935A JPS5768935A (en) | 1982-04-27 |
| JPS6230541B2 true JPS6230541B2 (en) | 1987-07-02 |
Family
ID=15386597
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14549680A Granted JPS5768935A (en) | 1980-10-16 | 1980-10-16 | Signal processing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5768935A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6411651U (en) * | 1987-07-14 | 1989-01-20 |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4961916U (en) * | 1972-09-09 | 1974-05-30 |
-
1980
- 1980-10-16 JP JP14549680A patent/JPS5768935A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6411651U (en) * | 1987-07-14 | 1989-01-20 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5768935A (en) | 1982-04-27 |
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