JPS62299771A - Frequency comparator - Google Patents

Abstract

PURPOSE:To compare frequencies and to reduce a circuit element by utilizing electric charge and discharge of a capacitor. CONSTITUTION:The signals f1, f2 of the frequencies f1Hz, f2Hz are supplied to input terminals 101, 102 respectively. A reverse polarity voltage is impressed to the gates of transistors (Tr)1, 2 by the function of an inverter 8 corresponding to the supply of this signal f1. When the Tr1 is turned on, a capacitor CD5 is charged by the electric power source which is from a terminal 104; when the Tr2 is turned on, a CD7 is charged by the discharge of CD5 through the Tr2. In the same way, a CD6 repeats charge and discharge in the frequency of f2Hz by impressing the signal frequency f2 to the terminal 102, the charge of the CD7 charges the CD6 in this case. The number of charging times of the CD7 is thereby proportional to the frequency f1, if f1>f2, the voltage across the terminal CD7 increases to output an L level on a terminal 103; if f1<f2, the voltage across the terminal CD7 drops to output an H level on the terminal 103.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a frequency comparator, and more particularly to a frequency comparator that performs frequency comparison using the amount of charge stored in a capacitor.

(Prior art J) A conventional frequency comparator digitally uses a timer 1.
It consisted of 2 counters, 2 registers, and 1 subtractor.

That is, for a certain period of time, a signal with frequency f3 and a signal with frequency fb are supplied to separate counters, each frequency is calculated, and the difference between the values of two registers that store the calculation results is found and compared using a subtracter. I was going.

[Problem that the invention seeks to solve]

As described above, since the conventional frequency comparator is composed of many functional blocks, it has the disadvantage that it requires a large layout area.

[Means for solving problems]

The frequency comparator of the present invention includes a first capacitor, second and third capacitors having a smaller capacitance value than the first capacitor and substantially equal capacitance values, and a first frequency applied from the outside. a first charging/discharging step in which the second capacitor is charged and discharged at the first frequency in response to the supply of a signal, a charging current is supplied from one terminal of a power supply, and a discharging current is supplied to the first capacitor; means for charging and discharging the third capacitor at the second frequency in response to an external supply of a signal having a second frequency, supplying a charging current from the first capacitor and generating a discharging current. and a second charging/discharging means that supplies the power to the other terminal of the power source.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

Frequency comparison in Figure 1? ; is each node (connection point > A
, B, D and the earth (the capacitance values are C5°C6, C7, respectively) are connected between the power supply terminal 104 and the node A, and their gates are connected between the power supply terminal 104 and the node A. a transistor 1 connected to one side of the inverter 8;
A transistor 2 is connected between node A and node B, and its gate is connected to input terminal 101;
transistor 3 connected between node B and the ground and its gate connected to one side of inverter 9; transistor 4 connected between node B and the ground and its gate connected to input terminal 102; and an inverter 8 connected between the gate of the transistor 3 and the input terminal 102, and an inverter 10 connected between the output terminal 103 and the node 1. It is configured. Transistors 1 and 2 are of the same type, and transistors 3 and 4 are of the same type.
Both are the same type of transistor.

The following relationship exists between the capacitance values of capacitors 5.6 and 7.

C3=C6<<C7 Next, the signals that are the targets of 0 frequency comparison to explain the operation in FIG. The frequency of f is flHz).

Signal f1 is supplied to input terminal 101, and signal f2 is supplied to input terminal 102.

In response to the supply of signal f1, voltages of opposite polarity are applied to the gate of L-transistor 1 and the gate of transistor 2 by the action of inverter 8, respectively. That is, during the period when the gate voltage of transistor 1 is high, the gate voltage of transistor 2 is low, and during the period when the gate voltage of transistor 1 is low, the gate voltage of transistor 2 is high. By applying the gate voltage as described above), when transistor 1 is on, transistor 2 is off, and when transistor 1 is off, transistor 1 is on, and if we focus on the individual transistors, their on state. The off frequency becomes the frequency fullz of the input signal f. As a result of the above operation, when the transistor 1 is on, the capacitor 5 is charged by the power from the power supply terminal 104, and when the transistor 2 is on, the charge in the capacitor 5 is discharged through the transistor 2, and the capacitor 7 is charged.

That is, by applying the signal r1 to the input terminal 101, the capacitor 5 is repeatedly charged and discharged at a frequency of flllz, thereby charging the capacitor 7.

By applying the signal f2 to the input terminal 102 in the same manner as described above, the capacitor 6 is repeatedly charged and discharged at a frequency f211z, but at the bottom, the charge of the capacitor 7 charges the capacitor 6. That is, the capacitor 7 is discharged by charging and discharging the capacitor 6.

As described above, the number of times the capacitor 7 is charged is determined by the frequency f,
The number of times the capacitor 7 is discharged is proportional to the frequency f2, and when f+>fz, the voltage across the terminals of the capacitor 7 increases, and a poW level is output to the terminal 103, and f+
(At f2, the voltage between the terminals of the capacitor 7 drops and a high level is output to the terminal 103.

As described above, in this embodiment, it is possible to compare the frequencies of two input signals.

In this embodiment, an inverter and transistors of the same type are used to charge and discharge the capacitors 5 and 6, but the present invention is not limited to this, and responds to the frequency of the supplied signal. Depending on the frequency, a reed relay or the like may also be used as long as it performs opening and opening operations.

〔Effect of the invention〕

As explained above, the present invention has the advantage that by utilizing capacitor charging and discharging, frequencies can be compared and the number of circuit elements can be reduced.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. 1.2.3.4...1~ransistor, 5.6.7...
・Capacitor, 8, 9.10... Inverter, 10
1.102...Input terminal, 103...Output terminal, 1
04...Power terminal. ,・−”−１

Claims (2)

[Claims] (1) a first capacitor; second and third capacitors having a smaller capacitance than the first capacitor and substantially the same capacitance; and responding to an external supply of a signal having a first frequency. a first charging/discharging means for charging and discharging the second capacitor at the first frequency, supplying a charging current from one terminal of a power supply and supplying a discharging current to the first capacitor; In response to the supply of a signal having a second frequency, the third capacitor is charged and discharged at the second frequency, a charging current is supplied from the first capacitor, and a discharging current is supplied to the other terminal of the power supply. A frequency comparator comprising: a second charging/discharging means for supplying a voltage to the frequency comparator. (2) The frequency comparator according to claim (1), wherein the charging/discharging means includes two transistors of the same type to which gate voltages of opposite polarity are applied by a signal supplied from the outside.