JPS62299085A - Vertical field-effect transistor - Google Patents
Vertical field-effect transistorInfo
- Publication number
- JPS62299085A JPS62299085A JP61143397A JP14339786A JPS62299085A JP S62299085 A JPS62299085 A JP S62299085A JP 61143397 A JP61143397 A JP 61143397A JP 14339786 A JP14339786 A JP 14339786A JP S62299085 A JPS62299085 A JP S62299085A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- drain
- resistance
- concentration
- spreading
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 7
- 238000009792 diffusion process Methods 0.000 claims abstract description 7
- 239000012535 impurity Substances 0.000 claims abstract description 4
- 239000004065 semiconductor Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 description 5
- 238000002844 melting Methods 0.000 description 3
- 230000008018 melting Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 239000008186 active pharmaceutical agent Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔産業上の利用分野〕
本発明は、縦形電界効果トランジスタに関し、特に１
自己整合形２重拡散型縦形電界効果トランジスタ（以後
ＤＭＯ８ＦＥＴ と略記する）の構造に関する。Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a vertical field effect transistor, particularly 1.
This invention relates to the structure of a self-aligned double diffused vertical field effect transistor (hereinafter abbreviated as DMO8FET).
従来、この種のＤＭＯ８ＦＥＴは、ゲート電極をマスク
として、ベース層とソース層とを形成し、その拡散横方
内拡がシ差分をチャネルとして利用する構造となってお
り、電極とのずれが生じにくく、無効ゲート面積を抑え
しかも高耐圧化が容易であると云った利点がある。Conventionally, this type of DMO8FET has a structure in which a base layer and a source layer are formed using the gate electrode as a mask, and the diffusion lateral inward expansion uses the difference as a channel, resulting in misalignment with the electrode. It has the advantages of being difficult to use, suppressing the ineffective gate area, and easily increasing the breakdown voltage.
上述した従来のＤ Ｍ ＯＳ Ｆ Ｅ Ｔ に電流を
流す場合、ＤＭＯ３ＦＥＴ での消費電力は、その抵
抗分（順方向ドレイン−ソース間抵抗二以下ＲＤＳ（ｏ
ｎ）と呼ぶ）で決定される。このため、 ）（＋ＤＳ（
ｏｎ）が低い程優秀なＦＥＴ と云える。この几ＤＳ
（ｏｎ） の構成要素を第４図に示す。図中の抵抗は
それぞれチャネル抵抗１１、ジャンクションＦＥＴ 部
抵抗１２、ドレイン低濃度層抵抗１３、ドレイン高濃度
層抵抗１４である。この中で、ドレイン高濃度層抵抗１
４は他の要素と比べて格段に小さく、主に１４Ｄｓ（ｏ
ｎ）を決定するのは他の３者である。When current flows through the conventional DMO3FET mentioned above, the power consumption in the DMO3FET is calculated by its resistance (forward drain-source resistance less than 2 RDS(o
n)). For this reason, )(+DS(
It can be said that the lower the on), the better the FET. This box DS
(on) components are shown in FIG. The resistances in the figure are a channel resistance 11, a junction FET part resistance 12, a low concentration drain layer resistance 13, and a high concentration drain layer resistance 14, respectively. Among these, drain high concentration layer resistance 1
4 is much smaller than other elements, mainly 14Ds (o
The other three parties decide n).
ＤＭＯＳＦＥＴ の特徴は高耐圧化が容易な事だが、高
耐圧化のためにはドレイン低濃度層の濃度を下げて、厚
くする必要がある。このため上述の構成要素中、ジャン
クションＦＥＴ 部抵抗１２とドレイン低濃度層抵抗１
３とが主になって来る。このうちドレイン低濃度層抵抗
１３については前述の通ｂｉ圧とのトレードオフで決定
してしまう。またジャンクションＰＥＴ 部抵抗１２に
ついてもコレクタ低濃度層の濃度によって００時の空乏
層波がりが決まるため、耐圧とトレードオフの関係にあ
った。このため、高耐圧化すると、Ｒｏｓ（ｏｎ）の増
大が避けられないという欠点がある。A feature of DMOSFET is that it is easy to increase the breakdown voltage, but in order to increase the breakdown voltage, it is necessary to lower the concentration of the drain low concentration layer and make it thicker. Therefore, among the above-mentioned components, the junction FET part resistance 12 and the drain low concentration layer resistance 1
3 will be the main one. Among these, the drain low-concentration layer resistance 13 is determined by the trade-off with the above-mentioned conduction pressure. Further, regarding the junction PET resistor 12, the depletion layer wave length at 00 is determined by the concentration of the collector low concentration layer, so there is a trade-off relationship with the breakdown voltage. For this reason, when the breakdown voltage is increased, there is a drawback that an increase in Ros(on) is unavoidable.
本発明によるＤＭＯＳＦＥＴ は、ベース、ソース形成
前に同一拡散窓から自己整合法によって、ベース層をと
りかこむ形で、ドレイン層と同一導電形で不純物濃度が
、ドレイン低濃度層の数倍である層が形成されている。The DMOSFET according to the present invention is manufactured by forming a layer surrounding the base layer using the self-alignment method from the same diffusion window before forming the base and source, and having the same conductivity type as the drain layer and an impurity concentration several times that of the drain lightly doped layer. is formed.
この層の存在によって、導電部の抵抗が下がるとともに
、導電時の、ドレイン層内部への空乏層波がりを抑制し
て、導通部の有効断面積が大きくとれ、前述の、ジャン
クションＦＥＴ 部抵抗を小さく抑えることができる。The presence of this layer lowers the resistance of the conductive part, suppresses depletion layer waves inside the drain layer during conduction, and increases the effective cross-sectional area of the conductive part. It can be kept small.
本発明の縦形電界効果トランジスタは、第１導電型半導
体基板の一主面上に絶縁膜を介して選択的に設けられた
ゲート電極を遮蔽膜としてベース層とソース層とを形成
した自己整合形２重拡散型縦形電界効果トランジスタに
おいて、ベース層を囲む様にドレイン層と同一導電型で
、かつ、ドレイン層より不純物濃度の高い拡散層が形成
されていることを特徴とする。The vertical field effect transistor of the present invention is a self-aligned type in which a base layer and a source layer are formed using a gate electrode selectively provided on one principal surface of a first conductivity type semiconductor substrate via an insulating film as a shielding film. A double diffused vertical field effect transistor is characterized in that a diffusion layer having the same conductivity type as the drain layer and having a higher impurity concentration than the drain layer is formed surrounding the base layer.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例の縦断面図である。第１
図ＤＭＯ８ＦＥＴ はドレイン高濃度層１と、ドレイン
低濃度層２に形成されたウェル部３、本発明の特徴であ
るドレイン中濃度拡散層４、ベース層５およびソース層
６と、絶縁膜層７を介して設けられた多結晶シリコンゲ
ート電極層８とリース層６に接続するリース電極層９と
からなる。この構造により第４図（ｂ）に示すＲＤＳ（
Ｏｎ） の構成要素のうちジャンクションＦＥＴ ｍ
の抵抗１２を小さく抑える様に、ベース層の周りにゲー
ト電極層を遮蔽膜として自己整合によってドレイン低濃
度層の数倍の濃度のドレイン中濃度層４を設けているた
め、その部の抵抗を下げるとともに、ジャンクシ、ンＦ
ＥＴ の導通部への空乏層波がりを抑えて、抵抗を小さ
く抑えることができる。また、この層は自己整合によっ
てベース層とは拡散深さ差だけで区分されているためご
く薄く、また濃度的にも数倍に抑えているため逆バイア
ス時の空乏層伸ひにはほとんど影響を与えず、耐圧的に
は従来通りの設計となっている。FIG. 1 is a longitudinal sectional view of a first embodiment of the invention. 1st
The DMO8FET in the figure shows a high concentration drain layer 1, a well part 3 formed in the low concentration drain layer 2, a medium concentration diffusion layer 4 for the drain, which is a feature of the present invention, a base layer 5, a source layer 6, and an insulating film layer 7. It consists of a polycrystalline silicon gate electrode layer 8 provided therebetween and a lease electrode layer 9 connected to the lease layer 6. With this structure, the RDS (
Junction FET m among the components of
In order to keep the resistance 12 of the region low, a medium concentration drain layer 4 with a concentration several times that of the low concentration drain layer is provided around the base layer using the gate electrode layer as a shielding film by self-alignment. At the same time as lowering the
It is possible to suppress the depletion layer wave to the conductive part of ET and to keep the resistance low. In addition, this layer is separated from the base layer only by the difference in diffusion depth due to self-alignment, so it is extremely thin, and the concentration is also suppressed several times, so it has little effect on depletion layer expansion during reverse bias. The design is the same as before in terms of pressure resistance.
第２図は本発明の第２の実施例の縦断面図である。図中
の番号はすべて第１図と共通でありこの実施例では高融
点金属ゲート電極の構成である。FIG. 2 is a longitudinal sectional view of a second embodiment of the invention. All the numbers in the figure are the same as in FIG. 1, and this embodiment has a structure of a high melting point metal gate electrode.
即ち本実施例は、ゲート電極としてポリシリコンと高融
点金属とを用いているため、ゲート抵抗が低くなり、高
速化がはかれる。That is, in this embodiment, since polysilicon and a high melting point metal are used as the gate electrode, the gate resistance is lowered and the speed is increased.
以上説明した様に本発明は、ベース層の外側に中濃度ド
レイン層をベース層と自己整合的に設ける事により、耐
圧特性に全く影響を与える事なく、ＤＭＯＳＦＥＴのＲ
ｏｓ（ｏｎ）特性が改善できろ効果がある。As explained above, the present invention provides the R
It is effective if the OS (on) characteristics can be improved.
第１図は本発明の第１の実施例によるＤ Ｍ Ｏ５ＦＥ
Ｔの縦断面図、第２図は本発明の第２の実施例の縦断面
図、第３図は従来のＤＭＯＳＦＥＴ の縦断面図、第
４図ｉａｌは従来のＤＭＯＳＦＥＴのＲＤＳ（ｏｎ）を
その構成要素に分けた模式図、第４図（ｂ）は本発明に
よるＤＭＯＳＦＥＴのＲＤｓ（ｏｎ）をその構成要素に
分けた模式図である。
１・・・・・・ドレイン高濃度層、２・・・・・・ドレ
イン低濃度層、３・・・・・・ウェル部、４・・・・・
・ドレイン中濃度層、５・・・・・ベース／＆、６・・
・・・・ソース層、７・・・・・・絶縁膜層、８・・・
・・・多結晶シリコンゲート電極層、９・・・・・・ソ
ース電極層、１０・・・・・・高融点金属ゲート電極層
、１１・・・・・・チャネル抵抗、１２・・・・・・ジ
ャンクションＦＥＴ抵抗、１３・・・・・・ドレイン低
濃度層抵抗、１４・・・・・・ドレイン高濃度層抵抗。
代理人 弁理士 内 原 晋
躬３図FIG. 1 shows a D M O5FE according to a first embodiment of the present invention.
2 is a vertical sectional view of the second embodiment of the present invention, FIG. 3 is a vertical sectional view of a conventional DMOSFET, and FIG. 4 ial is a vertical sectional view of the conventional DMOSFET. FIG. 4(b) is a schematic diagram dividing the RDs(on) of the DMOSFET according to the present invention into its components. 1... Drain high concentration layer, 2... Drain low concentration layer, 3... Well part, 4...
・Drain medium concentration layer, 5...Base/&, 6...
...Source layer, 7...Insulating film layer, 8...
... Polycrystalline silicon gate electrode layer, 9 ... Source electrode layer, 10 ... High melting point metal gate electrode layer, 11 ... Channel resistance, 12 ... ... Junction FET resistance, 13 ... Drain low concentration layer resistance, 14 ... Drain high concentration layer resistance. Agent Patent Attorney Shinman Uchihara 3rd figure
Claims (1)
的に設けられたゲート電極を遮蔽膜としてベース層とソ
ース層とを形成した自己整合形２重拡散型縦形電界効果
トランジスタにおいて、ベース層を囲む様にドレイン層
と同一導電型で、かつ、ドレイン層より不純物濃度の高
い拡散層が形成されている事を特徴とした縦形電界効果
トランジスタ。In a self-aligned double diffused vertical field effect transistor in which a base layer and a source layer are formed using a gate electrode selectively provided on one principal surface of a first conductivity type semiconductor substrate via an insulating film as a shielding film. A vertical field effect transistor characterized in that a diffusion layer having the same conductivity type as the drain layer and having a higher impurity concentration than the drain layer is formed surrounding the base layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61143397A JPS62299085A (en) | 1986-06-18 | 1986-06-18 | Vertical field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61143397A JPS62299085A (en) | 1986-06-18 | 1986-06-18 | Vertical field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62299085A true JPS62299085A (en) | 1987-12-26 |
Family
ID=15337814
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61143397A Pending JPS62299085A (en) | 1986-06-18 | 1986-06-18 | Vertical field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62299085A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02273972A (en) * | 1989-04-15 | 1990-11-08 | Matsushita Electron Corp | Vertical type mos field effect transistor |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57109376A (en) * | 1980-08-18 | 1982-07-07 | Int Rectifier Corp | High power mosfet |
| JPS62115873A (en) * | 1985-11-15 | 1987-05-27 | Matsushita Electronics Corp | Vertical mos field effect transistor |
-
1986
- 1986-06-18 JP JP61143397A patent/JPS62299085A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57109376A (en) * | 1980-08-18 | 1982-07-07 | Int Rectifier Corp | High power mosfet |
| JPS62115873A (en) * | 1985-11-15 | 1987-05-27 | Matsushita Electronics Corp | Vertical mos field effect transistor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02273972A (en) * | 1989-04-15 | 1990-11-08 | Matsushita Electron Corp | Vertical type mos field effect transistor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5057884A (en) | Semiconductor device having a structure which makes parasitic transistor hard to operate | |
| JPH0330310B2 (en) | ||
| JPH0621468A (en) | Insulated gate semiconductor device | |
| KR20000051294A (en) | DMOS field effect transistor with improved electrical characteristics and fabricating method thereof | |
| JPH0513387B2 (en) | ||
| JP3257358B2 (en) | Field effect type semiconductor device | |
| JPH0456473B2 (en) | ||
| JPS6159666B2 (en) | ||
| JPS62299085A (en) | Vertical field-effect transistor | |
| JPH07135307A (en) | Semiconductor device | |
| JP2730088B2 (en) | High voltage semiconductor device | |
| JP3137840B2 (en) | Semiconductor device | |
| JPS626352B2 (en) | ||
| JPH0349266A (en) | Mos-type semiconductor device | |
| JPH051083Y2 (en) | ||
| JPH0428149B2 (en) | ||
| JPS63254769A (en) | Vertical insulated-gate type field effect transistor | |
| JPH09205201A (en) | Horizontal type mosfet | |
| JPS61172371A (en) | Semiconductor device | |
| JPS60107866A (en) | Semiconductor device | |
| JPS6258683A (en) | Field effect transistor | |
| JPH03171774A (en) | High withstand voltage planar element | |
| JP3074065B2 (en) | Lateral MOS field effect transistor | |
| JPS62159468A (en) | Semiconductor device | |
| JPS5931224B2 (en) | semiconductor equipment |