JPS62298209A - Automatic gain control amplifier - Google Patents

Automatic gain control amplifier

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Publication number
JPS62298209A
JPS62298209A JP14002186A JP14002186A JPS62298209A JP S62298209 A JPS62298209 A JP S62298209A JP 14002186 A JP14002186 A JP 14002186A JP 14002186 A JP14002186 A JP 14002186A JP S62298209 A JPS62298209 A JP S62298209A
Authority
JP
Japan
Prior art keywords
current
circuit
pair
constant
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14002186A
Other languages
Japanese (ja)
Other versions
JPH0628325B2 (en
Inventor
Kazuaki Hori
和明 堀
Isao Akitake
秋武 勇夫
Ichiro Osaka
一朗 大坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14002186A priority Critical patent/JPH0628325B2/en
Publication of JPS62298209A publication Critical patent/JPS62298209A/en
Publication of JPH0628325B2 publication Critical patent/JPH0628325B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To attain the low power voltage by supplying a current to a connecting point of emitters of a differential pair and a connecting point of emitters of a transistor pair and varying the current ratio flowing thereto respectively according to a control signal. CONSTITUTION:Currents Ie3, Ie4 flowing to the differential pair 151 of a differential amplifier 15 and a transistor pair 161 of a current shunt circuit 16 are controlled by making currents Ie1, Ie2 of current sources 5, 6 constant and giving control currents Ic1, Ic2 from a control circuit 17 to constant current sources 5, 6 so as to increase/decrease the currents Ie3, Ie4 flowing to the differential pair 151 of the differential amplifier 15 and to the TR pair 161 of the circuit 16. It is required to change the current ratio of a current of the differential amplifier 15 to that of the circuit 16 in this case while keeping the current sum flowing to load resistors 9, 10 in order to prevent a DC level of an output signal from being changed. Thus, the control circuit 17 controls the current of the circuit 16 to keep the sum of the currents flowing to the load resistors 9, 10 constant.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は自動利得制御増幅器に関し、特に低電圧電源で
の動作に好適な自動利得制御増幅器(AuωGa1n 
Contro1回路、以下、 A、  G、 C回路と
略す〕に関するものである。
Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an automatic gain control amplifier, and in particular to an automatic gain control amplifier (AuωGa1n) suitable for operation with a low voltage power supply.
This relates to the Control 1 circuit (hereinafter abbreviated as A, G, and C circuits).

〔従来の技術」 従来の装置は、アナログ集積回路(近代科学社、中沢修
治、佐々木元、村瀬清隆訳、1975年)第283頁か
ら第287頁に記載されているように。
[Prior Art] The conventional device is as described in Analog Integrated Circuits (Kinda Kagakusha, translated by Shuji Nakazawa, Hajime Sasaki, and Kiyotaka Murase, 1975), pages 283 to 287.

定電流源が一段、トランジスタが二段、そして負荷抵抗
と、いう具合に縦に積み重ねられていた。
One stage of constant current sources, two stages of transistors, and a load resistor were stacked vertically.

このためトランジスタ一対の差動増幅器(差動アンプ)
に比ベトランシスタ一段分高い電源電圧が必要であった
For this reason, a differential amplifier with a pair of transistors (differential amplifier)
This required a power supply voltage that was one stage higher than that of the transistor.

そのことを第3図を用いて詳しく説明をする。This will be explained in detail using FIG.

第3図は従来のAGC回路の一例を示す回路図である。FIG. 3 is a circuit diagram showing an example of a conventional AGC circuit.

従来のAGC回路は、差動アンプ15の差動対151と
分流回路16のトランジスタ対161が並列に接続され
、制御回路17は、差動アンプ15の差動対151と分
流回路16のトランジスタ対161とそれぞれ直列に接
続されている。
In the conventional AGC circuit, the differential pair 151 of the differential amplifier 15 and the transistor pair 161 of the shunt circuit 16 are connected in parallel, and the control circuit 17 connects the differential pair 151 of the differential amplifier 15 and the transistor pair of the shunt circuit 16 in parallel. 161 and are connected in series.

差動アンプ15は、入力信号が差動対151のペース間
に入力されると、増幅して差動対151のコレクタ間に
出力する。また、分流回路16は、負荷抵抗9.10の
両者からそれぞれ等しく電流を引き出す。
When an input signal is input between the paces of the differential pair 151, the differential amplifier 15 amplifies the signal and outputs the amplified signal between the collectors of the differential pair 151. Further, the shunt circuit 16 draws current equally from both load resistors 9 and 10, respectively.

制御回路17は、トランジスタ21と22で差動対を構
成し、定電流源12で差動アンプ15の差動対151と
分流回路16のトランジスタ対161に流れる電流1e
s、IO2の和を一定に保ったまま、AGC制御信号に
従って、前記差動対で電流1es 。
The control circuit 17 includes transistors 21 and 22 that form a differential pair, and a constant current source 12 that controls current 1e flowing through the differential pair 151 of the differential amplifier 15 and the transistor pair 161 of the shunt circuit 16.
The current 1 es in the differential pair according to the AGC control signal while keeping the sum of s and IO2 constant.

工e4の比を制御する。これによシ、差動アンプ15の
利得が制御される。
Control the ratio of E4. This controls the gain of the differential amplifier 15.

以上のように従来のAGC回路は制御回路17が差動ア
ンプ15と分流回路16に直例に接続され高い電源電圧
が必要であった。
As described above, in the conventional AGC circuit, the control circuit 17 is directly connected to the differential amplifier 15 and the shunt circuit 16, and a high power supply voltage is required.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来技術では、1対の差動アンプに流れる電流を制
御するためにさらに1段、差動対を縦続に接続している
。このため、1対の差動アンプのみの場合に比べ、トラ
ンジスタ1段分電源電圧を高く取る必要がある。このた
めLSIの微細化が進むと、素子の耐圧が低くなるため
電源電圧を高く取れなくな)、高電源電圧を要する回路
を内装することができなくなったり、ダイナミックレン
ジが取れなくなるという問題があった。
In the above-mentioned prior art, one more stage of differential pairs is connected in cascade to control the current flowing through the pair of differential amplifiers. Therefore, it is necessary to increase the power supply voltage by one stage of transistors compared to the case where only one pair of differential amplifiers are used. For this reason, as LSI miniaturization progresses, the withstand voltage of the elements decreases, making it impossible to obtain a high power supply voltage), making it impossible to incorporate circuitry that requires a high power supply voltage, and causing problems such as not being able to maintain a dynamic range. Ta.

本発明の目的は、上記した従来技術の問題点を解決し、
低電源電圧化を図った自動利得制御増幅器を提供するこ
とにある。
The purpose of the present invention is to solve the problems of the prior art described above,
An object of the present invention is to provide an automatic gain control amplifier that achieves low power supply voltage.

〔問題点を解決するための手段〕[Means for solving problems]

上記目的を達成する為に、本発明では、自動利得制御増
幅器を、 第1のトランジスタと第2のトランジスタの差動対(以
下、単に差動対という)から成り、該第1及び第2のト
ランジスタの各コレクタをそれぞれ第1と第2の抵抗を
弁して第1の定電圧源に接続すると共に、該第1及び第
2のトランジスタの各エミッタ同士を接続し第1の定電
流源を介し接地することによシ構成した差動アンプと、
第3のトランジスタと第4のトランジスタのトランジス
タ対(以下、単にトランジスタ対という)から成り、該
第3及び第4のトランジスタの各コレクタをそれぞれ前
記第1及び第2のトランジスタの各コレクタに接続し、
更に、前記第3及び第4のトランジスタの各エミッタ同
士を接続し第2の定電流源を介して接地すると共に、該
第3及び第4のトランジスタのベース同士を相互に第2
の定電圧源によシバイアスすることKより構成した分流
回路と、 前記第1の定電圧源に接続されていて、前記差動対のエ
ミッタ同士の接続点及び前記トランジスタ対のエミッタ
同士の接続点に電流をそれぞれ供給し、前記第1の定電
圧源から前記第1及び第2の抵抗を経てそれぞれ流れる
電流の和を一定に保ったまま前記差動対とトランジスタ
対にそれぞれ流れる電流比を制御信号に従って可変する
ことのできる電流源をMした制御回路と、から成るよう
にした。
In order to achieve the above object, the present invention provides an automatic gain control amplifier that includes a differential pair of a first transistor and a second transistor (hereinafter simply referred to as a differential pair). Each collector of the transistor is connected to a first constant voltage source through a first and second resistor, and the emitters of the first and second transistors are connected to each other to connect a first constant current source. A differential amplifier constructed by grounding through the
It consists of a transistor pair of a third transistor and a fourth transistor (hereinafter simply referred to as a transistor pair), and the collectors of the third and fourth transistors are connected to the collectors of the first and second transistors, respectively. ,
Further, the emitters of the third and fourth transistors are connected to each other and grounded via a second constant current source, and the bases of the third and fourth transistors are connected to each other by a second constant current source.
a shunt circuit configured from a constant voltage source K, connected to the first constant voltage source, and connected to a connection point between the emitters of the differential pair and a connection point between the emitters of the transistor pair; and controlling the ratio of currents flowing through each of the differential pair and the transistor pair while keeping the sum of the currents flowing from the first constant voltage source through the first and second resistors constant. The control circuit includes a current source that can be varied according to a signal.

〔作用〕 制御回路は、制御回路内に設けられた、第1の定電圧源
である電源に接続されている電流源によって、差動アン
プの差動対のエミッタ接続点と分’IM Do Mのト
ランジスタ対のエミッタ接続点に、制御信号に従って電
流を供給することによシ、第1の定電圧源から第1及び
第2の抵抗を経てそれぞれ流れる電流の和を一定に保っ
たまま前記差動対とトランジスタ対にそれぞれ流れる電
流比を可変する。
[Function] The control circuit uses a current source connected to a power source, which is a first constant voltage source, provided in the control circuit to connect the emitter connection point of the differential pair of the differential amplifier to the minute point. By supplying current to the emitter connection point of the pair of transistors according to the control signal, the difference between the currents is maintained constant while the sum of the currents flowing from the first constant voltage source through the first and second resistors is kept constant. The ratio of current flowing through the dynamic pair and the transistor pair is varied.

この様に、この制御回路は差動アンプまたは分流回路に
直列に接続されておらず、しかも十分な利得制御を行う
ことができるので、AGC回路は高い電源電圧を必要と
しない。
In this way, this control circuit is not connected in series with a differential amplifier or a shunt circuit and can perform sufficient gain control, so the AGC circuit does not require a high power supply voltage.

〔実施例〕〔Example〕

以下、本発明の一実施例を第1図によシ説明する0 第1図のAGC回路は、差動アンプ15と分流回路16
と制御回路17とから成る。
Hereinafter, one embodiment of the present invention will be explained with reference to FIG. 1. The AGC circuit shown in FIG.
and a control circuit 17.

制御回路17は、AGC制御信号により差動アンプ15
の差動対151に流れる電流工e3を増減させ、さらに
、負荷抵抗9,10に流す電流を一部分担する分流回路
16のトランジスタ対へのt流工eaを制御する。
The control circuit 17 controls the differential amplifier 15 according to the AGC control signal.
It increases or decreases the current e3 flowing through the differential pair 151, and further controls the current ea flowing to the transistor pair of the shunt circuit 16 that partially shares the current flowing through the load resistors 9 and 10.

即ち、差動アンプ15の差動対151と分流回路16の
トランジスタ対161に流れる電流Ie3とIC4の制
御は、電流源5と6のtiIθ1とIezを一定にして
おき、制御回路17からの制御電流ICI+IC2を定
電流源5,6に流すことで差動アンプ15の差動対15
1と分流回路16のトランジスタ対161に流れる電流
xesとb14を増減する。以上の電流の関係を以下に
示す。
That is, the currents Ie3 and IC4 flowing through the differential pair 151 of the differential amplifier 15 and the transistor pair 161 of the shunt circuit 16 are controlled by keeping tiIθ1 and Iez of the current sources 5 and 6 constant, and by controlling from the control circuit 17. By flowing the current ICI+IC2 to the constant current sources 5 and 6, the differential pair 15 of the differential amplifier 15
1 and the currents xes and b14 flowing through the transistor pair 161 of the shunt circuit 16 are increased or decreased. The relationship between the above currents is shown below.

Ies = I8N −Ic。Ies = I8N - Ic.

IC4= Iez−IC2ここで工el 、 I62は
一定この時、出力信号のDCレベルが変化しないように
するために、負荷抵抗9と10に流れる電流の和を一定
に保ったまま差動アンプ15と分流回路16の電流比を
変える必要がある。従って、制御回路17は負荷抵抗9
.10に流れる電流の和を一定に保つように分流回路1
6の電流を制御する。即ち、 IC+ + IC2= C=一定 の条件を有する。この結果、負荷抵抗9.10に流れる
電流tutは一定となる。この関係を以下に示す。
IC4=Iez-IC2 Here, I62 is constant At this time, in order to prevent the DC level of the output signal from changing, the differential amplifier 15 is It is necessary to change the current ratio of the shunt circuit 16 and the current ratio of the shunt circuit 16. Therefore, the control circuit 17 has a load resistance 9
.. The shunt circuit 1
6 current is controlled. That is, IC+ + IC2=C=has a certain condition. As a result, the current tut flowing through the load resistor 9.10 becomes constant. This relationship is shown below.

IR? = IC3+ IC4 =Ie+−Ic+ + IC2−IC2” Ie++I
ez−1c+ −C+ ICI= Ie+ + I82
− C=一定 第1図における制御回路17の一具体例を第2図によシ
説明する。
IR? = IC3+ IC4 =Ie+-Ic+ + IC2-IC2" Ie++I
ez-1c+ -C+ ICI= Ie+ + I82
- C=constant A specific example of the control circuit 17 in FIG. 1 will be explained with reference to FIG.

この回路はPNP トランジスタ33〜36、NPNI
−ランジスタロ7〜40、抵抗41〜44、定電流源6
1と62、定電圧源46、そして電圧源45から成や、
第2図に示したように接続される。
This circuit consists of PNP transistors 33-36, NPNI
- Ranjistaro 7 to 40, resistor 41 to 44, constant current source 6
1 and 62, a constant voltage source 46, and a voltage source 45,
The connections are made as shown in FIG.

電圧源45はACC制御信号によ)制御されておシ、ま
た、トランジスタ66と54.55と56はそれぞれ差
動対を構成し、各PNPトランジスタ56〜56のコレ
クタはそれぞれNPNトランジスタ37〜40のコレク
タに接続され、トランジスタ63と34、また35と6
6のエミッタは共通に接続され、それぞれ電流源31と
32を介して電源■。0に接続している。さらにトラン
ジスタ66と36のベースは共通に接続され電圧源45
のプラス側に、そしてトランジス、!234と35のペ
ースは共通に接続され電圧源45のマイナス側にそれぞ
れ接続されている。そして、AGC制御信号によ)差動
対に電流差l\Ieを生じさせる。さらにトランジスタ
37〜40のエミッタは抵抗41〜44を介して接地さ
れ、トランジスタ37.38と抵抗41.42とでカレ
ントミラー回路を構成し、トランジスタ38と37のエ
ミッタに流れる電流L57とIsaが同じになるように
設定される。同様にトランジスタ39.38と抵抗39
.40でカレントミラー回路を構成しトランジスタ39
と38のエミッタに流れるt流I39と■40が等しく
なるように設定する。
Voltage source 45 is controlled by an ACC control signal), and transistors 66 and 54, 55 and 56 each constitute a differential pair, and the collector of each PNP transistor 56-56 is connected to the NPN transistor 37-40, respectively. transistors 63 and 34 as well as 35 and 6
The emitters of 6 are commonly connected to the power supply ■ through current sources 31 and 32, respectively. Connected to 0. Further, the bases of transistors 66 and 36 are connected in common to voltage source 45.
On the positive side of, and transis,! The paces 234 and 35 are connected in common and connected to the negative side of the voltage source 45, respectively. Then, a current difference l\Ie is generated in the differential pair (by the AGC control signal). Furthermore, the emitters of transistors 37 to 40 are grounded via resistors 41 to 44, and transistors 37.38 and resistors 41.42 form a current mirror circuit, so that currents L57 and Isa flowing through the emitters of transistors 38 and 37 are the same. is set to be. Similarly, transistor 39.38 and resistor 39
.. 40 constitutes a current mirror circuit, and the transistor 39
The t currents I39 flowing to the emitters of and 38 are set so that they are equal to 40.

今、AGC制御信号により電圧源45の電圧が増加した
ことでトランジスタ64のコレクタ電流IS4が△1.
変化したとすると、トランジスタ53のコレクタ電流I
33 とトランジスタ37.38のエミッタ電流l37
1148は、定を流源31の電流を工esとして、 Iss ” Ies/ 2  +Δ1゜Isy ” L
m = Ies/ 2−Δ1゜となる。この結果、制御
l路17の出力を流に1はIc+ = I33− h7
 = 2 ・ΔI。
Now, as the voltage of the voltage source 45 increases due to the AGC control signal, the collector current IS4 of the transistor 64 increases by △1.
If the collector current I of the transistor 53 changes
33 and emitter current l37 of transistor 37.38
1148 is Iss ``Ies/2 + Δ1゜Isy ''L, where the current of the current source 31 is es.
m = Ies/2-Δ1°. As a result, 1 based on the output of the control l path 17 is Ic+ = I33- h7
= 2 ・ΔI.

であるo同様にトランジスタ55.56のルクタ電流工
55* ”54 とトランジスタ39.40のエミッタ
電流11?l I4゜はIsaの変化分を八I2、定電
流源32の電流をIC4とすると、 I3A″工ao = I39 = Iθ6/2 +Δl
2bs= Iea/z−Δ12 となジ、制御回路17の出力電流IC2はIc2 = 
bs −I3. = −2・ΔI2となる。ここでI6
s ” IC6とすると電圧源45の電圧変化による電
流変化Δ工1とへ12は等しくなるため、 Ic+ + IC2= 2八1.−2へl2=0第1図
の回路において制御回路17の出力電流Ic+とIC2
の栄件 Ic+ + IC2=一定 を満足する。
oSimilarly, if the current of the transistor 55.56 is 55* "54 and the emitter current of the transistor 39.40 is 11?l I4°, the change in Isa is 8I2, and the current of the constant current source 32 is IC4. I3A″work ao = I39 = Iθ6/2 +Δl
2bs=Iea/z-Δ12, and the output current IC2 of the control circuit 17 is Ic2=
bs-I3. = −2・ΔI2. Here I6
s ” If IC6, the current change due to the voltage change of the voltage source 45 ∆ 1 and 12 will be equal, so Ic+ + IC2 = 28 1.-2 to l2 = 0 In the circuit of Fig. 1, the output of the control circuit 17 Current Ic+ and IC2
Satisfies the condition Ic+ + IC2 = constant.

本実施例によれば、AGC回路の制御回路17を差動ア
ンプ15と分流回路16に対し直列に接続していないの
で、を源電圧v0゜は低くすることができるC 〔発明の効果〕 本発明によれは、AGC回路の低を源亀圧化ができるの
で、耐圧が低いLSIにも実装することが可能となシ、
まfc、低電源電圧下においても従来と同等の動作を行
い、かつ十分なダイナミックレンジが得られるAGC回
路を実現できる。
According to this embodiment, since the control circuit 17 of the AGC circuit is not connected in series with the differential amplifier 15 and the shunt circuit 16, the source voltage v0 can be lowered. According to the invention, since the low voltage of the AGC circuit can be made into a source voltage, it is possible to implement it even in LSI with low breakdown voltage.
Furthermore, it is possible to realize an AGC circuit that operates in the same manner as the conventional one even under a low power supply voltage and can obtain a sufficient dynamic range.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す回路図、第2図は第1
図における制御回路の一具体例を示した回路図、第3図
はAGC回路の従来例を示す回路図、である。 1〜4,21,22.37〜40・・・NPN トラン
ジスタ、33〜36・・・PNP トランジスタ、5,
6゜12.13.31.52・・・定電流源、7.8・
・・電流源、It、24.46・・・定電圧源、23.
45・・・電圧源、9.10.37〜44・・・抵抗。
Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 3 is a circuit diagram showing a specific example of the control circuit shown in the figure, and FIG. 3 is a circuit diagram showing a conventional example of an AGC circuit. 1 to 4, 21, 22. 37 to 40...NPN transistor, 33 to 36...PNP transistor, 5,
6゜12.13.31.52... Constant current source, 7.8.
...Current source, It, 24.46... Constant voltage source, 23.
45...Voltage source, 9.10.37-44...Resistance.

Claims (1)

【特許請求の範囲】 1、第1のトランジスタと第2のトランジスタの差動対
(以下、単に差動対という)から成り、該第1及び第2
のトランジスタの各コレクタをそれぞれ第1と第2の抵
抗を介して第1の定電圧源に接続すると共に、該第1及
び第2のトランジスタの各エミッタ同士を接続し第1の
定電流源を介し接地することにより構成した差動アンプ
と、 第3のトランジスタと第4のトランジスタのトランジス
タ対(以下、単にトランジスタ対という)から成り、該
第3及び第4のトランジスタの各コレクタをそれぞれ前
記第1及び第2のトランジスタの各コレクタに接続し、
更に、前記第3及び第4のトランジスタの各エミッタ同
士を接続し第2の定電流源を介して接地すると共に、該
第3及び第4のトランジスタのベース同士を相互に第2
の定電圧源によりバイアスすることにより構成した分流
回路と、 前記第1の定電圧源に接続されていて、前記差動対のエ
ミッタ同士の接続点及び前記トランジスタ対のエミッタ
同士の接続点に電流をそれぞれ供給し、前記第1の定電
圧源から前記第1及び第2の抵抗を経てそれぞれ流れる
電流の和を一定に保ったまま前記差動対とトランジスタ
対にそれぞれ流れる電流比を制御信号に従って可変する
ことのできる電流源を有した制御回路と、 から成ることを特徴とする自動利得制御増幅器。
[Claims] 1. Consisting of a differential pair of a first transistor and a second transistor (hereinafter simply referred to as a differential pair);
The collectors of the transistors are connected to a first constant voltage source via first and second resistors, and the emitters of the first and second transistors are connected to each other to connect a first constant current source. It consists of a differential amplifier constructed by grounding through connected to each collector of the first and second transistors;
Further, the emitters of the third and fourth transistors are connected to each other and grounded via a second constant current source, and the bases of the third and fourth transistors are connected to each other by a second constant current source.
a shunt circuit configured by being biased by a constant voltage source; and controlling the ratio of currents flowing through the differential pair and the transistor pair in accordance with a control signal while keeping the sum of the currents flowing from the first constant voltage source through the first and second resistors constant. An automatic gain control amplifier comprising: a control circuit having a variable current source;
JP14002186A 1986-06-18 1986-06-18 Automatic gain control amplifier Expired - Lifetime JPH0628325B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14002186A JPH0628325B2 (en) 1986-06-18 1986-06-18 Automatic gain control amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14002186A JPH0628325B2 (en) 1986-06-18 1986-06-18 Automatic gain control amplifier

Publications (2)

Publication Number Publication Date
JPS62298209A true JPS62298209A (en) 1987-12-25
JPH0628325B2 JPH0628325B2 (en) 1994-04-13

Family

ID=15259096

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14002186A Expired - Lifetime JPH0628325B2 (en) 1986-06-18 1986-06-18 Automatic gain control amplifier

Country Status (1)

Country Link
JP (1) JPH0628325B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63292712A (en) * 1987-05-25 1988-11-30 Nippon Telegr & Teleph Corp <Ntt> Variable gain type differential amplifier circuit
JPH01317011A (en) * 1988-06-17 1989-12-21 Sony Corp Gain control amplifier

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63292712A (en) * 1987-05-25 1988-11-30 Nippon Telegr & Teleph Corp <Ntt> Variable gain type differential amplifier circuit
JPH01317011A (en) * 1988-06-17 1989-12-21 Sony Corp Gain control amplifier

Also Published As

Publication number Publication date
JPH0628325B2 (en) 1994-04-13

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