JPS62296617A - Semiconductor relay circuit - Google Patents

Abstract

PURPOSE:To decrease the chip area by using a voltage drop across a resistor by an electromotive force of a photovoltaic diode array so as to switch a normally-ON type drive transistor (TR) into the OFF-state. CONSTITUTION:The titled circuit consists of a light emitting element 1 generating an optical signal in response to an input signal, the photovoltaic diode array 2 generating an electromotive force by the optical signal, and a power MOSFET 3 receiving the electromotive force between the gate and the substrate thereby changing its state from the 1st impedance state into the 2nd impedance state to constitute a closed circuit in which the electromotive force caused between positive and negative electrodes of the array 2 is fed between the gate and the base of the FET 3 via a resistor 4. Further, the normally-ON type drive TR 5 is provided, in which the drain and source are connected to the gate and the base of the FET 3 and which is biased by a voltage drop caused across the resistor 4. Thus, the rapid charging circuit for the FET 3 is driven by the array 2 only and the chip area is decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION 3. Detailed Description of the Invention (Technical Field) The present invention relates to a semiconductor relay circuit, and more particularly to a semiconductor relay circuit that utilizes isolation through optical coupling.

(Background Art) Conventionally, a semiconductor relay circuit as shown in FIG. 3(a), which combines a photocoupler with MO, SF, and ET, has been proposed. In this conventional example, a light emitting diode] is connected to the relay input terminal 7-7', and a photovoltaic diode array 2 is provided which receives the optical signal from the light emitting diode 1 and generates an electric signal. , which constitutes a so-called photocoupler. The voltage generated in the photovoltaic diode array 2 is applied between the gate and source of the output MOSFET 3, making the MO3FET 3 conductive. This establishes continuity between relay output terminals 8 and 8'. Next, when the input voltage between the relay input terminals 7 and 7' is removed and the optical signal from the light emitting diode 1 disappears,
The photovoltaic diode array 2 stops generating electrical signals. Since the resistor 6 is connected in parallel to the photovoltaic diode array 2, the charge of the photovoltaic diode array 2 is discharged through the resistor 6. Similarly, M for output
The accumulated charge between the gate and source of O3FET3 is also connected to resistor 6.
is discharged through. By this, MO3F for output
ET3 becomes non-conductive, and relay output terminals 8-8' are cut off.

In this conventional example, the current generated in the photovoltaic diode array 2 during the light emitting operation of the light emitting diode 1 charges between the gate and source of the output MOSFET 3 and
SFET 3 is brought into conduction, but since the discharging resistor 6 is connected, not all of the current is used for charging between the gate and source, and current is also shunted to the discharging resistor 6. be done. Therefore, the rise of the gate voltage of MOSFET 3 is delayed. The resistor 6 is used to discharge the accumulated charge in the photovoltaic diode array 2 and the accumulated charge between the gate and source of the MOSFET 3 after the light emitting diode 1 stops emitting light, and is used to discharge the accumulated charge in the photovoltaic diode array 2 and the accumulated charge between the gate and source of the MOSFET 3.
It has the role of promoting the drop in the gate voltage of No. 3. Therefore, if the resistance value of the resistor 6 is high, the gate voltage rises quickly and falls slowly. On the other hand, if the resistance value of the resistor 6 is low, the gate voltage rises slowly and falls quickly. To speed up both the rise and fall of the gate voltage, use resistor 6.
It is necessary that the resistance value is high (preferably infinite) when the gate voltage rises, and low resistance (preferably 0) when the gate voltage falls.

The conventional circuit shown in FIG. 3(b) uses a depletion type (normally-on type) JFET 5a to achieve the above-mentioned conditions. In this circuit, a light signal from a light emitting diode 1 is simultaneously applied to first and second photovoltaic diode arrays 2 and 9. The light emitting diode 1 performs a light emitting operation, and the first
When the photovoltaic diode array 2 generates an electric signal, the second photovoltaic diode array 9 also generates an electric signal, thereby increasing the gate-source voltage of the depletion type JPET 5a. rises. When the voltage generated by the second photovoltaic diode array 9 exceeds the threshold voltage of J F E T 5 a, J F E T 5 a becomes non-conductive, and a high resistance is formed between the gate and source of the output MOSFET 3. state. Therefore, the gate and source of the MOSFET 3 are quickly charged by the current generated by the first photovoltaic diode array 2.

Next, when the light emitting diode 1 stops emitting light, the first
and the second photovoltaic diode array 2.9 stops generating electrical signals. Second photovoltaic diode array 9
Since the resistor 10 for discharging is connected in parallel,
The accumulated charge is quickly discharged. Therefore, the depletion type JF ET 5 a becomes conductive in a non-biased state.

Therefore, the charges accumulated between the gate and source of the output Mo5t''F, T3, and the accumulated charges of the first photovoltaic diode array 2 are discharged via the J PET 5a. This allows the output MOSFET3
MO3FET for output
3 switching speed can be increased. Note that the circuit including the JPET 5a, the second photovoltaic diode array 9, and the resistor 10 in the circuit of FIG.
Compared to the circuit shown in the circuit in Figure 3(a), which includes the output MOSFET 3, the photovoltaic diode array 2, and the resistor 6, it requires a smaller capacity, so its operating speed is lower than that shown in Figure 3(a).
) is faster than the circuit.

However, in the conventional example circuit of FIG. 3(b), the second
requires a photovoltaic diode array 9 of MO
There was a problem in that the chip area increased when the entire drive circuit for SFET 3 was integrated into one chip.

(Object of the Invention) The present invention has been made in view of the above-mentioned points, and its purpose is to drive a power MOSFET to open and close at high speed using a 1 series photovoltaic diode array. An object of the present invention is to provide a semiconductor relay circuit in which the chip area can be reduced.

(Disclosure of the Invention) As shown in FIGS. 1 and 2, a semiconductor relay circuit according to the present invention includes a light emitting element such as a light emitting diode 1 that generates a light signal in response to an input signal, and a light emitting element such as a light emitting diode 1 that generates a light signal in response to an input signal. A photovoltaic diode array 2 arranged so that an electromotive force is generated by a signal, and a power MOSFET 3 that changes from a first impedance state to a second impedance state by applying the electromotive force between the gate and the substrate. In a semiconductor relay circuit using optical coupling, the positive and negative electrodes of the photovoltaic diode array 2, the gate and substrate of the MOSFET 3, and the resistor 4 are configured by:
The electromotive force generated between the positive electrode and the negative electrode of the photovoltaic diode array 2 is transmitted through the resistor 4 to the MOSFET.
The MO3FE
A gate source is connected between the gate and the substrate of T3, and is connected to both ends of the resistor 4 so that the impedance between the drain and source increases due to the voltage drop generated across the resistor 4 due to the electromotive force. A normally-on drive transistor 5 is connected between the two.

In the present invention, as described above, the normally-on driving transistor 5 is switched to the OFF state by the voltage drop generated across the resistor 4 due to the electromotive force of the photovoltaic diode array 2. Therefore, MOSF for power
The rapid charging/discharging circuit between the gate and the substrate of the ET3 can be driven by only one series of photovoltaic diode array 2, and the chip area can be reduced.

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings. In the circuit of FIG. 1, a light emitting diode 1 is connected between input terminals 7 and 7°.

The photovoltaic diode array 2 is optically coupled to the light emitting diode 1 and is constructed on a dielectric isolation substrate.

When an input current flows between the input terminals 7 and 7°, the light emitting diode 1 generates an optical signal, and this optical signal generates an electromotive voltage across the photovoltaic diode array 2. This electromotive voltage is applied between the gate and substrate of the power MOSFET 3 via the resistor 4, and at the same time between the drain and source of the normally-on drive transistor 5 and the resistor 6.
flows through. Therefore, the current that charges the gate capacitance of MOSFET 3 and the current that flows through drive transistor 5 and resistor 6 flow through resistor 4 .

Therefore, the gate of the driving transistor 5 is biased to a negative voltage due to the voltage drop across the resistor 4. This bias voltage instantly puts the driving transistors into a high impedance state. Therefore, the presence of the driving transistor 5 does not delay the charging operation between the gate and the substrate of the power MOSFET 3.

When the input current is constantly flowing between the input terminals 7 and 7', a small amount of current flows through the resistor 4 through the resistor 6 or the driving transistor 5, and this causes the gate of the driving transistor 5 to is biased to a negative voltage, and the driving transistor 5 maintains a high impedance state. The driving transistor 5 is a static induction transistor (SIT).
) or field effect transistor (FET). When the drive transistor 5 is an SIT, due to its unsaturated characteristics, when a high voltage surge that causes dielectric breakdown of the gate of the power MOSFET 3 is superimposed on the gate, the drive transistor 5 enters a low impedance state. So, M
Protects the gate of OSFET3. Regarding only this function, it is better to use an SIT as the driving transistor 5 than an FET.

In order to bias the normally-on type driving transistor 5 to an off state, a negative bias voltage applied between the gate and source of the driving transistor 5 is applied to the resistor 4.
It can be adjusted by appropriately selecting the values of the resistor 6 and the resistor 6.

When the input current between the input terminals 7 and 7 is cut off, the voltage between the terminals of the photovoltaic diode array 2 rapidly drops, and the resistor 6 and the driving transistor 5 consisting of a normally-on SIT or FET are The current flowing through the resistor 4 disappears, the negative bias applied to the gate of the driving transistor 5 disappears, and the normally-on type driving transistor 5 turns on. Furthermore, MO3F'
The charge accumulated in the gate capacitance of ET3 is applied as a positive bias voltage to the gate of driving transistor 5 via photovoltaic diode array 2, and a current flows between the gate and source of driving transistor 5. this is,
It is useful for further lowering the impedance of the driving transistor 5 made of SIT or FET, and MOSFET 3
The function is to quickly discharge the charge stored between the gate and source of the device.

Since the above discharge is completed in an extremely short time, high-speed operation is possible as a semiconductor relay circuit.

When no input current flows between input terminals 7 and 7°, there is a large voltage change (d) between relay output terminals 8 and 8'.
When V/dt) is applied, the mirror current that charges the parasitic capacitance between the drain and gate of MOSFET 3 is discharged to the source of MOSFET 3 via the drive transistor 5, which is a normally-on type SIT or FET. be done. Therefore, there is no possibility of erroneous instantaneous ignition, and the driving transistor 5 also functions as a gate surge protection circuit.

In the example circuit of FIG. 1, the driving transistor 5 is an N-channel normally-on JFET, but the driving transistor 5 is a P-channel normally-on JPET. is the second
As shown in the example circuit shown in the figure, the connection may be made so that a positive bias voltage is applied to the gate of the driving transistor 5.

<Effects of the Invention> As described above, in the present invention, the positive electrode and negative electrode of the photovoltaic diode array, the gate and substrate of the MO3FET, and the resistor are connected to each other in the photovoltaic diode array. The positive electrode and the negative electrode are connected to form a closed circuit in which the electromotive force generated between the positive electrode and the negative electrode is applied between the gate and the substrate of the MCSFET via the resistor, and the drain...
The source is connected between the gate and the substrate of the MO3FET, and the train is biased across the resistor by a voltage drop generated across the resistor due to the electromotive force.
gate so that the impedance between the sources increases.
Since it is equipped with a normally-on drive transistor connected between the sources, it does not require two series of photovoltaic diode arrays as in the conventional example, but only one series of photovoltaic diode arrays. Therefore, when the MOSFET drive circuit is integrated into a single chip, the chip area is reduced and the yield is also improved, resulting in cost reduction. In addition, since the off-bias is applied to the drive transistor using a resistor, the bias voltage remains constant even when the temperature rises, compared to obtaining the bias voltage using an impedance element with negative temperature characteristics such as a diode. This has the effect that good operation is possible without deterioration of performance.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a semiconductor relay circuit according to an embodiment of the present invention, FIG. 2 is a circuit diagram of a semiconductor relay circuit according to another embodiment of the present invention, and FIG. 3(a) is a circuit diagram of a conventional example. FIG. 3(b) is a circuit diagram of another conventional example. 1 is a light emitting diode, 2 is a photovoltaic diode array,
3 is a MOSFET, 4 is a resistor, and 5 is a driving transistor.

Claims (2)

[Claims] (1) A light emitting element that generates an optical signal in response to an input signal, a photovoltaic diode array arranged so that an electromotive force is generated by the optical signal, and a photovoltaic diode array that is arranged so that the electromotive force is applied between the gate and the substrate. A semiconductor relay circuit using optical coupling configured by a power MOSFET that changes from a first impedance state to a second impedance state when The electromotive force generated between the positive electrode and the negative electrode of the photovoltaic diode array is connected to the gate and substrate of the photovoltaic diode array, and the resistor.
The MOSFE is connected to form a closed circuit such that the voltage is applied between the gate and the substrate of the MOSFE T, and the drain and source of the MOSFE
connected between the gate and substrate of T, and at both ends of the resistor,
A normally-on type driving transistor is provided whose gate and source are connected so that the impedance between the drain and source increases due to the bias caused by the voltage drop that occurs in the resistor due to the electromotive force. Characteristic semiconductor relay circuit. (2) The semiconductor relay circuit according to claim 1, wherein in the MOSFET, a second resistor forming a voltage divider together with the resistor is connected in parallel between the gate and the substrate. .