JPS62295489A - Munufacture of multilayer printed interconnection board - Google Patents

Munufacture of multilayer printed interconnection board

Info

Publication number
JPS62295489A
JPS62295489A JP61138695A JP13869586A JPS62295489A JP S62295489 A JPS62295489 A JP S62295489A JP 61138695 A JP61138695 A JP 61138695A JP 13869586 A JP13869586 A JP 13869586A JP S62295489 A JPS62295489 A JP S62295489A
Authority
JP
Japan
Prior art keywords
multilayer printed
layer material
printed wiring
inner layer
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61138695A
Other languages
Japanese (ja)
Other versions
JP2544726B2 (en
Inventor
浦口 良範
滝沢 秀夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP61138695A priority Critical patent/JP2544726B2/en
Publication of JPS62295489A publication Critical patent/JPS62295489A/en
Application granted granted Critical
Publication of JP2544726B2 publication Critical patent/JP2544726B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Laminated Bodies (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 3、発明の詳細な説明 〔技術分野〕 この発明は、多層プリント配線板の製法に関する。[Detailed description of the invention] 3. Detailed description of the invention 〔Technical field〕 The present invention relates to a method for manufacturing a multilayer printed wiring board.

〔背景技術〕[Background technology]

多層プリント配線板は、一般につぎのようにして作られ
ている。まず、少なくとも片面に電路が形成されている
とともにその電路の形成位置を知るための目印となる基
準ガイドが複数個設けられた内層材(以下、単に「内層
材」と記す)、樹脂含浸基材、外層材(金属箔または金
属箔張り板)および積層用プレートをそれぞれ所定枚、
ピンでそれぞれの間の位置決めをして重ね、積層体をつ
くる。得られた積層体を複数段重ね、成形用プレスによ
り熱圧して、硬化させ、ピンおよび積層用プレートを取
り除いて、分解し、多層プリント配線板中間品をつくる
。この後、外形を概略サイズに荒切りし、ガイドマーク
等の基準穴を利用して、打ち抜きまたは手切断を行い、
多層プリント配線板を得るようにする。
Multilayer printed wiring boards are generally manufactured as follows. First, an inner layer material (hereinafter simply referred to as "inner layer material") that has an electric path formed on at least one side and a plurality of reference guides that serve as marks for knowing the formation position of the electric path, and a resin-impregnated base material. , the outer layer material (metal foil or metal foil veneer) and the lamination plate, respectively.
Use pins to position each layer and stack them to create a laminate. The obtained laminates are stacked in multiple stages, heated and pressed using a molding press to harden them, and the pins and lamination plates are removed and disassembled to produce a multilayer printed wiring board intermediate product. After this, the outer shape is roughly cut to the approximate size, and punching or manual cutting is performed using reference holes such as guide marks.
To obtain a multilayer printed wiring board.

このように、従来の製法は、樹脂含浸基材、金属箔、内
層材をピンで位置決めして重ねることにより積層体をつ
くり、得られた積層体を複数段重ね、成形用プレスによ
り熱圧して、硬化させた後、分解することを繰り返し行
う必要があり、そのため、作業性が悪く、コストアンプ
の原因となっていた。
In this way, the conventional manufacturing method is to create a laminate by positioning and overlapping the resin-impregnated base material, metal foil, and inner layer material with pins, stacking the resulting laminate in multiple stages, and hot pressing with a molding press. However, it is necessary to repeatedly cure and then disassemble, resulting in poor workability and increased costs.

そこで、このような問題を解決するため、少なくとも片
面に電路が形成されている内層材と外層材とを含む帯状
の積層体を積層成形により連続的につくり、この積層体
を連続的に移送しながら硬化させた後、硬化後の積層体
から所定形状の多層プリント配線板を得る、いわゆる、
連続法による多層プリント配線板の製法が開発された。
Therefore, in order to solve this problem, a strip-shaped laminate including an inner layer material and an outer layer material with an electric circuit formed on at least one side is continuously produced by lamination molding, and this laminate is continuously transported. After curing, a multilayer printed wiring board of a predetermined shape is obtained from the cured laminate.
A continuous process method for manufacturing multilayer printed wiring boards has been developed.

ところが、この連続法でも、内層材の電路の形成位置を
知るための目印となる基準ガイドを複数個設けておく必
要があるが、積層体に硬化後の収縮が大きいという事情
があり、前記基準ガイド間寸法が収縮により小さくなる
という問題があった〔発明の目的〕 以上の事情に鑑みて、この発明は、硬化前と硬化後とで
、基準ガイド間寸法の狂いが少ない多層プリント配線板
を得ることができる多層プリント配線板の製法を提供す
ることを目的とする。
However, even with this continuous method, it is necessary to provide a plurality of reference guides that serve as marks for knowing the formation position of the electric circuit in the inner layer material, but there is a situation in which the laminate shrinks significantly after curing, and the above-mentioned reference guides are required. There has been a problem that the distance between the guides becomes smaller due to shrinkage. [Object of the Invention] In view of the above circumstances, the present invention provides a multilayer printed wiring board with less deviation in the standard distance between the guides before and after curing. The object of the present invention is to provide a method for manufacturing a multilayer printed wiring board that can be obtained.

〔発明の開示〕[Disclosure of the invention]

前記目的を達成するため、発明者らは、連続法について
種々検討を重ねた。その結果、成形方向(移送方向)に
対しては、テンションがかかるため、収縮が大きいが、
成形方向と交差する方向については、収縮が小さいとい
うことを見出し、この発明を完成した。
In order to achieve the above object, the inventors have repeatedly investigated various continuous methods. As a result, tension is applied in the molding direction (transfer direction), so shrinkage is large, but
The present invention was completed based on the discovery that shrinkage is small in the direction crossing the molding direction.

すなわち、この発明は、少なくとも片面に電路が形成さ
れているとともにその電路の形成位置を知るための目印
となる基準ガイドが複数個設けられた内層材と外層材と
を含む帯状の積層体を積層成形により連続的につくり、
この積層体を連続的に移送しながら硬化させた後、硬化
後の積層体から所定形状の多層プリント配線板を得るに
あたり、前記基準ガイドを成形方向に対して交差する方
向に並べて設けておくことを特徴とする多層プリント配
線板の製法をその要旨とする。
That is, the present invention provides a laminated strip-shaped laminate including an inner layer material and an outer layer material, in which an electric path is formed on at least one side, and a plurality of reference guides are provided as marks for knowing the formation position of the electric path. Made continuously by molding,
After the laminate is cured while being continuously transferred, the reference guides are arranged in a direction perpendicular to the molding direction in order to obtain a multilayer printed wiring board of a predetermined shape from the cured laminate. The gist of this paper is a method for manufacturing a multilayer printed wiring board characterized by the following.

以下に、この発明を、その一実施例をあられす図面を参
照しながら詳しく説明する。
Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

、帯状の樹脂含浸基材1,1と、帯状の金属箔(外層材
)2.2と、多数枚の内層材3・・・とを用意する。樹
脂含浸基材1は、基材に樹脂ワニスを含浸させてつくる
。基材としては、紙、ガラス布、ガラスマット、ガラス
不織布等を用いる。ガラス布等を用いる場合は、あらか
じめアクリルシラン等により表面処理が施されているも
のを用いるようにするとよい。樹脂ワニスとしては、普
通、不飽和ポリエステル樹脂、ジアリルフタレート樹脂
、ビニルエステル樹脂等の不飽和結合を有する不飽和樹
脂をビニルモノマー(架橋剤)などで希釈し、さらに重
合開始剤を加えてつくったものが用いられる。金属箔と
しては、銅箔やアルミニウム箔等を用いる。内層材3は
、第2図にみるように、その少なくとも片面(この実施
例では、両面)に電路5が形成されているとともに、そ
の電路の形成位置を知るための目印となる基準ガイド2
0が2個、幅方向に並べられて設けられている。また、
この内層材3は、樹脂含浸基材1および金属箔2より幅
が広くなっていて、そのはみ出し部分の3個所に穴4が
設けられている。
, strip-shaped resin-impregnated base materials 1, 1, strip-shaped metal foils (outer layer material) 2.2, and a large number of inner layer materials 3... are prepared. The resin-impregnated base material 1 is made by impregnating a base material with a resin varnish. As the base material, paper, glass cloth, glass mat, glass nonwoven fabric, etc. are used. When using glass cloth or the like, it is preferable to use one whose surface has been previously treated with acrylic silane or the like. Resin varnishes are usually made by diluting unsaturated resins with unsaturated bonds, such as unsaturated polyester resins, diallyl phthalate resins, and vinyl ester resins, with vinyl monomers (crosslinking agents), and then adding polymerization initiators. things are used. As the metal foil, copper foil, aluminum foil, etc. are used. As shown in FIG. 2, the inner layer material 3 has an electric path 5 formed on at least one side (both sides in this embodiment) thereof, and a reference guide 2 that serves as a mark for knowing the position where the electric path is formed.
Two 0's are provided side by side in the width direction. Also,
This inner layer material 3 is wider than the resin-impregnated base material 1 and the metal foil 2, and holes 4 are provided at three locations in the protruding portion thereof.

これら樹脂含浸基材と金属箔と内層材とは、連続的に上
下一対のロール6.6間に送り込まれる。内層材3は、
第3図にみるように、幅方向が移送方向に対して直交(
交差)する方向となるように送り込む。樹脂含浸基材と
金属箔と内層材とは、内層材3の両面に帯状の樹脂含浸
基材1,1、さらにその外側に帯状の金属箔2,2が配
置されるようにしてロール6.6で積層成形されること
により、帯状の積層体7となる。なお、第3図では、内
層材の電路5を省略してあられしている。
These resin-impregnated base material, metal foil, and inner layer material are continuously fed between a pair of upper and lower rolls 6.6. The inner layer material 3 is
As shown in Figure 3, the width direction is perpendicular to the transport direction (
(intersect) direction. The resin-impregnated base material, the metal foil, and the inner layer material are rolled into a roll 6. such that the resin-impregnated base material 1, 1 in the form of a belt is placed on both sides of the inner layer material 3, and the metal foil 2, 2 in the form of a belt is placed on the outside thereof. By laminating and molding in step 6, a strip-shaped laminate 7 is obtained. In addition, in FIG. 3, the electric circuit 5 of the inner layer material is omitted.

この後、得られた積層体7を加熱炉8に送り、ここで連
続的に加熱硬化させる。硬化後の積層体9を、ダイlO
とポンチ11とを備えた金型間に連続的に送り込む。ダ
イlOには、内層材の穴4と同じ間隔でピン12が形成
されていて、ピン12に穴4が差し込まれることによっ
て、金型に対する硬化後の積層体9の位置決めがなされ
るようになっている。このように、金型に対する硬化後
の積層板9の位置決めをしておいて、硬化後の積層体か
ら所定形状の多層プリント配線板13を金型で打ち抜く
ことにより得るようにする。
Thereafter, the obtained laminate 7 is sent to a heating furnace 8 where it is continuously heated and hardened. The laminate 9 after curing is die lO
and a punch 11. Pins 12 are formed in the die lO at the same intervals as the holes 4 in the inner layer material, and by inserting the holes 4 into the pins 12, the position of the laminate 9 after curing with respect to the mold is achieved. ing. In this manner, the cured laminate 9 is positioned with respect to the mold, and the multilayer printed wiring board 13 having a predetermined shape is punched out from the cured laminate using the mold.

以上のようにして、内部に電路が形成されているととも
に表面に金属箔が張られた多層プリント配線板が得られ
る。この後、前記基準ガイドを基に、表面の金属箔をエ
ツチングして電路を形成したり、スルホールを形成した
りするようにする。
In the manner described above, a multilayer printed wiring board having an electric path formed therein and a metal foil covered on the surface is obtained. Thereafter, based on the reference guide, the metal foil on the surface is etched to form an electric path or a through hole.

もし、硬化前と硬化後とで基準ガイド間の寸法が狂って
しまえば、内部の電路に対して、表面の電路およびスル
ホールが所望の位置に形成されないということが起こる
が、この多層プリント配線板の製法においては、前述し
たように、基準ガイドを成形方向に対して交差する方向
に並べて設けておくようにしているため、収縮が小さく
、硬化前と硬化後とで、基準ガイド間寸法の狂いが少な
いのである。
If the dimensions between the reference guides are incorrect before and after curing, the electrical circuits and through-holes on the surface will not be formed at the desired positions relative to the internal electrical circuits, but this multilayer printed wiring board In this manufacturing method, as mentioned above, the reference guides are placed side by side in the direction crossing the molding direction, so shrinkage is small and there is no difference in the dimension between the reference guides before and after curing. There are few.

この発明にかかる多層プリント配線板の製法は、前記実
施例に限定されない。前記実施例では、内層材の両面に
樹脂含浸基材を配置し、さらにその両性側に金属箔を配
置するようにしているが、片面のみしか樹脂含浸基材を
配置せず、金属箔もその外側に1枚しか配置しない場合
もあり、両面に樹脂含浸基材を配置した場合でも、その
片側だけしか金属箔を配置しない場合もある。また、内
層材を複数段、各内層材間に樹脂含浸基材を挟むように
して配置する場合もある。内層材を複数段に配置する場
合には、基準ガイドを最外層の内層材にのみ設けるよう
にすればよい。内層材は、帯状になっていてもよい。外
層材は、前記実施例のように、金属箔であってもよいし
、金属箔張り板であってもよい。樹脂含浸基材を用いず
に、接着剤を用いるようにしてもよい。
The method for manufacturing a multilayer printed wiring board according to the present invention is not limited to the above embodiments. In the above example, the resin-impregnated base material is placed on both sides of the inner layer material, and the metal foil is further placed on both sides, but the resin-impregnated base material is placed only on one side, and the metal foil is also placed on both sides. In some cases, only one metal foil is placed on the outside, and in some cases, even if resin-impregnated base materials are placed on both sides, metal foil is placed only on one side. Further, the inner layer materials may be arranged in multiple stages such that the resin-impregnated base material is sandwiched between each inner layer material. When the inner layer materials are arranged in multiple stages, the reference guide may be provided only on the outermost inner layer material. The inner layer material may be in the form of a band. The outer layer material may be a metal foil or a metal foil clad plate as in the above embodiment. An adhesive may be used instead of the resin-impregnated base material.

〔発明の効果〕〔Effect of the invention〕

以上にみてきたように、この発明にかかる多層プリント
配線板の製法は、少なくとも片面に電路が形成されてい
るとともにその電路の形成位置を知るための目印となる
基準ガイドが複数個設けられた内層材と外層材とを含む
帯状の積層体を積層成形により連続的につくり、この積
層体を連続的に移送しながら硬化させた後、硬化後の積
層体から所定形状の多層プリント配線板を得るにあたり
、前記基準ガイドを成形方向に対して交差する方向に並
べて設けておくことを特徴としているため、硬化前と硬
化後とで、基準ガイド間寸法の狂いが少ない多層プリン
ト配線板を得ることができる
As seen above, the method for manufacturing a multilayer printed wiring board according to the present invention is based on an inner layer in which an electric path is formed on at least one side and a plurality of reference guides are provided as marks for knowing the formation position of the electric path. A strip-shaped laminate including a material and an outer layer material is continuously produced by lamination molding, the laminate is cured while being continuously transferred, and a multilayer printed wiring board of a predetermined shape is obtained from the cured laminate. Since the reference guides are arranged side by side in a direction crossing the molding direction, it is possible to obtain a multilayer printed wiring board with little deviation in the dimensions between the reference guides before and after curing. can

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明にかかる多層プリント配線板の製法の
一実施例をあられす説明図、第2図は前記実施例に用い
る内層材をあられす斜視図、第3図は前記実施例の積層
成形工程をあられす平面図である。 2・・・金属箔(外層材) 3・・・内層材 5・・・
電路20・・・基準ガイド 代理人 弁理士  松 本 武 彦 第2図 @3図 手U辞甫正書岨発) 昭和61年 7月19日 昭和61年特許願第138695号 2、発明の名称 多層プリント配線板の製法 3、補正をする者 事件との関係    特許出願人 住   所    大阪府門真市大字門真1048番地
名 称(583)松下電工株式会社 代表者  イ懐輯役藤井貞夫 4、代理人 6、補正の対象 明細書 7、補正の内容 (11明細書第5頁第12行の「用いられる。」と「金
属箔」の間に、「また、エポキシ樹脂、ポリイミド樹脂
等も同様の方法で用いられる。」を挿入する。
Fig. 1 is an explanatory diagram showing an embodiment of the method for manufacturing a multilayer printed wiring board according to the present invention, Fig. 2 is a perspective view of the inner layer material used in the embodiment, and Fig. 3 is a laminated layer of the embodiment. It is a top view showing a molding process. 2... Metal foil (outer layer material) 3... Inner layer material 5...
Electrical line 20...Standard guide agent Patent attorney Takehiko Matsumoto (Figure 2 @ Figure 3) (From U Jifu Zheng Shue) July 19, 1988 Patent Application No. 138695 2 of 1988, Title of the Invention Manufacturing method for multilayer printed wiring boards 3, relationship with the amended case Patent applicant address 1048 Oaza Kadoma, Kadoma City, Osaka Name (583) Matsushita Electric Works Co., Ltd. Representative Ikai Tsuyoshi Fujii Sadao 4, Agent 6. Specification to be amended 7. Contents of amendment (11. On page 5, line 12 of the specification, between “used” and “metal foil”, “epoxy resin, polyimide resin, etc. Insert "Used in."

Claims (1)

【特許請求の範囲】[Claims] (1)少なくとも片面に電路が形成されているとともに
その電路の形成位置を知るための目印となる基準ガイド
が複数個設けられた内層材と外層材とを含む帯状の積層
体を積層成形により連続的につくり、この積層体を連続
的に移送しながら硬化させた後、硬化後の積層体から所
定形状の多層プリント配線板を得るにあたり、前記基準
ガイドを成形方向に対して交差する方向に並べて設けて
おくことを特徴とする多層プリント配線板の製法。
(1) A strip-shaped laminate including an inner layer material and an outer layer material, in which an electric path is formed on at least one side and a plurality of reference guides that serve as marks for knowing the formation position of the electric path, is formed continuously by lamination molding. After curing the laminate while continuously transporting it, in order to obtain a multilayer printed wiring board of a predetermined shape from the cured laminate, the reference guides are arranged in a direction perpendicular to the molding direction. A method for manufacturing a multilayer printed wiring board, which is characterized by providing a multilayer printed wiring board.
JP61138695A 1986-06-14 1986-06-14 Manufacturing method of multilayer printed wiring board Expired - Lifetime JP2544726B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61138695A JP2544726B2 (en) 1986-06-14 1986-06-14 Manufacturing method of multilayer printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61138695A JP2544726B2 (en) 1986-06-14 1986-06-14 Manufacturing method of multilayer printed wiring board

Publications (2)

Publication Number Publication Date
JPS62295489A true JPS62295489A (en) 1987-12-22
JP2544726B2 JP2544726B2 (en) 1996-10-16

Family

ID=15227959

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61138695A Expired - Lifetime JP2544726B2 (en) 1986-06-14 1986-06-14 Manufacturing method of multilayer printed wiring board

Country Status (1)

Country Link
JP (1) JP2544726B2 (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60119796A (en) * 1983-11-30 1985-06-27 松下電工株式会社 Method of producing multilayer printed circuit board
JPS60206089A (en) * 1984-03-29 1985-10-17 日立化成工業株式会社 Method of producing multilayer printed circuit board
JPH01120736A (en) * 1987-11-02 1989-05-12 Matsushita Electric Ind Co Ltd Transformer of inverter circuit for magnetron
JPH0578597A (en) * 1991-09-18 1993-03-30 Toppan Printing Co Ltd Radiation-curable coating composition

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60119796A (en) * 1983-11-30 1985-06-27 松下電工株式会社 Method of producing multilayer printed circuit board
JPS60206089A (en) * 1984-03-29 1985-10-17 日立化成工業株式会社 Method of producing multilayer printed circuit board
JPH01120736A (en) * 1987-11-02 1989-05-12 Matsushita Electric Ind Co Ltd Transformer of inverter circuit for magnetron
JPH0578597A (en) * 1991-09-18 1993-03-30 Toppan Printing Co Ltd Radiation-curable coating composition

Also Published As

Publication number Publication date
JP2544726B2 (en) 1996-10-16

Similar Documents

Publication Publication Date Title
JPS62295489A (en) Munufacture of multilayer printed interconnection board
JPS62295488A (en) Munufacture of multilayer printed interconnection board
JPS62295490A (en) Munufacture of multilayer printed interconnection board
JPH071828B2 (en) Method for manufacturing multilayer printed wiring board
SE465399B (en) SET ON MANUFACTURE OF MULTI-LAYER PATTERN CARDS
JP2004146624A (en) Method for manufacturing metal-foil-clad stacked plate having internal layer circuit
JPH043119B2 (en)
JPS62269391A (en) Manufacture of printed wiring board
JPS6156495A (en) Method of producing multilayer printed circuit board
JPS61120736A (en) Manufacture of multilayer printed wiring board
JPH05327192A (en) Manufacture of flexible printed circuit board
JP2003008176A (en) Manufacturing method of multi-layer board
JPH06244555A (en) Manufacture of multilayered laminate board
JP3159061B2 (en) Method of manufacturing metal foil-laminated laminate
JPH0320917B2 (en)
JPH05218616A (en) Manufacture of flexible printed wiring board
JPH071827B2 (en) Method for manufacturing multilayer wiring board
JPS63104806A (en) Manufacture of multi-layer board
JPS63136689A (en) Method and apparatus for forming double-sided circuit
JPH0635135B2 (en) Laminated board manufacturing method
JPS63285997A (en) Method and device for manufacturing multi-layer substrate
JPS6046098A (en) Method of producing multilayer board
JPS637040B2 (en)
JPH07336049A (en) Manufacture of multilayer printed circuit board
JPS5878750A (en) Manufacture of multilayer printed board