JPS62293836A - Time division multiplexer - Google Patents

Abstract

PURPOSE:To surely send an alarm without using a signal line exclusive for alarm by providing a fault detection means, an alarm sending means and an alarm signal detection means to a line interface unit. CONSTITUTION:The line interface unit 110 is provided with an error detection circuit 116 as a fault detection means and an AND gate circuit 117 as an alarm sending means. On the other hand, adaptor units 120a-120n each is provided with a pulse width deciding circuit 124 as an alarm detection means. If the error detection circuit 116 detects an error, it is sent to each adaptor unit 120a-120n via a write timing signal line 15, then the exclusive signal line to send the alarm is not required and the number of signal lines is reduced.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to a time division multiplexing device for time division multiplexing transmission of data using, for example, a high-speed digital line. Regarding.

(Prior art) Fig. 3 shows an example of the configuration of a conventional time division multiplexing device, where 1 is a time division multiplexing device and 28 to 2n
indicates a terminal device. The time division multiplexer 1 includes a line interface unit 11 and each terminal device 2a.
.about.2n, respectively. Of these, the line interface unit 11 is a frame decomposition circuit 11.
1 and a multiplexing section 112. Then, when time division multiplexed data arrives via the high-speed digital line 3,
After passing through the buffer circuit 113, this time-division multiplexed data is guided to the frame decomposition circuit 111 to each terminal device 2a.
The frame is decomposed into data of ~2n, the addresses of the adapter units 12a to 12n are added to these data, and the received data is sent to the PASCO 3. At this time, the frame decomposition circuit 111 generates a write timing signal WS in synchronization with the received data, and sends this timing signal WS to each adapter unit 1' via the timing signal line 15.
2 Supply to a to 12n. In addition, when transmission data is outputted from the adapter units 12a to 12n via the transmission data passco 4, the line interface unit 1-11 allocates the transmission data to the corresponding transmission channels in the multiplexer 112 and time-division multiplexes the transmission data. , this time-division multiplexed data is sent to the high-speed digital circuit $24 via the buffer circuit 114. Incidentally, at this time, the multiplexing section 112
supplies a read timing signal R8 to each adapter unit 12a to 12n via the timing signal line 16, thereby specifying the output timing of the transmission data to the transmission data bus 14.

On the other hand, each adapter unit 12a to 12n includes a reception buffer 121 and a transmission buffer 122, respectively. Then, when received data is sent from the line interface unit 11 via the receive data bus 13, this received data is sent to the receive buffer 121 in synchronization with the self-programming timing signal WS when the adapter address matches its own address. Import, then terminal device 2a
~Output to 2n. Furthermore, when transmission data is output from the terminal devices ftfi 2a to 2n, this transmission data is temporarily stored in the transmission buffer 122, read out in synchronization with the read timing signal R8, and sent to the line interface via the transmission data pathco 4. Multiplexer 11 of unit 11
Send to 2. Thus, the data sent and received by each of the terminal devices 2a to 2n is time-division multiplexed and transmitted via the high-speed digital line 3.4.

By the way, this rod device is designed to automatically transmit data to the line interface unit 11 and each adapter unit 128 to 12 when an abnormality occurs in the data transmission operation for the high-speed digital line.
It is necessary to perform predetermined abnormality processing for each of n. Therefore, in the past, for example, as shown in FIG. 3, an error detection circuit 115 is provided in the line interface unit 11, and this error detection circuit 115 first detects an abnormality in the communication line, that is, an abnormality in time division multiplexed data or the operation of the line interface unit 11. An abnormality is detected and an alarm indicating the occurrence of this abnormality is transmitted to each adapter unit 12a to 12n via the alarm signal line 17.Then, this alarm signal is sent to each adapter unit 128 to 12n.
The alarm signal is received by an alarm receiving circuit 123 provided at the terminal 2n, and the alarm signal is outputted from the alarm receiving circuit 123 to each of the transmitting and receiving buffers 121 and 122 for necessary processing. Therefore, even if an abnormality occurs, the time division multiplexing device can reliably and quickly deal with the abnormality and recover.

However, such conventional devices transmit alarm signals using dedicated signals 1i17.
The number of signal lines in the entire device is extremely large, and the number of signal lines in the device is increasing. i! It had the disadvantage of becoming cluttered and bulky. For example, 96
Alarm signal line 1 for devices that can manage multiple terminal devices
7 requires 96 signal lines, and laying these 96 signal lines means that each transmission and reception data bus 13 and 14
and write and read timing signal lines 15 and 16
In the case of a device in which a clock signal line and other clock signal lines are laid, the structure becomes complicated and large, which is very undesirable since space must be secured in addition to the wiring.

(Problems to be Solved by the Invention) As described above, the conventional device has a large number of signal lines for connecting the line interface unit and each adapter unit, which causes problems in the device. However, the present invention focuses on this problem and makes it possible to reliably transmit alarms without using a dedicated signal line for alarms, thereby simplifying the device configuration. The present invention aims to provide a time division multiplexing device that can be made smaller and more compact.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a line interface unit with an abnormality detection means for detecting an abnormality when an abnormality occurs in the transmission state of data to a communication line, and this abnormality detection means. and alarm sending means for sending an alarm signal in place of the normal control signal to a predetermined control signal line connecting between the line interface unit and each adapter unit when the occurrence of an abnormality is detected. , and each adapter unit is provided with alarm signal detection means for detecting an alarm signal sent from the line interface unit via the control signal line, distinguishing it from a control signal.

That is, the present invention focuses on the fact that there is a control signal line that does not require transmission of a control signal when an abnormality occurs, and uses this control signal line to transmit an alarm signal.

(Function) As a result, the alarm signal is transmitted via the existing control signal line, so there is no need to install a new signal line exclusively for alarms, and the wiring structure of the v device is simplified accordingly. Since the installation space can also be reduced, the configuration of the device can be significantly simplified and downsized.

Further, when an abnormality occurs, the alarm signal is transmitted by selecting a control signal line that does not require the transmission of the control signal, so that no problems that adversely affect the transmission of the control signal occur.

(Embodiment) FIG. 1 shows the configuration of a time division multiplexing apparatus in one embodiment of the present invention. In addition, in the same figure, the third
Components that are the same as those in the figures are given the same reference numerals and detailed explanations will be omitted.

The line interface unit 110 is provided with an error detection circuit 116 as an abnormality detection means and an AND gate circuit 117 as an alarm sending means. The error detection circuit 116 detects errors from time-division multiplexed data and also detects abnormal operations within the line interface unit 110. When an error is detected, the error detection circuit 116
Generates a detection output of a predetermined pulse width at L Tl level.

Here, the pulse width of the detection output is set longer than the pulse width of the write timing signal generated by the frame decomposition circuit 111. Furthermore, the AND gate circuit 117 sends the detection output of the "°L" level generated from the error detection circuit 116 to the interpolation timing signal line 15 in place of the write timing signal WS generated from the frame decomposition circuit 111. do.

On the other hand, each adapter unit 120a to 120n has a pulse width determination circuit 124 as an alarm detection circuit.
is the provision. This pulse width determination circuit 124 starts a timing operation every falling edge of the write timing signal WS sent via the timing signal line 15, for example, and when the falling edge is not detected within a certain time Ta, ' It consists of a counter or a one-shot multivibrator that generates an "H" level alarm detection signal, and outputs the alarm detection signal PS to receiving and transmitting buffers 121 and 122, respectively.

With this configuration, when normal data transmission is being performed, the detection output of the error detection circuit 116 is at the II HTl level, which indicates that no error has occurred, and therefore the output from the frame decomposition circuit 111 is The write timing signal WS is outputted as is to the write timing signal line 15 via the AND gate circuit 117 as shown in FIG. Furthermore, AD and DT in Figure 2
are the adapter address and data sent to each adapter unit 120a to 120n via the receiving data pathco 3, respectively.

For example, if an abnormality occurs in the transmission state of time division multiplexed data during data transmission, this abnormality will be detected by the error detection circuit 1.
16, and at that point the detection output becomes 'L' level. Therefore, the detection output ("LIT level") of the error detection circuit 116 is sent to the write timing signal line 15 instead of the write timing signal @WS that had been sent until then.On the other hand, at this time Each of the adapter units 120a to 120n has a pulse width determination circuit 124 that determines the pulse width of the signal sent via the write timing signal 1i115.
''When the level is above Ta for a certain period of time, the second
As shown in the figure, an alarm detection signal PS is generated. Therefore, predetermined abnormality processing is performed in each of the reception and transmission buffers 121 and 122 of each adapter unit 120a to 120n.

In this embodiment, when an error is detected by the error detection circuit 116, the error is notified to each adapter unit 1208 to 120n via the write timing signal line 15.
Therefore, there is no need for a dedicated signal line for transmitting the alarm, and the number of signal lines can be reduced accordingly, making it possible to simplify and downsize the device configuration. Further, when an abnormality occurs, there is no need to perform a write operation of received data, and a write timing signal is not required, so that there is no problem in transmitting the write timing signal.

Note that the present invention is not limited to the above embodiments. For example, in the above embodiment, the alarm is transmitted using the write timing signal line 15, but it may also be transmitted using the read timing signal line 16 or the O-lock signal line (not shown). In addition, the configurations of the alarm sending means and the alarm detecting means can be modified in various ways without departing from the gist of the present invention.

[Effects of the Invention] As described in detail above, according to the present invention, the line interface unit includes an abnormality detection means for detecting an abnormality when an abnormality occurs in the data transmission state to the communication line, and the abnormality detection means detects the abnormality. alarm sending means for sending an alarm signal in place of the normal control signal to a predetermined control signal line connecting between the line interface unit and each adapter unit when the occurrence of By providing each adapter unit with an alarm signal detection means that detects the alarm signal sent from the line interface unit via the above-mentioned control signal line, distinguishing it from the control signal, alarms can be detected reliably without using a signal line exclusively for alarms. This makes it possible to simplify and downsize the device configuration (9 hours/minute v1 multiplexing device can be provided).

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a time division multiplexing device in an embodiment of the present invention, FIG. 2 is a timing diagram for explaining the operation of the same device, and FIG. 3 is a conventional time division multiplexing device. FIG. 2 is a block diagram showing an example of the configuration of a device. 3.4... High-speed digital line, 10... Time division multiplexer, 13... Reception data bus, 14... Transmission data bus, 15... Write timing signal line, 16.
...Read timing signal line, 28-2n...Terminal device, 110...Line interface unit, 111
. . . Frame decomposition circuit, 112 . . . Multiplexing unit, 11
3.114... Buffer circuit, 116... Error detection circuit, 117... AND gate circuit, 120a-1
2On...Adapter unit 1-1121...Reception buffer, 122...Transmission buffer, 124...Pulse width determination circuit, W S...Write timing signal, P
S...Alarm detection signal.

Claims (2)

[Claims] (1) A plurality of adapter units, each of which is provided corresponding to a plurality of terminal devices, inputs and outputs transmission data to and from the terminal device, and time-division multiplexes the transmission data output from the adapter units and sends the data to a communication line. In a time division multiplexing device, the time division multiplexing device is equipped with a line interface unit that decomposes multiplexed data that has arrived via a communication line and outputs the decomposed data to each adapter unit. An abnormality detection means detects when an abnormality occurs, and when the abnormality detection means detects the occurrence of an abnormality, a normal signal is sent to a predetermined control signal line connecting between the line interface unit and each adapter unit. an alarm sending means for sending an alarm signal in place of the control signal of the adapter unit, and detects the alarm signal sent from the line interface unit to each of the adapter units via the control signal line, distinguishing it from the control signal. 1. A time division multiplexing device comprising: alarm detection means. (2) The alarm sending circuit continuously fixes the signal level of the control signal line at a predetermined level for a period longer than the maximum pulse width of the regular control signal, and sends this as an alarm signal. The time division multiplexing device according to paragraph (1).