JPH0376332A - Time division multiplexer - Google Patents

Abstract

PURPOSE:To quickly execute a proper processing by providing a data conversion means and a fault detection means to a low speed interface to detect a fault or a data error or the like generated in a time division multiplexer with the time division multiplexer. CONSTITUTION:Low speed interfaces 101-10m provided with a code rule violation(CRV) generating circuit 76 or the like as a transmission system circuit and a CRV detection circuit 80 or the like as a reception system circuit. Then to a transmission data sent from a terminal equipment, a bit causing a code rule violation in terms of the code form is inserted at a prescribed bit interval and the result is outputted to the time division multiplex section. On the other hand, a transmission data transferred from the time division multiplex section is detected for the presence of a code rule violation bit via the circuit 80 and when the code rule violation bit is not detected for a prescribed bit interval, an alarm signal is generated. Thus, a fault or a data error or the like generated in the time division multiplexer is detected in the time division multiplexer and a proper countermeasure processing is quickly taken.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Field of Application) The present invention relates to a time division multiplexing apparatus for time division multiplex transmission of terminal data using, for example, a high-speed digital line.

(Prior Art) FIG. 3 shows an example of the basic configuration of a time division multiplexing device, where 1 is the time division multiplexing device and 21 to 2m are terminal devices. The time division multiplexer 1 has high speed digimole times tj[3
a time division multiplexing section 4 connected to
.about.2m, a plurality of low speed interfaces 11 to 1m connected via low speed lines 31 to 3m, respectively, and a control section 5. Of these, the time division multiplexer 4 has a multiplexer and a demultiplexer for transmission data. The multiplexing unit inputs the transmission data from the terminal devices 21 to 2m via the internal bus 6 by time-divisionally accessing each of the low-speed interfaces 11 to 1m, and time-divisionally multiplexes these transmission data to generate high-speed digital data. Send to line 3. The separation unit separates the time-division multiplexed data arriving via the high-speed digital line 3 into each terminal data, and transfers each separated terminal data to the corresponding low-speed interfaces 11 to 1m via the internal bus 6.

On the other hand, the low-speed interfaces 11 to 1m are connected to the terminal devices 21 to 1m.
2m and the time division multiplexing section 4, and includes, for example, a transmission buffer 71, a reception buffer 72, and a timing generation circuit 73 as shown in FIG.

The transmission buffer 71 temporarily stores the transmission data sent from the terminal devices 21 to 2m in synchronization with the terminal clock CK2 outputted from the timing generation circuit 73, and then stores the transmission data sent from the terminal devices 21 to 2m once, and then stores the transmission data sent from the terminal devices 21 to 2m in synchronization with the terminal clock CK2 outputted from the timing generation circuit 73. A predetermined amount is read out in accordance with the signal RS and output to the internal bus 6. The reception buffer 72 stores the received data transferred from the time division multiplexer 4 via the internal bus 6 according to the write control signal WS, and then sequentially stores it in synchronization with the terminal clock CK2 generated from the timing generation circuit 73. Read and terminal device 21
Output towards ~2m. Furthermore, the timing generation circuit 73
is generated by frequency-dividing the transmission lock CKI supplied from the time division multiplexer 4 to the terminal clock CK2.

With such a configuration, when transmission data is sent from each of the terminal devices 21 to 2m, these transmission data are first written to the transmission buffers 71 of the low-speed interfaces 11 to 1m, respectively, and then time-division multiplexed. The signals are read onto the internal bus 6 at predetermined timings in synchronization with the read control signal RS supplied from the converting section 4, and introduced into the time division multiplexing section 4. These transmission data are time-division multiplexed by the time-division multiplexer 4 and transmitted to the high-speed digital line 3, and then transmitted to the other party's time-division multiplexing device having a similar configuration via the high-speed digital line 3. be done.

On the other hand, when time division multiplexed data arrives from the other party's time division multiplexing device via the high-speed digital line 3, this time division multiplexed data is separated for each terminal data in the time division multiplexer 4, and then transferred to the internal bus 6. sent upwards. Further, at this time, the write control signal WS is supplied to each of the low-speed interfaces 11 to 1m in a time-division manner from the time-division multiplexing section 4 in accordance with the transmission order of the terminal data. For this reason, each of the low-speed interfaces 11 to 1m receives only the received data addressed to itself among the terminal data strings sent out on the internal bus 6.

After this received data is further written into the reception buffer 72, it is sequentially read out at a constant speed in synchronization with the terminal clock CK2 and transmitted to the terminal devices 21 to 2m.

(Problems to be Solved by the Invention) However, such conventional devices have the following problems. That is, the transmission data sent from the terminal devices 21 to 2m is transferred to the time division multiplexing unit 4 as it is after being speed-converted by the low-speed interfaces 11 to 1m.
The signals are then time-division multiplexed and transmitted to the high-speed digital line 3.

Furthermore, data arriving via the high-speed digital line 3 is also separated by the time division multiplexer 4, then speed-converted by the low-speed interfaces 11-1m, and then transmitted as is to the terminal devices 21-2m. For this reason, for example, a failure may occur in the low-speed interfaces 11 to 1m, making it impossible to perform normal data transfer operations, or the internal bus 6.
If a code error or the like occurs in the time division multiplexing section 4, the occurrence of such failure or code error can only be detected by the terminal devices 21 to 2m that have received the data. Therefore, when a failure or a transmission error occurs in the time division multiplexing device, it is difficult to take appropriate countermeasures quickly.

Therefore, the present invention has focused on the above points, and enables the time division multiplexing device to detect failures, data errors, etc. that occur in the time division multiplexing device, thereby allowing the time division multiplexing device to quickly take appropriate countermeasures. The purpose is to provide equipment.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a plurality of low-speed human outputs that are provided corresponding to a plurality of terminal devices and output data transmitted to the terminal devices. It time-division multiplexes the transmission data output from the interface and these low-speed interfaces and sends it out to the communication line, and also decomposes the time-division multiplexed data that arrives via the communication line into terminal data and transfers it to the corresponding low-speed interface. In a time division multiplexing device equipped with a time division multiplexing section, each of the low-speed interfaces is provided with a data conversion means and an abnormality detection means, and the data conversion means converts the transmission data sent from the terminal device into the transmission data. Bits that violate the coding rules for the code format are inserted at regular bit intervals and output to the time division multiplexing section, and the abnormality detection means detects the coding rules from the transmission data transferred from the time division multiplexing section. Violating bits are detected, and an alarm signal is generated if the bits violating the coding rule are not detected at regular bit intervals.

(Function) As a result, according to the present invention, when a failure occurs in the low-speed interface in the time division multiplexing device on the transmitting side and normal data transfer operation cannot be performed due to this, the insertion of coding rule violation bits is also performed normally. I won't be able to do it. Furthermore, if a data error occurs during transmission, the time division multiplexing device on the receiving side cannot correctly detect bits that violate coding rules. Therefore, by monitoring the detection status of coding rule violation bits in the received data, the time division multiplexing device on the receiving side can determine that a failure has occurred in the time division multiplexing device on the transmitting side, and at that point This makes it possible to quickly take appropriate countermeasures, such as stopping the data transmission of the transmitter, or causing the time division multiplexing device on the transmitting side to halt the transmitting operation.

(Embodiment) FIG. 1 shows the configuration of a low-speed interface of a time division multiplexing device in an embodiment of the present invention. It should be noted that the other circuit sections of the time division multiplexing device have the same configuration as in FIG. 3, so detailed explanations will be omitted.

The low-speed interfaces 101 to 10m first include a transmission buffer 71, a transmission timing generation circuit 74, a code conversion circuit 85, a code rule violation generation circuit (CRV generation circuit) 76, and a switching circuit 77 as a transmission system circuit section. have.

The code conversion circuit 75 converts the code form of the transmission data SD read from the transmission buffer 71 into NRZ (Non ret
urn-to-Zero) code to CM I (Co
dedMark Inversion) code.

CMI code is, for example, "0" becomes 10, "1" becomes 11
and 00 alternately, thereby preventing consecutive "0"s.

The CRV generation circuit 76 generates a bit (CRV bit) that violates the coding rule for the bit string for each predetermined bit of the transmission data SD read out from the transmission buffer 71. Output to. The switching circuit 77 switches between the output of the code conversion circuit 75 and the output of the CRV generation circuit 76 in accordance with the switching control signal generated from the transmission timing generation circuit 74, and thereby changes the transmission data converted into the CMI code at predetermined bit intervals. The CRV code is inserted into the .

The transmission timing generation circuit 74 generates a read gate signal to the transmission buffer 71, a code conversion circuit 75, and a read control signal R8' sent from the time division multiplexer 4.
A timing signal and a switching control signal to the RV generation circuit 76 are respectively generated.

On the other hand, the reception circuit section includes a reception timing generation circuit 78, seven code conversion circuits, and a CRV detection circuit 80 in addition to the reception buffer 72.

The code conversion circuit 79 connects the time division multiplexer 4 to the internal bus 6.
The code form of the received data HRD' transferred via C
M! This converts the code into an NRZ code. CRV
The detection circuit 73 detects CR from the received data HRD'.
The V bit is detected, and when the CRV bit is no longer detected at a predetermined bit interval, an alarm signal AL is generated. This alarm signal AL is introduced into the control unit 5 of the time division multiplexer 4, for example. The reception timing generation circuit 79 generates a write gate signal to the reception buffer 72 in synchronization with the write control signal WS' sent from the time division multiplexer 4.

With such a configuration, the transmission data SD transmitted from the terminal devices 21 to 2m is transmitted to the communication timing generation circuit 73.
The transmission timing generation circuit 7 writes sequentially to the transmission buffer 71 according to the low-speed clock CK2 generated from the
In accordance with the successive gate signal generated in step 4, the transmission data SD is read out from the transmission buffer 71 in fixed bits at a time. This transmission data SD is converted into NR by the code conversion circuit 75.
After the code is converted from the Z code to the CMI code, it is sent to the internal bus 6 via the switching circuit 77.

At this time, the CRV generation circuit 76 generates a bit that violates the coding rule for the bit string for each predetermined bit of the transmission data SD, and the CRV bit is transmitted to the transmission data of the CMI code by passing through the switching circuit 77. H
It is pushed into 8D'. For example, if the bit string of the transmission data SD read out from the transmission buffer 71 is roloooolooJ as shown in FIG. The code is converted into a CMI code, a CRV bit '00' is added to the end of the code, and the code is sent to the time division multiplexer 4.

The transmission data H8D' sent out from each of the low-speed interfaces 101 to 10m are mutually time-division multiplexed by the time-division multiplexer 4 and transmitted to the high-speed digital line 3.

On the other hand, when time division multiplexed data arrives from the communication partner's time division multiplexing device via the high-speed digital line 3, this time division multiplexed data is separated for each terminal data in the time division multiplexing section 4, and then internally transmitted. The data is transferred to each of the low-speed interfaces 101 to 10m via the bus 6. Then, when it is introduced into the low-speed interfaces 101 to 10m, the received data HRD'
is first converted back from the CMI code to the NRZ code by the code conversion circuit 79, and then written to the reception buffer 72. Note that the CRV bit added to the received data is deleted by this timing control during writing. Then, this received data RD is sequentially read out from the reception buffer 72 according to the low-speed clock CK2, and
It is transmitted to the terminal devices 21 to 2m via 3m.

By the way, when the above received data HRD' is introduced, CR
The V detection circuit 80 detects CRV from the received data HRD'.
Bit monitoring is performed.

In this state, if the low-speed interface of the time-division multiplexing device on the transmitting side were to malfunction, this would cause a tossle in which normal data transfer operations could no longer be performed. In this case, the CRV bits are added and the process is not performed normally, so that the CRV detection circuit 80 of the time division multiplexing device on the receiving side cannot detect the CRV bits at predetermined bit intervals. Then, at that point, the CRV detection circuit 80 outputs an alarm signal A.
L is generated and supplied to the control section 5. For this reason, the control unit 5 performs an operation to stop the data transmission operation to the terminal devices 21 to 2m, for example, or sends an alarm to the time division multiplexing device on the transmitting side to the effect that there is an abnormality.

In addition, even if there is no failure in the time division multiplexing device on the transmitting side, if a data error occurs due to deterioration in transmission quality or the introduction of noise, the time division multiplexing device on the receiving side will change the CRV bit to a specified bit. It is no longer detected at intervals, and the CRV detection circuit 80 generates an alarm signal AL. Therefore, in this case as well, the control unit 5 quickly takes appropriate measures as described above.

In this embodiment, the low-speed interface 101
~10m transmission system, converts the transmission data SD into a CMI code, adds CRV bits every predetermined bits, and transmits it, and low-speed interfaces 101 to 10
Since the receiving system of m monitors whether the CRV bit is detected from the received data HRD' at a predetermined interval and generates an alarm signal AL if it is not detected, a failure occurs in the low-speed interfaces 101 to 10m. If data errors occur during transmission, these can be detected by the time division multiplexing device on the receiving side. For this reason,
Compared to the conventional method, which detected data from the received data at the terminal devices 21 to 2m, it is possible to detect failures and deterioration in the quality of the transmission path much more quickly, making it possible to take appropriate countermeasures quickly. Become.

Note that the present invention is not limited to the above-mentioned embodiment. For example, in the above-mentioned embodiment, the transfer speed of the transmitted and received data on the internal bus 6 is set to the same speed as before, and the CRV bit is set at predetermined intervals for the transmitted data. However, the transfer speed of the transmitted and received data may be made faster than before by speed conversion, and the CRV bit may be inserted into the remaining bits generated by this speed conversion before being transferred.

In this way, the length of the time slot for transmitting and receiving data allocated to each low-speed interface does not need to be increased by the amount of CRV bits, and can be set to the same q length as before.

Further, in the above embodiment, the terminal data is code-converted and CRV
I added a bit, but the code of the terminal data is C.
In the case of a code to which an RV bit can be added or inserted, there is no need to perform particular code conversion. In addition, the type of conversion code, the addition or insertion position of the CRV bit, the circuit configuration of the low-speed interface, countermeasures when an alarm is generated, etc. can be modified in various ways without departing from the gist of the present invention.

[Effects of the Invention] As detailed above, according to the present invention, each low-speed interface is provided with a data conversion means and an abnormality detection means, and the data conversion means converts the transmission data sent from the terminal device into Bits that violate the coding rules for the code format are inserted at regular bit intervals and output to the time division multiplexing section, and the abnormality detection means detects the code from the transmission data transferred from the time division multiplexing section. By detecting code violation bits and generating an alarm signal when these coding rule violation bits are not detected at regular bit intervals, failures, data errors, etc. that occur in the time division multiplexing device can be detected by time division multiplexing. can be detected in the device,
This makes it possible to provide a time division multiplexing device that can quickly take appropriate countermeasures.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing the configuration of a low-speed interface of a time division multiplexing device in an embodiment of the present invention, FIG. 2 is a signal waveform diagram showing an example of code conversion and CRV bit addition states, and FIG. The figure is a circuit block diagram showing an example of the basic configuration of a time division multiplexing device, FIG. 4 is a circuit block diagram showing the configuration of a low-speed interface in the same device, and FIG. 5 is a schematic configuration diagram of a time division multiplexing transmission system. be. 1... Time division multiplexing device, 21-2m... Terminal device,
3...High-speed digital line, 31-3m...Low-speed line, 4...Time division multiplexing unit, 5...Control unit, 6...
- Internal bus, 71... Transmission buffer, 71... Reception buffer, 73... Communication clock generation circuit, 74...
- Transmission timing generation circuit, 75. 79... Code conversion circuit, 76... Code rule violation (CRV) generation circuit, 77
... switching circuit, 78 ... reception timing generation circuit,
80... Code rule violation (CRV) detection circuit, 101-1
0m...Low speed interface.

Claims (1)

[Scope of Claims] (1) A plurality of low-speed interfaces provided corresponding to a plurality of terminal devices and inputting and outputting transmission data to and from the terminal devices, and time-division multiplexing of the transmission data output from these low-speed interfaces. In a time division multiplexing device, the time division multiplexing unit includes a time division multiplexing unit that transmits the data to a communication line, and also decomposes the time division multiplexed data that has arrived via the communication line into terminal data and transfers it to a corresponding low-speed interface.
Each of the low-speed interfaces includes a converting means that inserts bits that violate the coding rules for the code format into the transmission data sent from the terminal device at regular bit intervals, and outputs the inserted data to the time division multiplexing unit; and an abnormality detection means for detecting a coding rule violation bit from the transmission data transferred from the encoding section and generating an alarm signal if the coding rule violation bit is not detected at a constant bit interval. Multiplex device. (2) The conversion means converts the transmission data sent from the terminal device into a predetermined zero consecutive suppression code,
Further, bits that violate a coding rule for this code are inserted into the code-converted transmission data at constant bit intervals and output to the time division multiplexing section (1).
) time division multiplexing device. (3) The converting means converts the transmission data sent from the terminal device into a predetermined zero consecutive suppression code and converts the speed,
Further, bits that violate a coding rule for the consecutive zero suppression code are inserted into the surplus bits generated at regular intervals by this speed conversion, and the bits are output to the time division multiplexing section. Time division multiplexer.