JPS62291059A - Solid state color image sensing device - Google Patents

Abstract

PURPOSE:To obtain a solid state color image sensing device which facilitates reading signal charges created in a photodiode region directly with high accuracy without using a CCD and simplifying an external color signal processing circuit by a method wherein a specific photodetector, charge transfer control gate electrode, charge storing gate electrode, floating gate electrode and so forth are provided. CONSTITUTION:2nd conductivity type semiconductor region 3 is formed in the surface of 1st conductivity type semiconductor substrate 1 and a photodetector is constituted by the region 3 and the substrate 1 and a color separation filter 3a is formed on the region 3 with an insulating film between. Further, 2nd semiconductor region 2 of the 2nd conductivity type for storing signal charges is formed in the surface of the substrate 1 with an interval between the region 3 and itself. A charge transfer control gate electrode 14 which controls the transfer of the signal charges to the region 2 and whose potential is fixed to the 1st potential is formed on the substrate 1 between the regions 3 and 2. A charge storing part gate electrode 15 whose potential is fixed to the 2nd potential is formed on the region 2 on the region 2 with an insulating film 46 between. Further, a floating gate electrode 16 for detecting the signal charges stored in the region 2 is formed between the region 2 and the charge storing part gate electrode 15.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a color prison imaging device, and particularly to a color solid-state &Iil imaging device in which a floating gate electrode is provided above a signal charge storage region. It is related to the device.

[Prior art] Fig. 4 shows the conventional Charge-8kle+5ino
FIG. 2 is a poly cross-sectional view of the structure of one pixel from the photodiode region to the CCI (charge coupled device) of the solid-state image transfer device operating in -Mode.

In the figure, a 0+ type silicon region 11163 and an n- type silicon region 62 are formed on the surface of a 0 type silicon region 1 at a distance from each other. The n+ type silicon region 63 and the surrounding p type silicon substrate 1 form a diode region 71 in the pn filter A1. This pn-A diode region 71 converts the incident light into a signal. 'do. Gate electrodes 64, 65, .
66.67°68 is formed. 84, 85, 86
．． 87° and 88 are gate voltage input terminals. In particular, the gate electrode 88 is a COD electrode, and a COD signal is input to this gate electrode 88. The n-type silicon region 62 serves as a Verirad channel region suitable for charge transfer.
The signal charge from the pn photodiode region 71 is transferred to the region under the gate electrode 68 of the COD through the region under the gate electrodes 64, 65, 66, and 67, and the signal charge is transferred to the region under the gate electrode 68 of the COD.
is read externally.

Figures 5(a), (b), (c), and (d) show the Chargo -3klnu++ing structure for one pixel in Figure 4.
-Mode It is a figure which shows the potential of each part for demonstrating operation|movement. In the figure, (a) and (b).

(C) and (d) are diagrams each corresponding to the operation of each part at each time. 71 corresponds to the pn photodiode region 71 shown in FIG. 4, and 72.73.74
．． 75 and 76 are the gate electrodes 6 of the p-type silicon substrate/plate 1 and the n-type silicon region 62 shown in FIG. 4, respectively.
It shows the area under 4.65.66.67.68. In addition, 78, 79, and 77 are gate electrodes 64, 6, respectively.
6.68 shows signal charges accumulated in the area below.

Next, Charge −S k of the structure for one pixel in FIG.
The ialIing-Modo operation will be explained with reference to FIG. When the voltages applied to the gate electrodes 64 to 68 shown in FIG. 4 are increased, the body deficiencies 11 of each part shown in FIG. 5 are lowered. This is because the potential for electrons in FIG. 5 is assumed to be positive. first,(
a) shows the charge accumulation state. Electrode 67 to goo 1
is in the OFF state, and area 75 also shows the OFF state. At this time, the area 76 and area 74, which are the COD transfer sections, are cut off. The electrode 64 to goo 1 is always D.
C voltage is applied, and the potential of area IA72 does not change. Then, the electrodes 65 and 66 are in the ON state, and the goo 1~? ! A deep storage well is formed in region 74 above the basin 66. pn photodiode region 71
The potential of the region 72 is fixed by the DC voltage applied to the gate electrode 64. fixed by the That is, the pn photodiode region 71 is
Even if the potential of this pn photodiode region 71 increases due to signal charges (electrons) generated within the pn
The signal charge overflows from the photodiode region 71 over the fixed potential barrier of the region wt72, and is transferred to the pn photodiode region tii! The potential of 271 returns to its original state. This overflowing signal charge flows into the well in region 72, but at this time, this well is already filled with signal charge 78, so the signal charge is transferred to the well in region 74 and accumulated as signal charge 79. be done. Next, after a certain accumulation time of the signal charge 79 has elapsed, the gate electrode 67 is turned ON and the gate electrodes 65 and 66 are turned OFF, so that the signal charge 79 in the loop of the region 66 becomes COD. It is transferred into the well of region 76, which is the transfer section. Also, at this time, signal charges generated in the pn photodiode region 71 by the incident light are accumulated in the well of the region 72 (Fig. 5(b)
))−〇−. Next, the goo 1 to electrode 67 are in the 01F state, and the area 7
The No. 11 Kasumi cargo 77 in No. 6 is transferred to the outside by COD (Fig. 5 (C)). Next, the gate electrode 65.66
No. 10 is returned to the N state, and the signal charges that had been accumulated in the well of region 72 flow into the well of region 74 (
Figure 5(d)).

This person 115 (Chargo -311i1111
110Q mode) has the advantage that the potential of the pn photodade region 71 can be kept constant. By fixing the potential of the pn photodiode region 71 to the potential of the adjacent gate region, p If
The signal charge leaking out from the photodiode region 71J is
This is the net signal charge generated by the incident light, and excellent linearity is established between the amount of incident light and the signal charge l accumulated in the area TjI74.

FIG. 6 is a diagram showing an example of the configuration of a linear image sensor in which a plurality of structures for one pixel in FIG. 4 are arranged in one line so that C sequential signal charges are not read out by COD.

In the figure, 82 is the gate electrode 64°65 in Figure 134.
．． 66.67 and the gate oxidation below these gate electrodes! 1191, a p-type silicon M plate 61, and a 0-type silicon region 62.
3 shows a COD composed of the N electrodes 68, the gate oxide film 91, the p-type silicon region 1, and the n-type silicon region 62 under the N-electrodes.

Further, 89 is a signal amplification circuit, and 90 is an output terminal. The signal charge from each pn photodiode region 71 is transferred to the CCD 83 through the signal charge transfer region 82 using the method described in FIGS. After being transferred to and amplified, it is read out from the output terminal 90.

By the way, in COD, there has been a method in the past in which the amount of signal charge to be transferred is sensed by a floating gate electrode provided between a fixed potential gate electrode and a transfer region, for example, as disclosed in Documents W and E.

Engeler, J., Tie+mann,
“3 surface” by R, D, Baertsch
Charge transport tn 5i1ic
on” Δpp1.Phys, LOtt, 17
pll, 469-472 (1070).

FIG. 7 is a sectional view showing the structure used in the COD described in the above-mentioned document. In the figure, a 0'-type series field 20 is formed on the surface of a p-type linear substrate 1. The p-type silicon 1-It board 1 (1j and 0-type silicon regions 20 have a flow through the goo 1-oxide film 39 consisting of 5102).
i-rng game 1~? a IM 3-7 is formed, and this floating gate 1'44A+ 3-/
A fixed potential gate electrode 38 is formed on the soil with an oxide film 40 interposed therebetween.

It is now assumed that the n-type silicon region 20 is in a low depleted state. That is, in the n-type silicon region 20, there is no information JJN direction (w1 child), and only fixed positive charges (donors) exist. At this time, the potential distribution on the dashed-dotted line A-A becomes as shown in FIG. 8<a>.

This potential distribution is obtained by solving Boisson's equation, and in the literature, for example, "P" of S, M, 5ZOW.
L+physics of 3eml conductor
[)ovices”-9= 3econti FdiNOn pp, 423~
(7, 4, 4.

Buried Channel CCD). Further, the potential distribution 4J on the dashed-dotted line A-A when signal charges are injected into the n-type silicon region 20 is shown in FIG.
b) Assuming that the signal charge is divided into fixed positive charges and the fixed positive charge distribution is constant, the electric field is uniform and the potential is constant in the region where fH charges are accumulated. The potential in the region where signal charges are accumulated is considered to be the potential due to the fixed positive charges minus the signal charge (potential due to the small number of electrons), and the potential in the region where the signal charges are accumulated is the same as the fixed potential gate +-X pole 38 and the fl where the signal charges are accumulated. The electric field between the regions changes depending on the amount of signal charge applied to the n-type silicon region 20. Then, the potential of the floating group 1 to electrode 38 also changes depending on the amount of integrated signal charge. Therefore, the electrode 38 of the floating gate 1 can be used for detecting the amount of signal charge.

The principle of this floating gate structure is to achieve high sensitivity and S/
Due to the high N, it is effective as a method for detecting the M charge during COD transfer.
There has been no report yet on a method of detecting signal charges by providing 70-signal gates 1 to m poles on the signal charge storage region in the IIMING-JYLODE.

[Problems to be solved by the invention] Conventional Charoe-Sklwvina-Mode
The structure of one pixel of an operating solid-state imaging device is constructed as described above, and a signal charge having a linear relationship with incident light is read out by COD and there is only one signal output line.

Therefore, if the signal charge transfer efficiency in the COD is poor or if the number of stages in the COD increases, the signal charges will not be read out accurately and the Charge -8kissin
There were problems in that the advantages of g-Mode were not fully utilized, and when colorization was used, the external color signal processing circuit was complicated because there was only one signal output line.

This invention was made in order to solve the above-mentioned problems.
It is an object of the present invention to provide a color solid-state m-image device that can directly read signal charges generated in a range with high precision and that can simplify an external color signal processing circuit.

[Means for Solving the Problems] A color solid-state imaging device according to the present invention includes a first semiconductor region of a second conductivity type formed on a surface of a semiconductor substrate of a first conductivity type, the first semiconductor region; The surrounding semiconductor substrate constitutes a photodetection section that converts incident light into signal charges,
A color separation filter is formed on the first semiconductor region via an insulating film, and a second conductivity type filter is formed on the surface of the semiconductor substrate at a distance from the first semiconductor region for accumulating signal charges from the photodetector. A second semiconductor region is formed on the semiconductor substrate between the first semiconductor region and the second semiconductor region through an insulating film, the potential of which is fixed at the first potential, and signal charges generated in the photodetector are fixed. A charge storage section in which a charge transfer control gate electrode is formed to control the movement of the charge to the second semiconductor region, and the potential thereof is fixed at a second potential through an insulating film on the second semiconductor region. A gate electrode is formed, and a floating gate electrode for detecting a signal voltage field accumulated in the second semiconductor region is formed between the second semiconductor region and the charge storage portion gate electrode.

[Function] According to the present invention, since the potential of the photodetector is fixed at a constant potential by the charge transfer control gate electrode fixed at the first potential, the signal generated in the photodetector by incident light is Charge overflows from this photodetector and is accumulated in the second semiconductor region. Then, this overflowing signal charge becomes a net signal charge generated by the incident light, and excellent linearity is established between the amount of incident light and the amount of signal charge accumulated in the second semiconductor region.

Furthermore, since the floating gate electrode is formed between the charge storage section gate electrode fixed at the second potential and the second semiconductor region, the potential of the floating gate electrode is determined by the potential of the second semiconductor region. Since the potential of this second semiconductor region is determined by the amount of signal charge added to it, the potential of the floating gate electrode represents the amount of accumulated signal charge. By detecting the potential of the photodetector, the signal charge generated in the photodetector can be directly read out with high sensitivity without using COD, which poses problems in transfer efficiency and the number of stages.

Furthermore, since the potential of the floating gate electrode is directly read out using the scanning circuit, it is possible to separate signal output lines for each color separation filter, and it is possible to simplify the external color signal processing circuit.

[Example] Embodiments of the present invention will be described below with reference to the drawings.

In the description of this embodiment, the description of parts that overlap with the description of the conventional technology will be omitted as appropriate.

FIG. 1 is a cross-sectional view showing the structure of one pixel of a solid-state imaging device according to an embodiment of the present invention.

First, the configuration of this one pixel structure will be explained. In the figure, an n+ type silicon region 3, a row type silicon region 2, and n+ type silicon regions 41, 42, 43, 44.degree. 45 are formed at intervals on the surface of a p-type silicon substrate 1. A color separation filter 3a is formed on the n+ type silicon region 3 via a gate oxidation wA46. p between n+ 10-type silicon region 3 and 0-type silicon region 2
A charge transfer control gate electrode 14 made of polysilicon is formed on a shaped silicon substrate 1 with a gate oxide film 46 interposed therebetween. Further, a floating gate electrode 16 made of polysilicon is formed on the n-type silicon region 2 with a gate oxide film 46 interposed therebetween. Reference numeral 15 denotes a charge storage gate electrode made of polysilicon, which is partially formed on the silicon region 2 via a film 46 made of goo 1 to m, and the remaining part is formed on the floating gate electrode 16. It is formed thereon with an oxide film 47 interposed therebetween. The p-type silicon substrate 1, the 04-type silicon region 3, the n-type silicon region 2, the goo 1 to oxide film 46, and the charge transfer control gate electrode 14 constitute a MOS transistor 23. A pn photodiode region 20 for converting incident light into signal charges is formed by the n+ 10-type silicon region 3 and the p-type silicon substrate 1 around it. The n-type silicon region 2 is a region for accumulating signal charges generated in the pn photodiode region 20. The potential of the charge transfer control gate electrode 14 is fixed at a constant potential by the charge transfer control voltage (VGPO) applied from the gate voltage input terminal 5, thereby fixing the potential of the pn photodiode region 20 at a constant potential. The movement of signal charges generated in the pn photodiode region 20 to the n-type silicon region 2 is controlled. The potential of the charge storage section gate electrode 15 is determined by the gate voltage input terminal 6.
The aMOS transistor 25, which is fixed by the storage gate voltage (v, T) given by The overflow drain voltage (Voro) is given by
The other electrode is connected to the n-type silicon region wt2, and an overflow control clock (VGoro) is applied to the gate electrode from the gate voltage input terminal 8. Also, n
A gate electrode 17 made of polysilicon is formed on the p-type silicon substrate 1 between the 10-shaped silicon regions 41 and 42 with a gate oxide film 46 interposed therebetween.
And 431! A gate oxide film 4 is formed on a p-type silicon substrate 1 of I.
A gate electrode 18 made of polysilicon is formed through the gate electrode 6 . P-type silicon substrate 1, n-type silicon region 41, n-type silicon region 42, gate oxide film 46, and gate i! ! Ti17 constitutes a MOS transistor 28, and floating gate 1-'R pole 16 is connected to gate electrode 17. In addition, p-type silicon substrate 1 and n
The 10-shaped silicon region 42, the n-10 silicon region 43, the gate oxide film 46, and the gate N pole 18 constitute a MOS transistor 29. A drain voltage (VDD) is applied to the n1 type silicon region 41 from the terminal 9. Gate li!
The amplifier load voltage (VGL) is applied to m18 from the gate voltage input terminal 10. D1 type silicon region 111
43 is supplied with an amplifier source voltage (V, S), which is a ground voltage, from the terminal 11.

MO8I - transistor 28 converts the voltage of floating gate electrode 16 into a current, MO8I - transistor 29
is a negative transistor. Further, a gate oxide film 4 is formed on the p-type silicon substrate 1 between the n+-type silicon regions 44 and 45.
An output control gate electrode 19 is formed via 6,
The n4 type silicon region 42 is connected to the n+ type silicon region 44.

The p-type silicon substrate 1, the n-type silicon region 44, the n-type silicon region 45, the gate oxide film 46, and the output control gate electrode 19 constitute a MOS transistor 30 for output control. The output M control gate electrode 19 receives an input clock (V=oAN) from the scanning circuit from the gate voltage input terminal 12.
is given.

The n-type silicon region 45 is connected to the output terminal 13, from which a signal charge output is obtained.

FIG. 2 is a circuit diagram of the structure of one pixel in FIG. 1.

In the figure, the numbered parts correspond to the numbered parts in the ii diagram. The pn photodiode 21 corresponds to the pO photodiode region 20, and the signal charge storage region 22 corresponds to the n-type silicon region 2. In addition, the capacitor 48 is connected to the low-type silicon region 2 and the gate oxidation #Ii! 46 and floating gate electrode 16
Corresponding to the capacitor device consisting of the capacitor 4
9 is floating goo 1-'i @ pole 16 and oxide film 4
7 and a charge storage gate electrode 15. The DC power supply 50 is for supplying the :wr product gate voltage (V-T) to the gate voltage input terminal 6, and the DC power supply 50 is for applying the :wr product gate voltage (V-T) to the gate voltage input terminal 6. If! Reference numeral 51 provides a drain voltage (Voo) to the terminal 9, and a DC power supply 52 provides an amplifier load voltage (VaL) to the input terminals 10 to 10. Here, 33 is referred to as a signal processing circuit.

Next, the operation of this structure for one pixel will be explained. The incident light is color separated by the color separation filter 3a and then transmitted to the n+ type silicon region 3 via the gate oxide film 46! )j
i3-reru. The process in which the signal charge generated in the pn photodiode region 20 passes through the region under the charge transfer control gate electrode 14 and reaches the n-type silicon region 2, which is the signal charge 6M region, is similar to the Charoe-8kimmi described in the prior art.
Same as ng-Mode, n-type silicone region 2
The 4m charge m that is transferred to the top is the charge transfer 11. pn photodiode region 2 by lJ goo i~electrode 1・1
Since the potential of 0 is fixed at a constant potential, it is accurately proportional to the amount of incident light, and the potential of the region where signal charges are accumulated changes according to the accumulated signals@charges. At this time, the potential of the charge storage part 1 to the electrode 15 is changed from the storage part 1 to the voltage (Vs
y), the potential of the floating cable 1/electrode 16 is as shown in FIG. 8(a).

As explained in (b), it is determined by the potential of the region where the signal charges are multiplied by V1i. Therefore, by detecting the potential of the floating gate electrode 16, the amount of signal charge accumulated in the n"' type silicon region 2 can be detected. is connected to MO3I to the gate electrode 17 of the transistor 28, and the current flowing through the MOS transistor 28 is controlled by the DC power supply 51. At this time, the MOS transistor 2
9 acts as a load, and the current flowing through MO3I to transistor 28 is converted into a voltage, and this voltage is applied to the MOS transistor 3 used as a switching transistor.
When the input clock (v, cA, i) from the scanning circuit is applied to the gate electrode 19 of 0 from the gate voltage input terminal 12, the signal is output from the output terminal 3o as a signal@charge output.

Thus, in this example, Charoe −S k
Since the method of transferring signal charges from the photodiode region to the signal charge storage region in ivsing-Mode is used, excellent linearity is established between the incident light layer and the amount of signal charges, and furthermore, the floating gate electrode By detecting the potential, transfer efficiency and number of stages become a problem.
The signal charges generated in the photodiode region can be directly read out with high precision without using an OD, and more accurate image information can be obtained.

FIG. 3 is a diagram showing an example of the configuration of a linear image sensor in which a plurality of structures for one pixel in FIG. 1 are arranged in one line.

In the figure, 51 is a shift register, 21R is a pn photodiode with a color separation filter that transmits red, and 21G
is a pn photodiode with a color separation filter that transmits green; 21B is a pn photodiode with a color separation filter that transmits blue; 52R, 52G, and 52B are pn photodiodes, respectively.
Red signal 9 output line corresponding to photodiodes 21R, 21G, and 21B.

These are the green signal output line and the blue signal output line. The amount of light incident on each pO photodiode 21R, 21G, and 21B is detected with high accuracy using the method described above, each MOS transistor 30 is scanned with the output of the shift register 51, and the output of each signal processing circuit 33 is sequentially set for red color. Signal output line 52R9
Independent signals for each color are extracted from the green signal output line 52G and the blue signal output line 52B.

In this way, by dividing the signal output line for each color signal and using a scanning circuit to extract information about each pixel independently for each color, the external color signal The processing circuit can be simplified.

In the above embodiment, a one-dimensional image sensor having one row of light-receiving sections has been described, but the present invention can be applied to a one-dimensional image sensor or a two-dimensional image sensor having multiple rows of light-receiving sections.

In addition, in the above embodiment, the color separation filter is the primary color system R,
Although the case where G and B filters are used is shown, the color separation filter may be a complementary color filter or a complementary color filter including a transparent filter. In addition, regarding the array of color separation filters, even if it is a one-dimensional image array, two
x2 matrix as a unit ii! ii) Any array may be used as long as it is a prime array and has the same number of signal output lines as the number of types of color separation filters.

[Effects of the Invention] According to the present invention, a first semiconductor region of a second conductivity type is formed on the surface of a semiconductor substrate of a first conductivity type,
The first semiconductor region and the surrounding semiconductor substrate constitute a photodetection section that converts incident light into signal charges, and a color separation filter is formed on the first semiconductor region via an insulating film. , a second semiconductor region of a second conductivity type for accumulating signal charges from the photodetector is formed on the surface of the semiconductor substrate at a distance from the first semiconductor region; via an insulating film on the semiconductor substrate between the semiconductor regions,
A charge transfer control gate electrode whose potential is fixed at a first potential and which controls the movement of signal charges generated in the photodetector to a second semiconductor region is formed, and an insulating film is formed on the second semiconductor region. A charge storage part gate electrode whose potential is fixed at a second potential is formed between the second semiconductor region and the charge storage part gate electrode, and the amount of signal charge stored in the second semiconductor region is Since a floating gate electrode is formed for detecting , excellent linearity can be obtained between the amount of incident light and the amount of signal charge accumulated in the second semiconductor region. Further, the accumulated signal charge port can be detected by detecting the potential of the floating gate electrode, and the signal charge generated in the photodiode region can be directly read out with high accuracy without using a COD. Therefore, Charga-3kimn is not affected by COD transfer efficiency or the number of stages.
It is possible to obtain a solid-state imaging device that can read out signal charges with high precision by taking advantage of the ing-mode, and can simplify the external color signal processing circuit.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the structure of one pixel of a color solid-state imaging device according to an embodiment of the present invention. FIG. 2 is a circuit diagram of the structure of one pixel in FIG. 1. FIG. 3 is a diagram showing an example of the configuration of a linear image sensor in which a plurality of structures for one pixel in FIG. 1 are arranged in one line. Figure 4 shows the conventional Charae-8kllino-M
FIG. 2 is a cross-sectional view showing the structure of one pixel of a solid-state*a device that operates in ode mode. Figure 5 shows the structure of Charge-8 for one pixel in Figure 4.
FIG. 3 is a diagram illustrating the shavings of each part for explaining the kin+ming-mode operation. FIG. 6 is a diagram showing an example of the configuration of a linear image sensor in which a plurality of structures for one pixel in FIG. 4 are arranged in one line. FIG. 7 is a cross-sectional view showing a floating gate structure used in a CCD. FIG. 8 is a diagram for explaining changes in the potential of the floating gate electrode in the structure of the floating gate electrode 25--1 in FIG. 7. In the figure, 1 is a p-type silicon region, 2 is an n-type silicon region, 3.41 to 45 are n+-type silicon regions, 3a is a color separation filter, 14 is a charge transfer control gate electrode, 15
is a charge storage part gate electrode, 16 is a floating gate electrode, 17.18 is a gate electrode, 19 is an output control group 1
~electrode, 20 is pn7, t diode region, 21.
21R, 21G. 21B is a pn photodiode, 22 is a signal charge storage region, 23.25.28-30 is a MOS l-transistor, 33 is a signal processing circuit, 46 is a gate oxide layer, 47 is an oxide layer, 48.49 is a capacitor, 51 is a shift register, 52R is a red signal output line, 52G is a green signal output line, 52 B 1. This is the signal output line for the blue color. Note that the same reference numerals in each figure indicate the same or corresponding parts. Wow, Figure 2 33: IS Forklift Supervisor Lia, ff I←48.4
'l; Capacitor so, sl, s2: L:/L Ichishio,

Claims (2)

[Claims] (1) A structure for one pixel of a color solid-state imaging device, comprising: a semiconductor substrate of a first conductivity type; and a first semiconductor region of a second conductivity type formed on a surface of the semiconductor substrate; The first semiconductor region and the semiconductor substrate surrounding the first semiconductor region constitute a photodetection section that converts incident light into signal charges, and is formed on the surface of the semiconductor substrate at a distance from the first semiconductor region. a second semiconductor region of a second conductivity type for accumulating signal charges from the photodetection section; a color separation filter formed on the first semiconductor region with an insulating film interposed therebetween; is formed on the semiconductor substrate between the first semiconductor region and the second semiconductor region via an insulating film, the potential of which is fixed at the first potential, and the second semiconductor region of the signal charge generated in the photodetector is a charge transfer control gate electrode for controlling transfer to the semiconductor region; and a charge storage gate electrode formed on the second semiconductor region via an insulating film, the potential of which is fixed at the second potential. . A color solid-state imaging device, comprising: a floating gate electrode formed between the second semiconductor region and the charge storage section gate electrode for detecting the amount of signal charge accumulated in the second semiconductor region. (2) Further, a third semiconductor region of a second conductivity type formed on the surface of the semiconductor substrate at a distance from the second semiconductor region; and a third semiconductor region of a second conductivity type formed on the surface of the semiconductor substrate at a distance from the third semiconductor region. a fourth semiconductor region of a second conductivity type formed apart from each other; and another gate electrode formed on the semiconductor substrate between the third semiconductor region and the fourth semiconductor region with an insulating film interposed therebetween. The color solid-state imaging device according to claim 1, further comprising: the floating gate electrode being connected to the other gate electrode.