JPS62290987A - Testing system for ic card - Google Patents

Abstract

PURPOSE:To point out the position of errors at the time of testing an IC card by executing various tests on LSI constituting an IC card, storing the result of each test, and at the same time, displaying the content of memory in a displaying means. CONSTITUTION:In testing LSI operation of an IC card 5, data errors in a system program ROM 55 and a test program ROM 54, reading/writing errors of data in a storage memory 64, errors of various function for various instructions etc. stored corresponding to each bit of error data ED, and at the same time, the content of memory is displayed in the display unit of a terminal. Thereby, the position of errors can be pointed out simply, and the errors can be dealt with promptly.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to an IC card testing method that makes it possible to identify error locations during an IC card test 1-.

[Prior art and its problems] In recent years, it has been called the cashless era, and it has become possible to purchase products without handling cash by using cards issued by credit card companies. There is.

Conventionally, cards used include plastic cards, embossed cards, and magnetic striped cards, but these cards are easy to forge due to their structure, so unauthorized use has become a problem.

In order to solve this problem, information cards, so-called IC cards, have been developed in which an IC circuit that stores a personal identification number and the like is built into the card so that the personal identification number cannot be easily read from the outside.

Incidentally, such an IC card stores an LSI having a system program ROM, a test program ROM, a storage memory, etc., but the bit pattern states stored in these program ROMs and the writing/continuation of data in the storage memory are Operations etc. must always be maintained normally, and for this reason, it is necessary to be able to conduct tests for each type of equipment.

Therefore, conventional IC cards store a test program, and by executing this program, a predetermined test can be performed.

However, conventionally, when an error is discovered during various tests on an LSI, the error is treated as an error in the entire card, making it difficult to identify the location of the error. For this reason, no action can be taken to deal with the error at this time, and even if the error is simple, the entire IC card may become unusable.

[Purpose of the Invention] This invention has been made in consideration of the above-mentioned circumstances, and provides an IC card testing method that can identify error points during IC card testing and quickly take measures against errors. The purpose is to

[Summary of the Invention] The IC card testing method according to the present invention is an IC card having an IC card and a terminal to which the card is installed.
LSI that constitutes an IC card in a card system
Various tests are executed for each test, and the results of each test are stored in correspondence with each bit of error data consisting of a plurality of dot codes, and the stored contents are displayed on the display means of the terminal.

[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

First, Figure 1 shows the terminal 1 where the IC card 5 is installed.
This shows the circuit configuration of 0. In the figure, 11 is a system bus, and this system bus 11 includes a sound controller 12, a working RAM 13, a system program ROM 14, a terminal attribute ROM 15, an initial parameter RAM 16, and a main controller 17.
, display drive controller 18, key controller 1
9, a reader/writer controller 20, a comparator 21, an input/output controller 22, an output buffer 24 via an output controller 23, and an input controller 26 via an input buffer 25 are connected, respectively.

A speaker 27 is connected to the sound controller 12 and outputs an alarm sound as necessary.

The working RAM 13 stores error data rEDJ sent from the IC card side in the memory area, as well as IPAN
j, rcHNJ, rEPDJ, etc., and various processing data within the terminal are also stored.

The system program ROM14 is an ENQ for matching with IC cards as well as various system programs.
It has codes etc.

The terminals R◯ to 115 store terminal codes TC (for example, manufacturing code, issue code, store code, etc.) according to their uses.

Initial parameter RAM 16 stores answer-to-reset data from IC card 5 all at once. This initial parameter RAM 16 contains the transmission line 16.
Output controller 23, input controller 2 via a
6, a vpp level latch section 28, a VDP timer latch section 29, and an lpp level latch section 30 are connected, and these latches 28, 29, and 30 are connected to the corresponding vpp power supply 31
, VI) A p timer 32 and an Ipp limiter 33 are connected.

Here, the vpO power supply 31 is used to secure the voltage ■pp used for writing data to the data memory of the IC card. Further, the Vpp timer 32 is used to secure the maximum Vpp power application time specified by the IC card 5. Further, the Ipp limiter 33 determines the permissible value of the data write current.

In this case, the maximum data write voltage by the Vpp power supply 31, the ■pp application time by the Vpp timer 32, the maximum allowable data write current by the Ipp limiter 33, etc. are determined by the answer-to-reset data stored in the initial parameter RA\11G. Set based on

An IC card operating frequency selector 34 is connected to the data transmission line 16a. An oscillation signal from an oscillator 35 is supplied to this selector 34 via a frequency divider 36.
It is output from the C1''ock terminal as a signal with the operating frequency set.

A comparator 21 and an input/output controller 22 are connected to the system control line 17a of the main controller 17.
Main controller 1-○-ra 17 depending on the operating status of the system.
Control commands are sent to each circuit from

The display drive controller 18 controls the display on the display section 3 of the terminal 10.

The key controller 19 is the keyboard 2 of the terminal 10
A key human input signal is detected by giving a sampling signal to the key.

The reader/writer controller 20 drives and controls the reader/writer i structure 38. Here, the structure section 38 is equipped with a card transport motor, and transports the IC card 5 inserted from the card insertion slot of the terminal to a predetermined position, electrically connects the card to the terminal 10, and performs a predetermined process. When the process is completed, the IC card 5 is returned to the card insertion slot.

Such a reader/writer mechanism section 38 has an output buffer?
24, reset controller 39, IDp level latch section 30, operating frequency selector 34, VCC electric it! 40
is connected. These output buffer 24, reset controller 39, lpp level latch unit 30. Operating frequency selector 34, Vcc electric it! I10 terminals connected to the IC card 5 side corresponding to 40, Re5e
terminal, vpp terminal, CIock4 child, 'J c
It has a c terminal.

The input controller 26 and the output controller 23 control data exchange with the IC card in accordance with commands from the main controller 17 via the initial parameter RAM 16. Among these, the input controller 26 outputs the data sent from the IC card to the working RAM 13 etc. via the input buffer 25 and also provides it to the comparator 21, and provides the comparison output here to the main controller 17. Further, the output controller 23 sends data given from the terminal attribute ROM 15 or the like to the IC card 5 via the output buffer 724.

The input/output controller 22 sends and receives encrypted data when a database, ie, a host computer, is connected online.

Next, FIG. 2 shows the circuit configuration of the IC card 5. As shown in FIG. In the figure, 51 is a system bus, and this system bus 51 carries answer-to-reset data ROfv.
152, application ROM 53, test program ROM 54, system program RO~155, working RA~156, central controller 57, storage memory read/write controller 58, decryption calculator 59, input controller 61 via input buffer 60, output buffer Output controllers 63 via 62 are connected respectively. Further, a data input/output terminal I10 is connected to the input/output controller 61 and the output controller 63.

Here, Answer to Reset 1-Data RO~152
is all operating conditions for the IC card 5 itself (e.g. data writing, applied voltage, current permissible value and maximum applied voltage,
Maximum data transmission amount, maximum response waiting IFJ interval, etc.) are stored, and after the card's internal initialization is completed, these condition data are sent to the terminal side as answer-to-reset data in a predetermined format. It is set to be sent.

The application ROM 53 stores card type data rAPNJ indicating what type of IC card 5 this card type data is.
After setting the initial parameters based on the two-reset data, the data is sent in a predetermined format when exchanging the data with the terminal side.

Test programs RO to 154 store programs for various tests of cards.

The system program ROM 55 contains various system programs as well as a code signal rAcKJ or rNA indicating whether the signals transmitted and supplied from the terminal side are correct or not.
I am improving my cj. Also, this system program RO
M55 stores data <N+1> used for a write test of the storage memory 64, which will be described later.

The working RAM 56 stores various processing data within the card. In this case, error data ED consisting of an 8-bit code as shown in FIG. 3 is stored. Here, the code contents of the error data ED are as follows:
bl indicates a data error in the system program ROM 55, b2 indicates a data error in the test program ROM 54, b3 indicates a data read error in the storage memory 64 (described later), and b4 indicates a data write error in the storage memory 64. bit, b
5 indicates a card function error, and b6-b
8 is an unused bit.

The central controller 57 outputs operation commands to each circuit according to the data reception signal transmitted and supplied via the input buffer 60 and the operation state.

The storage memory read/write controller 58 controls three-in-one data reading from the storage memory 64 in response to commands from the central controller 57.

In this case, the storage memory 64 includes a zone address table 641, a public zone 64 as shown in FIG.
2, a secret zone 643, a transaction zone 644, and a credit zone 645. Here, the zone address table 641 stores an address of a predetermined zone as test data used for card authentication, for example, and extracts verification data from the predetermined zone based on the address, and also extracts verification data from the predetermined zone based on the address and performs verification on the card by comparing with the test data. Authentication is now performed. The public zone 642 includes a test area 642 for executing write/read tests on the storage memory 64.
It has a. Here, such test area 642a
For example, as shown in FIG. 5, r2 . J, .
RT N J (Re −T ryN u m b
er), number r until PINJ is used
lPINJ (In l tia l zat 1
onPersonal 1dentificatio
n Number), account number IF'ANJ (P
primary ACCOUNT Number), decryption code rPRKJ (PrivateK e
yCode) etc. are stored. The transaction zone 644 stores various data related to general transactions. Credit zone 645 stores data regarding credit transactions.

Returning to FIG. 2, the decryptor 59 decrypts the code based on a predetermined algorithm, and uses the decryption code fPRKJ from the storage memory 64 from the terminal side via the manual buffer 6o. It is designed to decode input data provided by

A timer 65 is connected to the central controller 57. This timer 65 is used to preset the time required for correct/incorrect processing of the card=W to a predetermined time.
It is set by a command from the central controller 57 before inputting the INJ, and counting is started when the input of the PIN number IPINJ begins, and after a predetermined time elapses, the central controller 57 is interlocked.

- The contents of the storage memory 64 read by the storage memory read/write controller 58 are applied to one input terminal of the comparator 66. The other input terminal of the comparator 66 is supplied with input data decrypted by the decryptor 59, data stored in the working RAM 56, a specific code stored in the data ROM 52, and the like. The comparison output of this ratio if 566 is the central controller 5
Sent to 7.

It should be noted that while the IC card 5 thus constructed is attached to a terminal TO (not shown), the reset signal Re5et and the system clock clock are supplied from the terminal 10 side, and the Vcc power supply and the Vpp power supply are connected. Here, the VCC power supply is 1! for system drive. f[, Vp
The p1 source is a power supply for loading the storage memory 64, and its N source voltage is applied to the terminal 10 based on the answer-to-reset data stored in the data ROM 52.
IlI! It is set in I. On the other hand, system clock c
A system operation signal from the lock is supplied to each circuit via a frequency divider 67.

Next, the operation of the embodiment configured as described above will be explained according to the flowcharts shown in FIGS. 6 and 7.

First, in order to perform a test, the IC card 5 is attached to the terminal 10. In this state, when the test mode of the IC card 5 is inputted from the keyboard 2 of the terminal, a test start command is read from the system program ROM 14 in response to a command from the main controller 17, and the IC card is Sent to card 5. In the IC card 5, this test start command is input into the working RAM 56 via the input controller 61 and the input sofa 60.

When the central controller 57 determines that it is a test start command, answer-to-reset data is read out from the answer-to-reset data ROM 52 in step A1 (not shown in FIG. 6), and the input buffer 62 and output It is sent to the terminal via the controller 63 from the I10 terminal. In this case, in the terminal,
A predetermined time is set to wait for the answer-to-reset data to be sent from the IC card 5, and if the data is not returned within this time, a test start command is issued again. and multiple times, e.g. 3
Even if the command is issued repeatedly, the answer-to-reset
If the data is not returned, it will be treated as a card function error.

Now, as shown in step A1, when the answer-to-reset data is sent to the terminal 10, the IC card 5 enters the test mode.

As a result, first, in step A2, data in the system program ROM 55 is read in byte units. Then, these data are sequentially subjected to logical operations, and in step A3, it is determined whether the data obtained by these operations correspond to a predetermined value. Here, if it is equal to the predetermined value, proceed to step A4, but if it is not equal to the predetermined value,
It is determined that there is an error in the data in the system program ROM 55, and the process proceeds to step A5. In this step A5, bit b of the error data ED of the working RAM 56 is read by a command from the central controller 57.
1 is set as a flag "1".

In this case as well, the process proceeds to step A4.

In step A4, the test program ROM 54 is
Read data in bytes. Then, these data are sequentially subjected to logical operations, and in step 86, it is determined whether the data obtained by these operations correspond to a predetermined value. Here, if it is equal to the predetermined value, step A
If the value is not equal to the predetermined value, it is determined that there is an error in the data in the test program ROM 54, and the process proceeds to step A8. In this step 88,
Working R by command from central controller 57
Flag “1” is set in bit b2 of error data ED of AM56.
” will be erected. In this case as well, the process proceeds to step A7.

Next, in step A7, data is sequentially read from the test area 642a in the public zone 642 of the storage memory 64. In this case, data is read from the test area 642a in the order of "1", "2", "3", ... rNJ, and it is determined in step A9 whether all of these data have been read correctly. do. Then, if everything is read correctly, step A
The process proceeds to IO, but if the data is not read correctly, it is determined that there is an error in reading data from the straight memory 64, and the process proceeds to step A11. In this step A11, the working RA is
Flag “1” in bit b3 of error data ED of M56
is erected. In this case as well, the process proceeds to step A10.

In step AIO, data (N
+1> is read and this data is stored in the storage memory 64.
(N+1) of the test area 642a in the public zone 642 of . Thereafter, in step A12, the public zone 6 of the storage memory 64 is
The data written in the test area 642a (<N+1) in 42 is read out immediately. And step A13
Then, it is determined whether the read data and the four-way data are equal. Here, if the two are equal, step A1
4, but if they are not equal, it is determined that there is an error in data writing to the straight memory 64, and the process advances to step A15. In step A15, the working RAM 56 is
A flag "1" is set in bit b4 of the error data ED. In this case as well, the process proceeds to step A14.

In step A14, various instructions are read from the system program ROM 55 in response to instructions from the central controller 57, and the results of their execution are determined in step A16.

Here, if the execution results for the various instructions are correct, proceed to step A17, but if not, the card 1! The process proceeds to step A18 as a function error. In this step A18, the central controller 5
The error data E in the working RAM 56 is
A flag "1" is set in bit b5 of D. and,
In this case as well, the process proceeds to step A17.

In step A17, the error data ED from the working RAM 56 is read out and sent to the terminal 10 via the output buffer 62 and output controller 63.

The terminal 10 receives the error data ED sent from the IC card 5 via the input controller 26 and the input buffer 25, and writes it to the working RAl'v 113 as shown in step B1 in FIG. Then, proceed to step B2.

In this step B2, the content of the error data ED in the working RAM 13 is determined by the main controller 17, and the result is sent to the display drive controller 18 and displayed on the display section 3. In this case, the display content on the display section 3 will be in accordance with the state of each bit b1 to b5 of the error data ED, and the results of various tests will be displayed.

Therefore, if you do this, the LSI of the IC card 5
In the I production test, data errors in system programs RO to 1 and test program ROM, data read/write errors in storage memory, and various function errors for various instructions are detected for each bit of error data ED. At the same time, the stored contents are displayed on the display section of the terminal, so that the location of the error in the LSI can be easily identified. This makes it possible to take prompt action against errors, and it is possible to avoid a situation where the entire IC card becomes unusable even if the error content is simple, unlike in the conventional case.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but can be implemented with appropriate modifications without changing the gist.

[Effects of the Invention] According to the present invention, it is possible to identify an error location during an IC card test, and it is possible to promptly take measures against the error.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the circuit configuration of a terminal used in one embodiment of the present invention, Figure 2 is a block diagram showing the circuit configuration of an IC card used in the same embodiment, and Figure 3 is a block diagram showing the circuit configuration of an IC card used in the same embodiment. A diagram showing the configuration of error data ED included in the working RAM of the IC card, FIG. 4 is a diagram for explaining the storage memory used in the same embodiment, and FIG. 5 is a diagram showing the test area in the public zone of the storage memory. The figures for explanation, FIGS. 6 and 7, are flowcharts for explaining the operation of the embodiment. 3... Display unit, 5... IC card, 10... Terminal, 13... Working RAM 117... Main controller, 54... Test program ROM,
55... System program ROM, 56... Working RAM, 57... Central controller, 6
4...Storage memory, 642...Public zone, 642a...Test area. Figure 3 Figure 4 Figure 5 Figure 7

Claims (1)

[Claims] In an IC card system having an IC card and a terminal to which the card is installed, various tests are executed on the LSI that constitutes the IC card, the results of each test are stored, and the stored contents are displayed on the display means of the terminal. An IC card test method characterized by: