JPS62290940A - Emulator device for microprocessor - Google Patents

Emulator device for microprocessor

Info

Publication number
JPS62290940A
JPS62290940A JP61134630A JP13463086A JPS62290940A JP S62290940 A JPS62290940 A JP S62290940A JP 61134630 A JP61134630 A JP 61134630A JP 13463086 A JP13463086 A JP 13463086A JP S62290940 A JPS62290940 A JP S62290940A
Authority
JP
Japan
Prior art keywords
emulator
signal line
information communication
power supply
developed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61134630A
Other languages
Japanese (ja)
Inventor
Hideo Takagi
英雄 高木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP61134630A priority Critical patent/JPS62290940A/en
Publication of JPS62290940A publication Critical patent/JPS62290940A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To prevent occurrence of a latch-up phenomenon of an input buffer having a CMOS structure of the communication part of a development subject device, by setting a signal line set between an emulator device and the information communication part of the development subject device under an unconnection state when the main current of the development subject device is turned off and then in a connection state when said current is turned on. CONSTITUTION:A main power supply state detecting part 6 of a development subject device 2 detects the ON/OFF states of the power supply of the subject device 2. When said power supply is set in an ON state, an active signal is outputted to a signal line control part 5 set between an information communication part 3 of an emulator device 1 for microprocessor and an information communication part 4 of the device 2 via a control part 7. Thus a signal line 8 is activated and therefore an input buffer of the part 4 never produces a latch-up phenomenon. While an inactive signal is applied to the part 5 if the power supply of the device 2 is set under an OFF state. Thus the line 8 has a high impedance and therefore the latch-up phenomenon is avoided for the input buffer of the part 4.

Description

【発明の詳細な説明】 ３、発明の詳細な説明 〔産業上の利用分野〕 本発明はマイクロ・プロセッサ用エミュレータ装置に関
し、特に対象プロセッサがＣＭＯ８構造の場合の安全性
改善の分野に関する。Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an emulator device for a microprocessor, and particularly to the field of improving safety when the target processor has a CMO8 structure.

〔従来の技術〕[Conventional technology]

従来、この種のマイクロ・プロセッサ用エミュレータ装
置は開発対象装置側のエミュレータ部と直接接続される
素子を考慮した設計はなされていなかった。Conventionally, this type of microprocessor emulator device has not been designed with consideration given to elements that are directly connected to the emulator section of the device under development.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のエミュレータ装置は、開発対象装置のエ
ミュレータ部と直接接続される素子が０ＭＯ８である場
合、エミュレータ装置の電源を開発対象装置側の電源よ
り早く投入した場合、エミュレータ側からの出力信号線
がハイレベルであると開発対象装置側が電源未投入状態
において該Ｃ５ｔｏｓ素子がラチアップ現象を起し破壊
する可能性がある。また投入順序が逆の場合、開発対象
装置側からの出力信号線がハイレベルであると、エミュ
レータ側の入力素子がＣＭ　ＯＳである場合、エミュレ
ータ側の入力素子が破壊される可能性がある。In the conventional emulator device described above, if the element directly connected to the emulator section of the device to be developed is 0MO8, and if the power to the emulator device is turned on earlier than the power to the device to be developed, the output signal line from the emulator side If it is at a high level, there is a possibility that the C5tos element will cause a latch-up phenomenon and be destroyed when the device to be developed is not powered on. Furthermore, if the input order is reversed and the output signal line from the device under development is at a high level, there is a possibility that the input element on the emulator side will be destroyed if the input element on the emulator side is a CMOS.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のエミュレータ装置は、開発対象装置の［首の投
入、未投入を検出する手段と該開発対象装置と直接接続
される信号線を上記検出手段に二り制御する手段を有し
ている。The emulator device of the present invention has means for detecting whether the device to be developed is turned on or not, and means for controlling a signal line directly connected to the device to be developed to the detection means.

〔実施例〕〔Example〕

次に本発明について第１図を参照して説明する。 Next, the present invention will be explained with reference to FIG.

第１図は本発明の一実施例である。１はマイクロ・プロ
セッサ用エミュレータ装置、２は開発対象装置である。FIG. 1 shows an embodiment of the present invention. 1 is a microprocessor emulator device, and 2 is a device to be developed.

エミュレータ装置ｉｉｌ：は開発対象装置の主電源状態
検出部６と制御部７と信号線制御部５と情報通信部３と
エミュレータ主装置１０とによって構成されている。The emulator device iil: is composed of a main power state detection section 6, a control section 7, a signal line control section 5, an information communication section 3, and an emulator main device 10 of the device to be developed.

次にその動作を説明する。一般エミュレータ装置におい
ては、エミュレータ装置の電源を開発対象装置の電源よ
り常に先に投入する場合、エミュレータ装置内の０ＭＯ
８構造を持つ情報通信部の入力バッファは破壊されない
。しかし、開発対象装置の情報通信部の入力バッファは
マイクロ・プロセッサ・エミュレータ装置の情報通信部
からの信号が入る為該入カバ、ファがラッチアップ現象
を引き起こす。Next, its operation will be explained. In a general emulator device, if the power of the emulator device is always turned on before the power of the device to be developed, the 0MO inside the emulator device
The input buffer of the information communication section having an 8-structure is not destroyed. However, since the input buffer of the information communication section of the device to be developed receives a signal from the information communication section of the microprocessor emulator device, the input buffer causes a latch-up phenomenon.

そこで、開発対象装置の主電源状態検出部６で開発対象
装置の電源′″ＯＮ”　、”ＯＦ’Ｆ“状態を検出する
。Therefore, the main power state detection unit 6 of the device to be developed detects the power ``ON'' and ``OFF'' states of the device to be developed.

開発対象装置の電源が１ＯＮ“状態であれば、制御部７
によりマイクロ・プロセッサ用エミュレータ装置の情報
通信部３と開発対象装置の情報通信部４の間にある信号
線制御部５にアクティブ信号を出力し信号線８をアクテ
ィブにする。この結果、開発対象装置の情報通信部の入
力バッファはラッチアップ現象を引き起こさない。If the power supply of the device to be developed is in the “1ON” state, the control unit 7
This outputs an active signal to the signal line control section 5 located between the information communication section 3 of the microprocessor emulator device and the information communication section 4 of the device to be developed, thereby activating the signal line 8. As a result, the input buffer of the information communication section of the device to be developed does not cause latch-up phenomenon.

開発対象装置の電源が１ＣＪ　Ｆ　Ｆ“状態であれば、
ＯＮ“状態の時とは逆に、上記信号線制御部５にインア
クティブ信号を出力し、信号線８をハイ・インピーダン
スにする。こｎにより、開発対象装置の情報通信部の入
力バッファのラッチアップ現象を防止する事ができる。If the power supply of the device to be developed is in the 1CJ F F state,
Contrary to the "ON" state, an inactive signal is output to the signal line control section 5, and the signal line 8 is set to high impedance.This causes the latch of the input buffer of the information communication section of the device to be developed. Up phenomenon can be prevented.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発８Ａは、マイクロ・プロセッサ
用エミュレータ装置と開発対象装置の情報通信部の信号
線を開発対象装置の主電源がゝゝＵ　ＦＦ“の時に電気
的に未接続状態にし、ゞＯＮ”の時に接続状態にするこ
とによシ開発対象装置の上記通信部の０ＭＯ８構造をも
つ入カパノファがラッチアップ現象を引き起こす事を防
止する効果がある。As explained above, in the present invention 8A, the signal line of the information communication section of the microprocessor emulator device and the device to be developed is electrically disconnected when the main power supply of the device to be developed is “U FF”. By setting the connection state when "ON", there is an effect of preventing the input capacitor having the 0MO8 structure of the communication section of the device under development from causing a latch-up phenomenon.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明のマイクロ・プロセッサ用エミュレータ
装置のブロック図である。 １・・・・・・マイクロ・プロセッサ用エミュレータ装
置、２・・・・・・開発対象装置、３・・・・・・情報
通信部、４・・・・・・情報通信部、５・・・・・・信
号線制御部、６・・・・・・開発対象装置の主電源状態
検出部、７・・・・・・制御部、８・−・・・・信号線
、９・・・・・・開発対象装置の主電源、１０・・・・
・・マイクロ・プロセッサ用エミュレータ主装置。 λｔ　　　　１ゝ１FIG. 1 is a block diagram of an emulator device for a microprocessor according to the present invention. 1... Microprocessor emulator device, 2... Development target device, 3... Information communication department, 4... Information communication department, 5... ... Signal line control section, 6... Main power state detection section of the device to be developed, 7... Control section, 8... Signal line, 9... ...Main power supply of the device to be developed, 10...
...Main device of emulator for microprocessor. λt 1ゝ1

Claims (1)

【特許請求の範囲】[Claims] 開発対象装置の電源の投入、未投入を検出する手段と該
開発対象装置と直接接続される信号線を上記検出手段に
より制御する手段を有する事を特徴とするマイクロ・プ
ロセッサ用エミュレータ装置。1. An emulator device for a microprocessor, comprising means for detecting whether the power of a device to be developed is turned on or not, and means for controlling a signal line directly connected to the device to be developed by the detection means.
JP61134630A 1986-06-09 1986-06-09 Emulator device for microprocessor Pending JPS62290940A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61134630A JPS62290940A (en) 1986-06-09 1986-06-09 Emulator device for microprocessor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61134630A JPS62290940A (en) 1986-06-09 1986-06-09 Emulator device for microprocessor

Publications (1)

Publication Number Publication Date
JPS62290940A true JPS62290940A (en) 1987-12-17

Family

ID=15132863

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61134630A Pending JPS62290940A (en) 1986-06-09 1986-06-09 Emulator device for microprocessor

Country Status (1)

Country Link
JP (1) JPS62290940A (en)

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