JPS62286311A - Pulse processing circuit - Google Patents

Abstract

PURPOSE:To operate the titled circuit without deteriorating the accuracy of reproduction from a DC to a high frequency in the order of MHz from a low to a high level by differentiating an input wave, amplifying the result, giving the result to a slice circuit while giving a proper time constant so as to form a correction pulse for the leading, or trailing or the both. CONSTITUTION:A bias of a differentiation amplifier 5 is set so as to slice only the leading waveform among differentiation waveforms produced by the differentiation amplifier 5, and the output of the slicer and the output of a DC amplifier 2 are ORed to correct the wave. The pulse width of the correction pulse depends on a capacitor 12, a resistor 11 and an input resistance including a resistance Rf of an amplifier element 14 used for the differentiation amplifier. Further, an unbuffer type CMOS inverter is used for the DC amplifier element and if an input bias is not easily applied, a midpoint bias is applied by providing a negative feedback resistor.

Description

Detailed Description of the Invention 2. Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a pulse processing circuit that amplifies weak pulse signals and shapes waveforms, and particularly relates to pulse processing circuits that handle pulse signal levels. This relates to a pulse amplifier that requires a wide range.

(Prior art) Most of the prior art that is closest to this invention uses an operational amplifier to amplify the signal to a certain level, and then uses a comparator to shape the pulse waveform. The principle is the same. Furthermore, as a more advanced type, there is a type with an ATC circuit that automatically changes the comparison standard of the comparator up and down depending on the magnitude of the input.

On the other hand, some are equipped with AGC, which changes the gain of the pulse amplifier depending on the magnitude of the input and keeps the output constant. Outside of this,
There is also a DC feedback type to reduce the drift of DC amplifiers.

(Problems with the prior art) As mentioned above, many types of pulse amplifiers have been developed, but a common problem is the reproduction of pulse widths from DC to high frequencies on the order of MHz, from low levels to high levels. It is difficult to operate without reducing accuracy. In order to simultaneously achieve these conditions, at present most amplifier elements (DC amplifier circuits) that require dual power supplies are used, and the circuit size also increases significantly. Recently, in order to meet the demand for a single power supply, low voltage, and low power consumption in order to realize the miniaturization of electronic devices, it has only partially satisfied the necessary conditions. For example, limiting the frequency to a low range to make it more resistant to level fluctuations.
The question becomes whether to select the opposite conditions or compromise the pulse width accuracy. For example, even with AGO and ATC devices that are thought to be advancing in the current amount, there is a temporary unstable period from when the pulse stops to when the signal starts. This is natural because it is based on the operating principle that a pulse is input, its level is checked, and control begins.

Even during this period, bit errors cannot be tolerated, and as a countermeasure, the circuit must be complicated or delicate adjustments must be made. or,
If a device without these control functions sufficiently amplifies the low-level signal and adjusts it to create a pulse, when a high-level signal enters the amplifier, the amplifier will become saturated, the waveform will be distorted, the pulse width accuracy will decrease, and the In such cases, pulse regeneration becomes impossible.

(Means for Solving the Problems of the Present Invention) The pulse processing circuit of the present invention is intended to comprehensively solve the above problems.

The configuration and operating principle of the present invention are as follows. The basic element is a DC amplifier that operates up to high frequencies.
Amplify as much as N allows to reach the saturation region of the amplifier. Therefore, the amplifier element is preferably an FKT amplifier.
Those that operate in current mode, such as bipolar, are not suitable. When high gain amplification is performed in this way, the waveform deteriorates.

That is, since either the rising portion, the falling portion, or both are blunted, if this portion is included in the slice, the pulse width will be inaccurate. Therefore, it is necessary to correct this pulse width by some method.

This is accomplished by differentiating and amplifying the input wave, giving it an appropriate time constant, and inputting it into a slice circuit to create correction pulses for rising or falling, or both. This is converted into the above-mentioned main pulse (amplified by a DC amplifier,
Then, it is corrected by combining it with the sliced pulse). At this time, whether to correct the rising edge, the falling edge, or both depends on where the 0 level of the input signal is within the operating range of the DC amplifier. In the case of the configuration shown in Figure 2, the 0 level of the input signal (no signal level) is slightly on the VDD side from the center of the operating range, and if the pulse is generated downward (toward the ground side), the rising edge of the pulse, that is, the ground side. Waveform deterioration tends to occur at points of change from VDD to VDD, and vice versa, as the gain of the DC amplifier increases, waveform deterioration tends to decrease. Therefore,
Only the rising edge correction needs to be performed, and the bias of the differential amplifier is set to slice only the rising edge of the differential waveform generated by the differential amplifier, and the output of this slicer and D
It is corrected by ORing the output of the C amplifier. When waveform accuracy (pulse width accuracy) is more strongly required or when the input pulse waveform has a large degree of droop, waveform correction for both the rise and fall of the pulse is performed as in the configuration shown in FIG. In this case, a sixth differential amplifier is added to the pulse whose rising edge has been corrected using the configuration shown in FIG. 2, and the bias point of the differential amplifier is selected so that only the falling waveform is sliced. That is, as shown in FIG. 3, a bias point setting resistor is connected between VDD and the input, and an appropriate resistance value t is selected. Then, AND the output of this third block and the final output shown in FIG.
By putting it into a circuit and making its output the final output, correction of both sides of the pulse is achieved and the complete pulse waveform is reproduced.

Further, the width of these correction pulses needs to be larger than the width of the signal pulse at the DC amplifier. Also, the larger limit of the time constant is selected within a range that does not deteriorate the frequency characteristics of the differential capacitor or amplifier used.

The pulse width of this correction pulse is determined by the input resistance including C1, R1, and Rf of the amplifier element used in the differential amplifier in FIG. When R1 is sufficiently large, R
The correction pulse width can be found from the time constant formed by the product of C1 and the value obtained by dividing f by the amplification degree of the amplifier element. Conversely, the predetermined value of C1 is determined based on this relationship.

(Example) FIGS. 2 and 6 show an embodiment of the present invention.

The signal sources shown in FIGS. 2 and 3 are often connected to an arbitrary signal source via an impedance reduction circuit, output from the signal source, and then branched. Further, the DC amplifier element uses a C-MO8 unbuffered inverter, and if it is difficult to apply an input bias, a negative feedback resistor is inserted to apply a midpoint bias. In FIGS. 2 and 3, it is assumed that the output point of the signal source is biased at a midpoint, and the DC amplifier has no feedback. Also, if the gain is insufficient for both the DC amplifier and the differential amplifier, stack the stages. After the slicer, an inverter and a NAND gate may be used instead of an OR gate. or,
The OR gate may be configured with a diode coupler, and finally an inverter may be used to configure the waveform shaping and output buffer. In both Figures 2 and 3, the bias point adjustment is R, , R2,
Perform with R3.

(Effects of the Invention) The present invention based on the above-described configuration and operating principle exhibits great effects that could not be achieved conventionally in the following respects.

First, it operates with a single power supply of 5V or less, and is DC to several M
It has a bandwidth up to H2, and can suppress power fluctuations of 20 dB or more to pulse width fluctuations of ±10 cm or less. Moreover, since waveform processing is performed for each pulse, the rise from rest and level It works regardless of sudden changes.

Moreover, if the configuration of the present invention is adopted, first of all, the popular C-MO8FE
A T element can be used, the power supply voltage can operate from 5V to 2V, and a single power supply is required. Also, if a C-MO8FET is used, the power consumption is naturally low, and the logic element can also be configured on one chip.

In addition, in order to compensate for the time delay due to waveform distortion with the differential waveform,
The system delay becomes extremely small, making it easier to create loops. Drops in the waveform in the DC amplifier due to level fluctuations are compensated for by the differential waveform, and up to the minimum signal pulse width are not affected by the level at all. The frequency characteristics are also C! - It can demonstrate the full performance of MOSFET, and can be used as a 50 ns high-speed C-MOS with an unbuffered inverter of conventional C-MOS logic.
It operates up to a speed of about 1 Qns. In terms of baud rate conversion, assuming a pulse width accuracy of ±10%, the former is 2M baud and the latter is 10M0M baud. The usable level fluctuation range is 2 Q dB in power in the prototype.

[Brief explanation of the drawing]

FIG. 1 is a basic system block diagram of the present invention.
) is a basic system block diagram when correcting one edge of the pulse, FIG. 1(b) is a basic system block diagram when correcting both edges of the pulse, and FIG. 2 is an embodiment of the present invention. In this case, the diagram showing the case of correcting the rising edge, FIG. 3, is also an embodiment of the present invention, and in this case, it shows the case where both edges are corrected. 1... Pulse waveform signal source, 2... DC amplifier, 3...
Slicer, 4...Logic circuit (OR function), 5...Differential amplifier, 6...DC amplifier element, 7...Differential amplifier (with different operating point from 5), 8...Slicer (3 or 6 ), 9... Logic circuit different from 4, 10... DC amplifier element, 11... Bias point setting resistor R+, 12... Differential capacitor C1, 13... Bias setting resistor R2, 1
4... Negative feedback resistor Rf, 15... Power supply point (VDD
), 16... Ground point, 17... Bias point setting resistor R3, 18... Logic circuit (AND function), 19
・・Signal output point, 20・・Differential capacitor C2, 21・
・Slicer (separate from 6 for DC amplifier). Patent applicant Hirios Co., Ltd. No. 10

Claims (1)

[Claims] 1. The output of the signal source (1) that outputs a signal with a pulsed waveform is branched into two or three branches, one of which is connected to a DC amplifier (2), and the other is connected to a differential amplifier (input). An amplifier that produces an output close to a waveform with a slight waveform) (5) or (5) and (7), and a slicer (that always produces the highest level output when the input signal is higher than a certain level) at the subsequent stage of each. , a circuit that produces the lowest level output when it is low) is connected, and each output is passed through a logic circuit (4) or (a) to have one or more outputs. 2. In claim 1, the DC amplifier (2) is defined as D
C amplifier element (10) and its input point and power supply point (15)
) is connected with a bias setting resistor R_1, an inverter is used for the slicer (3), an OR gate or a group of logic circuits with an equivalent function is used for the logic circuit (4), and the signal input point is connected to the differential amplifier. Differential capacitor C_1 is connected in series with
(12) is provided and connected to the input point of the DC amplifier element, and another bias setting resistor R_ is connected between this point and the ground (16).
2 (13), and also connect this input point to the DC amplifier element (
6) A pulse processing circuit according to claim 1, which includes a negative feedback resistor R_f (14) at the output point of the pulse processing circuit. 3. A different operating point is set by connecting the input of the DC amplifier element (6) through the power supply point (15) and R_3 (17) in parallel to the input of the pulse processing circuit according to claim 2. The differential amplifier 7 and the circuit block having the slicer (3) at the subsequent stage are connected, and their respective outputs are ANDed.
The pulse processing circuit according to claim 1, which is inserted into a circuit or a logic circuit block having a function equivalent to the circuit, and whose output is the final output.