JPS6228602A - Method for detecting deviating quantity of interlayer position in multilayer printed circuit board - Google Patents

Abstract

PURPOSE:To improve the detecting accuracy ad efficiency of deviating quantities of inter-layer positions of a multilayer printed circuit board after the laminating process, by measuring the electrostatic capacities of conductive patterns which are previously provided by etching at two points. CONSTITUTION:Conductive patterns P1-P4 which become electrodes for measuring electrostatic capacity are formed by etching on insulative base materials 1 before the laminating process. Of the conductive patterns, those P3 and P4 are formed in such a way that they can respectively face the others P1 and P2 and have larger sizes than the others P1 and P2 have so that they can respectively cover the positions corresponding to the patterns P1 and P2. After the base materials 1 are laminated, electrostatic capacities between the patterns P1 and P3 and between the patterns P2 and P4 are measured. After the measurement, deviating quantities of inter-layer positions at the laminating time are calculated from the measured and designed electrostatic capacity values.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for detecting the amount of interlayer misregistration of a multilayer printed wiring board, and particularly to a method for detecting the amount of interlayer misregistration after a lamination process.

[Conventional technology]

In the lamination process, multilayer printed wiring boards are manufactured by attaching prepreg, an adhesive material made of an insulating material, to one or more of the outermost layer substrate, which is an insulating base material with conductive foil, and the inner layer substrate, which has a desired conductive pattern formed and arranged on the insulating base material. The sheets are placed in the middle and stacked together using a lamination press to heat and pressurize them to form an integrated laminated sheet. The accuracy of the deviation of the position between the eyebrows of the conductor pattern in each layer of this laminate is basically determined by the printing accuracy in the process of forming the conductive pattern on the insulating base material of each layer and the accuracy of the stacking position in the lamination process of stacking the inner layer substrates. be done. In addition, the amount of interlayer misalignment directly affects the basic properties of the multilayer printed wiring board, such as the insulation properties, resistance characteristics, and impedance properties of the laminate. Therefore, understanding the amount of interlayer misregistration after the lamination process during the manufacturing of multilayer printed wiring boards provides feedback information for managing the accuracy of interlayer misregistration during lamination, as well as whether or not the amount of interlayer misregistration after lamination conforms to the standard. Necessary for determination - Conventionally, methods for detecting this type of interlayer misalignment amount are as follows:
By arranging conductive patterns facing each other with a predetermined area in each layer and measuring the capacitance between the conductive patterns)
FIG. 7 is a cross-sectional view of a conventional multilayer printed wiring board used in a method for simply determining the amount of one-open position deviation, and FIG. 7 is a plan view of the second layer on which the conductive pattern P in FIG. 6 is disposed. 8 is an enlarged plan view of the conductive pattern P in FIG. 6, and FIG. 9 is a plan view of the conductive pattern P in FIG.
FIG. 7 is an enlarged cross-sectional view of an example in which an interlayer displacement amount σ occurs in a layer.

As shown in the multilayer printed wiring board in FIG. 6, the conventional method for determining the above-mentioned glabella positional deviation amount is to arrange conductive patterns P, P of electrodes for capacitance measurement in each layer at the same position and facing each other, and to This method detects the interlayer misalignment amount σ by measuring the capacitance between the conductive patterns P and P.
It is calculated using the formula. That is, σ: Amount of deviation in interlayer position ε: Dielectric constant of the insulating base material α: Width dimension design value of the conductive pattern P ΔS: Error value (of the width dimension of the conductive pattern P) CK: Static between the conductive patterns P-P Capacitance reference value C1: An actual measured capacitance value between the conductive patterns P and P is calculated.

[Problem that the invention seeks to solve]

However, the error value 8 with respect to the width dimension design value of the conductive pattern P in equation (1) has the characteristic that it varies from place to place due to variations in the manufacturing conditions of the multilayer printed wiring board. In other words, the design value 0 of the width dimension of the conductive pattern P in FIG. 7 is due to the printing and etching conditions for forming the conductive pattern during manufacturing, and as shown in FIG. 8, the microscopic finish is not constant and the width dimension of one conductive pattern P is An error value of 3 occurs with respect to the design value α. To actually measure this error value S, dimensions in a minute range are measured by an optical measurement method using a microscope, a projector, etc., but it is extremely difficult to measure accurately. Therefore, the error value 3 for the designed width dimension α of the conductive pattern P in equation (1) above includes an error, resulting in a disadvantage that the accuracy of the interlayer positional deviation amount σ becomes low. Furthermore, the capacitance reference value CK between one conductive pattern P-P needs to be calculated every time the error value changes, which has the drawback of requiring a large number of man-hours.

An object of the present invention is to provide a method for detecting the amount of interlayer misalignment of a multilayer printed wiring board, which solves the conventional drawbacks.

[Means for solving problems]

In the present invention, a first conductive pattern having a predetermined area is disposed on the m-th layer (m is an integer of 1<m<n-1) of a multilayer printed wiring board consisting of n layers (n is an integer), and m"l) the layer includes a position corresponding to the m-th layer, and a conductive pattern having a larger area than the first conductive pattern of the m-th layer is arranged oppositely), and at the same time adjacent to the first conductive pattern of the m-th layer. A second conductive pattern having the same dimensions as the first conductive pattern and electrically insulated from the first conductive pattern is placed at the (mth) position.
+1) At a position corresponding to the m-th layer, one side has the same width and the other side has a longer width than the two sides of the second conductive pattern of the m-th layer. a step of arranging conductive patterns of the same dimensions to face each other; and between the conductive patterns of the (m+1)th layer facing the first conductive pattern of the mth layer, and between the conductive patterns of the mth layer facing the second conductive pattern. m+
1) Measure the capacitance value between the conductive patterns of the layer and
A method for detecting an amount of interlayer misregistration of a multilayer printed wiring board, characterized by performing a step of detecting an unknown amount of interlayer misregistration between the layer and the (m+1)th layer.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a cross-sectional view of a multilayer printed wiring board according to an embodiment of the present invention, FIG. 2 is a plan view of the 2' layer in FIG. 1, and FIG. 3 is a plan view of the 3rd layer in FIG. FIG. 4 is an enlarged plan view of the conductive patterns PL and P2 in FIG. 2. FIG. 5 is an enlarged sectional view of the second and third layers in FIG.

The conductive patterns P arranged on the front and back surfaces of each insulating base material 1 are arranged in the first to fourth layers, respectively, and the insulating base material 1 and the prepreg 2 of an insulating adhesive are inserted between the layers of each conductive pattern P. The floating thickness d of the conductive pattern is obtained. The fifth and higher layers, which are not shown, are similarly configured. First of all 1
The multilayer printed wiring board shown in Fig. 1 is manufactured by laminating the printed wiring boards of each layer via the prepreg 2 by a known manufacturing method. Conductive patterns P1 to P4, which will become electrodes, are formed by etching. At the same time, circuit patterns 3, 4 and seats 5 are formed and arranged as shown in FIG. 2 for electrical connection. Also,
The circuit pattern 4 is a conductive pattern for electrical connection with the conductive patterns P1 to P4 to measure the capacitance in the outermost layer 1 (surface layer 1 back layer).This conductive pattern PL, P2 is formed and arranged in the second layer, and one conductive pattern P3. P4 is formed and arranged in the third layer. As shown in FIG. 2, the conductive pattern P1 is designed in advance to have a square shape with a width value α, and the design value of the area can be calculated as cL2. The conductive pattern circle is formed and arranged in a square shape larger than the conductive pattern P1 at a position facing the conductive pattern P1. That is, even if a predictable amount of interlayer misalignment occurs as shown in FIG. 3, the width dimension value of the conductive pattern circle is large enough to face and include the width dimension α of the conductive pattern P1 in FIG. Form and arrange. As shown in FIG. 2, the conductive pattern has a square shape with the same width value α as the conductive pattern P1, and has an electrical conductor at a position adjacent to the conductive pattern P1 at a distance of at least a predictable interlayer positional deviation. It is formed and placed in an insulated state. The conductive pattern P4 is formed on the conductive pattern at a position opposite to the conductive pattern in a shape in which one side has the same width value and the other side has a larger width value with respect to the dimension of the 02 side. . i.e. - conductive node P4
As shown in Fig. 3, the width dimension values α and C of The width dimension value α of the conductive pattern l in FIG. Form and arrange. Furthermore, as shown in FIG. 4, the width dimension value α of the conductive patterns PI and P2 in FIG. The width dimension value α+ including the dimensional variation becomes S (
The error value can be either positive or negative depending on the variation). Furthermore, since this error value m has a characteristic that it is constant near the same location of each printed wiring board to be laminated, almost the same error value occurs for the width dimension value α5bsc of the conductor patterns P1 to P4.

Next, in a lamination step, a prepreg 2 which is an insulating adhesive material is laminated between each of the insulating base materials 1, 1, and is heated and pressed in a lamination press to integrally laminate them. At this time, each insulating base material 1, 1
The interlayer positioning of the upper conductive pattern P is performed by a laminating means that performs positioning using a reference hole (not shown) provided in each insulating base material 1 and a reference pin of a mold on the side of the first lamination press. As shown in the figure, between the conductive pattern P1 and the circle and the nib 24, the amount of glabellar position deviation σ occurs as a manufacturing variation. Further, this interlayer positional deviation amount σ is a complex phenomenon caused by expansion and contraction of the base material caused by the physical characteristics of the insulating base material 1.

Next, after the lamination process, conductive patterns P1 to P4 were electrically connected as terminals for capacitance measurement on the outermost layers (surface layer, back layer), similarly to the known manufacturing method of multilayer printed wiring boards. Form through-holes, conduction holes, etc.

Next, the capacitance of the conductive pattern P1 and the private capacitance is measured) to obtain a capacitance value C0.

Next, the capacitance between the conductive patterns 1 and 24 is measured) to obtain a capacitance value C1.

As described above, the interlayer positional deviation amount σ can be calculated from the obtained capacitance value using the following equation (2).

Co: Actual capacitance C1 between conductive patterns PI-P3
: Measured capacitance value between conductive patterns P2 and P4 ε: Dielectric constant d of insulating base material: Interlayer thickness α: Width dimension design value of conductive patterns PL and P2 ΔS: (Width dimension of conductive patterns P1 to P4 ) Error value σ: Amount of misalignment between layers (second layer - third layer) From the above equation (2), the amount of interlayer misalignment σ between the second and third layers is the capacitance value C
It is obtained as a function of 0 and C□, and also the above (1)
Compared to the formula, the error value 8 of the width dimension of the conductive pattern P is not included. Note that although this embodiment has explained the positional deviation between the second layer and the third layer, it is also possible to detect the positional deviation between other layers in the same way.

Also, conductive patterns P1 to P4 for detecting the amount of interlayer positional deviation.
It is also possible to detect the amount of glabella misalignment of the entire multilayer printed wiring board by forming it at a corner or an appropriate location of the multilayer printed wiring board, or by forming and arranging it in multiple directions at the same location. be.

〔Effect of the invention〕

As explained above, the present invention measures the area of the conductive pattern of the electrode for capacitance measurement by measuring the capacitance at two locations of the conductive pattern that has been etched and arranged in advance. It has the effect of being able to detect the amount of interlayer positional deviation with high efficiency (high accuracy that eliminates fluctuation errors).

[Brief explanation of drawings]

FIG. 1 is a sectional view of a multilayer printed wiring board according to an embodiment of the present invention;
Fig. 2 is a plan view of the second layer in Fig. 1, Fig. 3 is a plan view of the third layer in Fig. 1, and Fig. 4 is a plan view of the conductive pattern P in Fig. 2.
1 and 5 are enlarged plan views of the 2nd and 3rd layers in Figure 1.
1. An enlarged sectional view of layers 1. FIG. 6 is a sectional view of a conventional multilayer printed wiring board. 1. FIG. 7 is a plan view of the second layer in FIG. 6.
FIG. 9 is an enlarged plan view of the conductive pattern P in the figure, and FIG. 9 is an enlarged sectional view of the second layer and third layer in FIG. 1... Insulating base material, 2... Prepreg (insulating base material),
3゜4...Circuit pattern, 5...Locus, P, Pi~P
4... Conductive pattern (of the electrode for capacitance measurement), αr
b r C...width dimension design value of conductive pattern, d.
...Interlayer thickness, △S... (width dimension of conductive pattern)
Error value/σ... interlayer positional deviation amount, x, y... direction axis

Claims (1)

[Claims] (1) The mth layer of a multilayer printed wiring board consisting of n layers (n is an integer)
A first conductive pattern having a predetermined area is arranged in a layer (m is an integer of 1<m<n-1), the (m+1)th layer includes a position corresponding to the mth layer, and the mth layer A conductive pattern having an area larger than that of the first conductive pattern of the m-th layer is arranged facing each other, and at the same time, a first conductive pattern having the same dimensions as the first conductive pattern is placed adjacent to the first conductive pattern of the m-th layer. A second conductive pattern insulated is arranged, and the (m+1
) layer, the width dimension of one side is the same as the dimension of two sides of the second conductive pattern of the m-th layer at a position corresponding to the m-th layer,
and a step of arranging conductive patterns facing each other with a long width dimension on the other side, and between the conductive patterns of the (m+1) layer facing the first conductive pattern of the m-th layer, and the conductive patterns of the m-th layer facing the first conductive pattern. The capacitance value between the conductive pattern of the (m+1)th layer facing the conductive pattern of the second conductive pattern and the (m+1)th layer is measured.
m+1) A method for detecting an amount of interlayer misregistration of a multilayer printed wiring board, the method comprising: detecting an unknown amount of interlayer misregistration between layers.