JPS62285460A - Protective circuit for input - Google Patents
Protective circuit for inputInfo
- Publication number
- JPS62285460A JPS62285460A JP12848486A JP12848486A JPS62285460A JP S62285460 A JPS62285460 A JP S62285460A JP 12848486 A JP12848486 A JP 12848486A JP 12848486 A JP12848486 A JP 12848486A JP S62285460 A JPS62285460 A JP S62285460A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layers
- current path
- layer
- easy
- diffusion layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001681 protective effect Effects 0.000 title abstract 2
- 238000009792 diffusion process Methods 0.000 claims abstract description 28
- 230000015556 catabolic process Effects 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 4
- 241001391944 Commicarpus scandens Species 0.000 abstract 2
- 238000007493 shaping process Methods 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
3、発明の詳細な説明
[発明の目的コ
(産業上の利用分野)
本発明は半導体集積回路における入力保護回路に関する
。Detailed Description of the Invention 3. Detailed Description of the Invention [Objective of the Invention (Industrial Application Field) The present invention relates to an input protection circuit in a semiconductor integrated circuit.
(従来の技術)
半導体集積回路の静電耐圧試験時に、電源ビン(vcc
とv88)の一方の電位を固定し、他方に電位を与えた
拡散層はブレークダウンを起こし、固定電位の拡散層と
の間に電流パスが生じる。この時内部回路の一部の拡散
層だけに電流ノ々スが生じると、大電流が集中して拡散
層が破壊されてしまう。(Prior art) During electrostatic withstand voltage testing of semiconductor integrated circuits, power supply bins (vcc
and v88), the potential of one of which is fixed, and the potential applied to the other, the diffusion layer causes breakdown, and a current path is generated between the diffusion layer and the diffusion layer with the fixed potential. At this time, if a current flow occurs in only a part of the diffusion layer of the internal circuit, a large current will concentrate and the diffusion layer will be destroyed.
そこで内部回路に大電流を集中させないために、vcc
′rL位の拡散層とv8s電位の拡散層とを近い位置に
並べた第5図の如き入力保護回路が提案されている。図
中1はN+型のvcct位の拡散層、2はN+型のv、
lc位の拡散層、3はこれら拡散層ノ。Therefore, in order to prevent large current from concentrating on the internal circuit,
An input protection circuit as shown in FIG. 5 has been proposed in which a diffusion layer at a potential of 'rL and a diffusion layer at a potential of v8s are arranged close to each other. In the figure, 1 is an N+ type diffusion layer of about vcct, 2 is an N+ type v,
1c is a diffusion layer, and 3 is a diffusion layer of these layers.
2t−設けたP型基板である。この第5図の入力保護回
路は、電流を集中させない大きな電流パスをつくると共
に、内部回路よりも早くブレークダウンを起こしている
ことが必要である。上記ブレークダウン現象は、拡散層
の直線部分よりも、曲が9角部分で起きやすい。これは
、拡散層の曲がり角部分では、直線部分よりも電界が集
中していることによるものである。2t- is a P-type substrate provided. The input protection circuit shown in FIG. 5 must create a large current path that prevents current from concentrating, and must also break down earlier than the internal circuit. The above-mentioned breakdown phenomenon occurs more easily in the curved 9-cornered portion than in the straight line portion of the diffusion layer. This is because the electric field is more concentrated in the curved portions of the diffusion layer than in the straight portions.
(発明が解決しようとする問題点)
図の如く拡散層1.2の対向部分が平行な直線であった
ため、1!界の密な部分が少なく、ブレークダウンが起
きにくいものであった。(Problem to be Solved by the Invention) As shown in the figure, since the opposing portions of the diffusion layers 1 and 2 are parallel straight lines, 1! There were few dense areas in the field, making it difficult for breakdowns to occur.
本発明は上記実情に鑑みてなされたもので、ブレークダ
ウンを起こしやすく、電流/4’スの大きい入力保護回
路を提供しようとするものである。The present invention has been made in view of the above circumstances, and is intended to provide an input protection circuit that is prone to breakdown and has a large current/4' current.
[発明の構成コ
(問題点を解決するための手段と作用)本発明は、電源
電位に接続される同導電型の拡散層どうしを反対導電型
層に互に対向して設け、前記各拡散1#はこれらが対向
する辺に屈曲部が設けられたことを特徴とする。即ち本
発明は、ブレークダウンを起こしやすい拡散層の曲がり
部分を多く設けたものである。[Structure of the Invention (Means and Effects for Solving the Problems)] The present invention provides diffusion layers of the same conductivity type connected to a power supply potential and facing each other in layers of opposite conductivity type. 1# is characterized in that a bent portion is provided on the opposing sides. That is, in the present invention, the diffusion layer has many curved portions that are likely to cause breakdown.
(実施例)
以下図面を参照して本発明の一実施例を説明する。第1
図は同実施例の平面図であるが、これは第5図のものと
対応させた場合の例であるから、対応する個所には同一
符号を用いる。第1図において1は1型のV。C電位の
拡散層、2はN+型のv88寛位の拡散層、3はこれら
拡散層1.2を近距離に対向配置したP型基板である。(Example) An example of the present invention will be described below with reference to the drawings. 1st
This figure is a plan view of the same embodiment, but since this is an example corresponding to that of FIG. 5, the same reference numerals are used for corresponding parts. In Figure 1, 1 is type 1 V. 2 is a diffusion layer of C potential, 2 is an N+ type diffusion layer of V88 position, and 3 is a P type substrate on which these diffusion layers 1.2 are disposed facing each other at a short distance.
この入力保護回路の特徴は、拡散層1.2が対向する辺
に屈曲部1*+2thが設けられ、ブレークダウンを起
こしやすいようにしたことである。また拡散層1.2間
の距離はすべて均一にして、同じように電流が流れやす
い条件にしておき、より大きい電流・臂スをつくるよう
にしている。A feature of this input protection circuit is that a bent portion 1*+2th is provided on the opposite side of the diffusion layer 1.2 to facilitate breakdown. Further, the distances between the diffusion layers 1 and 2 are all made uniform to create conditions where current can easily flow in the same manner, thereby creating a larger current flow.
なお本発明は実施列のみに限られず棹々の応用が可能で
ある。例えば拡散層1,2の屈曲部1a。It should be noted that the present invention is not limited to only practical arrays, and can be applied to many other applications. For example, the bent portions 1a of the diffusion layers 1 and 2.
2aは第2図ないし第4図のような構成であってもよい
。2a may have a configuration as shown in FIGS. 2 to 4.
[発明の効果]
以上説明した如く本発明によれば、ブレークダウンを起
こしやすく、かつ電流・クスも大きいため、内部回路の
拡散層破壊が起きにくくなるものである。[Effects of the Invention] As explained above, according to the present invention, breakdown is likely to occur and the current/gas is large, so that breakdown of the diffusion layer of the internal circuit is less likely to occur.
第1図は本発明の一実施例の平面図、第2図ないし第4
図は本発明の他の実施例の平面図、第5図は従来の入力
保護回路の平面図である。
1.2・・・N+層、3・・・P型基板、’ a r
2 a・・・屈曲部。
出願人代理人 弁理士 鈴 江 武 彦@2図
第3図FIG. 1 is a plan view of one embodiment of the present invention, and FIGS.
This figure is a plan view of another embodiment of the present invention, and FIG. 5 is a plan view of a conventional input protection circuit. 1.2...N+ layer, 3...P type substrate,' a r
2 a...Bending part. Applicant's agent Patent attorney Takehiko Suzue @2 diagram
Figure 3
Claims (2)
反対導電型層に互に対向して設け、前記各拡散層はこれ
らが対向する辺に屈曲部が設けられたことを特徴とする
入力保護回路。(1) Diffusion layers of the same conductivity type connected to a power supply potential are provided opposite to each other in layers of opposite conductivity type, and each of the diffusion layers is provided with a bent portion on the side where they face each other. input protection circuit.
均一であることを特徴とする特許請求の範囲第1項に記
載の入力保護回路。(2) The input protection circuit according to claim 1, wherein the distance between opposing sides of the diffusion layers is uniform.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12848486A JPS62285460A (en) | 1986-06-03 | 1986-06-03 | Protective circuit for input |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12848486A JPS62285460A (en) | 1986-06-03 | 1986-06-03 | Protective circuit for input |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62285460A true JPS62285460A (en) | 1987-12-11 |
Family
ID=14985885
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12848486A Pending JPS62285460A (en) | 1986-06-03 | 1986-06-03 | Protective circuit for input |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62285460A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2671911A1 (en) * | 1991-01-23 | 1992-07-24 | Samsung Electronics Co Ltd | Electrostatic discharge protection device for semiconductor devices |
-
1986
- 1986-06-03 JP JP12848486A patent/JPS62285460A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2671911A1 (en) * | 1991-01-23 | 1992-07-24 | Samsung Electronics Co Ltd | Electrostatic discharge protection device for semiconductor devices |
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