JPS62285203A - Read circuit - Google Patents

Abstract

PURPOSE:To prevent the read error by using a synchronizing signal permitting and inhibiting the read of an external data block so as to control the time constant of an integration circuit switchingly thereby quickly bringing the amplitude of a data signal to a prescribed value and suppressing the generation of noise with an abnormal amplitude. CONSTITUTION:Read signals RD1, RD2 being differential signals from a read head 1 are inputted to an amplifier 2 whose gain depends on the gain control voltage CV, data signals SD1, SD2 being differential signals of the outputs of the amplifier 2 are inputted to a rectifier circuit 3, and its output is inputted to an integration circuit 5 via a buffer circuit 4. The integration circuit 5 outputs the gain control voltage CV corresponding to the integration value of the input signal voltage. That is, a switch circuit 51 of the integration circuit 5 connects a resistor R2 in parallel with a resistor R1 of a series circuit comprising the resistor R1 and a capacitor C1 of a time constant circuit 52 to decrease the time constant when the synchronizing signal SYNC permitting and inhibiting the read of a data block from an external host device is at a high level and disconnects the resistor R2 to increase the time constant when the signal SYNC is at a low level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a read circuit, and particularly to a read circuit having an AGC circuit in a magnetic storage device.

[Conventional technology]

Conventionally, in this type of readout circuit, the amplitude response speed of the AGC circuit has been fixed.

In general, in magnetic storage devices, the data recorded on the medium is
Data is recorded divided into multiple data blocks, and when reading within the same data block, there is little change in the head output amplitude.

With respect to noise and extra pulses, it is desirable that the amplitude response speed of the AGC circuit is slow.

On the other hand, when reading the head of a data block,
Since the change in the output amplitude is large, in order to keep the output amplitude of the AGC circuit constant, it is desirable that the amplitude response speed be faster than the response speed within the data block.

[Problems to be Solved by the Invention] In the conventional readout circuit described above, since the amplitude response speed of the AGC circuit is constant, when the amplitude response speed is slow, as shown in FIG. 2(a), , when the period A during which a large change appears in the amplitude of the AGC circuit output for the head of the data block becomes long, and when the amplitude response speed is fast, noise is input to the AGC circuit input as shown in Figure 2(b). Since an excessively large reaction pulse B is generated at the output of the AGC circuit, the amplitude of the signal waveform input to the decoding circuit does not reach a predetermined value, resulting in a reading error.

An object of the present invention is to provide a read circuit that can prevent read errors from occurring during decoding.

[Means for solving problems]

The readout circuit of the present invention includes a switch circuit whose opening and closing are controlled by an external synchronization signal that instructs permission and prohibition of data protection, and a time constant circuit whose time constant is changed by opening and closing the switch circuit. an integrating circuit that integrates a signal voltage of an input data signal according to the time constant and outputs a gain control voltage; and a gain determined by the gain control voltage that amplifies a read signal for the data block and outputs the data signal. and an amplifier.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

In FIG. 1, read signals RD, 7i and RD2, which are differential signals from a read head 1, are input to an amplifier 2 whose gain is determined by a gain control voltage CV, and the output is a data signal, which is a differential signal. SD and SD 2 are input to a rectifier circuit 3, and the output thereof is input to an integrating circuit 5 via a buffer circuit 4 composed of an amplifier and a resistor.

The integrating circuit 5 includes a time constant circuit 52 of a switch circuit 51 and a differential amplifier 53, and outputs a gain control voltage C■ corresponding to the integral value of the input signal voltage. That is, the switch circuit 51 of the integrating circuit 5 switches the resistor R1 and capacitor C of the time constant circuit 52 when the synchronizing signal 5YNC, which allows and prohibits reading of the data program from an external host device, is at a high level.
A resistor R2 is connected in parallel to the resistor R1 of the series circuit No. 1 to reduce the time constant, and when the level is low, the resistor R2 is disconnected to increase the time constant.

Therefore, when the synchronizing signal 5YNC is at a high level, the gain control voltage CV rises quickly, and when the synchronizing signal 5YNC is at a low level, it rises slowly.

Amplifier 2. Rectifier circuit 3. Buffer circuit 4 and integration circuit 5
Since the AGC circuit is configured as follows, when the rise of the gain control voltage C2 is fast, the amplitude response speed is fast, and when the rise is slow, the amplitude response speed is slow.

On the other hand, the data signals SD and sD2 are input to the decoding circuit 6 and decoded to obtain output data.

FIG. 3 is a waveform diagram for explaining the operation of the embodiment shown in FIG. 1. In FIG. 3, read signals RD and R
D2, data signal SD, and SD2 each indicate an envelope waveform.

As shown in Fig. 3, AGC uses synchronization signal 5YNC.
By controlling the amplitude response speed of the circuit as described above, the data signals SD and SD2 output from the amplifier 2 quickly reach the normal amplitude at the beginning of the data block, and then the synchronizing signal S'Y ' Since NC is at a low level, an oversensitive response can be avoided and data signals SD and SD2 having waveforms of appropriate amplitude can always be sent to the decoding circuit 6.

〔Effect of the invention〕

As explained above, the readout circuit of the present invention switches and controls the time constant of the integrating circuit using a synchronization signal that allows and prohibits reading of data blocks from the outside.
The amplitude response speed of the AGC circuit is made faster in the first part of the data block, and the AGC circuit is
Since the amplitude response speed of the C circuit can be slowed down, the amplitude of the data signal can be quickly brought to a predetermined value, and the occurrence of abnormal amplitude noise can be suppressed, which has the effect of preventing read errors and improving the reliability of the circuit. be.

[Brief explanation of drawings]

Fig. 1 is a process diagram of one embodiment of the present invention, Fig. 2 (a)
) and (b) are waveform diagrams for explaining the operation of the conventional readout circuit, and FIG. 3 is a waveform diagram for explaining the operation of the embodiment shown in FIG. DESCRIPTION OF SYMBOLS 1... Readout bed, 2... Amplifier, 3... Rectifier circuit, 4... Buffer circuit, 5... Integrating circuit, 6...
...Decoding circuit, 51...Switch circuit, 52...Time constant circuit, 53...Differential amplifier, C■...Gain control voltage, RD. RD2...Read data, SDl, SD2・
...Data signal. No./I! 1 (a)
Cb) Kaya 2I! I

Claims (1)

[Claims] The signal voltage of the input data signal is equipped with a switch circuit whose opening and closing are controlled by an external synchronization signal that instructs permission and prohibition of data block reading, and a time constant circuit whose time constant is changed by opening and closing of the switch circuit. and an amplifier whose gain is determined by the gain control voltage and which amplifies a read signal for the data block and outputs the data signal. readout circuit.