JPS62283475A - Block access method - Google Patents

Abstract

PURPOSE:To recognize a reliable address by a simple signal processing by deciding by the number within a constant value obtained by comparing a prescribed address and a correction code with the (n) code writing of an unit consisting of the address and the correction code of a reproducing block. CONSTITUTION:An object address supplied through an input terminal 6 from a host computer or the like is encoded 7, the error correction code ECC is added and the set of the object address and the error correction code is fed to a comparison circuit 5. This set is sequentially compared with the set of the (n) code written address and the error correction code in a reproducing signal obtained from an address reading circuit 3 in the circuit 5. As a result of the comparison, if there are more than K (1<K<=n) time of the coincidences within a prescribed allowable value (a), it is decided to be the object address, and a coincidence output is fed to a terminal 9. According to this simple signal processing, the address can be recognized with the reliability maintained.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention A. Industrial Field of Application The present invention relates to a recording medium such as an optical disk or an optical card, in which the recording area is divided into blocks of 1M sectors, etc. The present invention relates to a method for accessing a block of predetermined addresses in a computer.

B0 Summary of the Invention The present invention provides a method for accessing a block at a predetermined address on a recording medium that is divided into a plurality of blocks and recorded with an address and an error detection or correction code written in nu for each block. 88 error detection or correction codes are added to the pre-encoded and reproduced professional data.

The n overwritten address and the above error detection or correction code are sequentially compared, and as a result of this comparison, a predetermined value a
By accessing the program currently being played as a block at a predetermined address, unnecessary signal processing, such as error correction decoding processing, can be omitted. In addition to simplifying the hardware configuration required for decoding, the reliability can be set arbitrarily high or low depending on the system, and in particular, it is possible to obtain extremely high reliability.

C1 Prior Art - In disk-shaped optical recording media such as optical disks and magneto-optical disks, concentric or spiral trunks are formed, and one track is i.
It is divided into o sectors.

Further, in a card-shaped recording medium such as an optical card, for example, a strip-shaped recording area is divided into a plurality of recording trunks. Each predetermined position of each recording block such as each sector or each recording trunk, for example, each start position, is subjected to so-called formanoting processing prior to the start of use of a new disc, and so-called pre-printing processing performed by the disc or card supplier. By formatting processing etc., synchronization pattern, address, C
A so-called identification signal including an RC error detection code and the like is recorded. The address information of such an identification signal allows random access to recorded data.

The identification part of each block (sector, etc.) in which this identification signal is recorded is also called an ID part or an address part in a broad sense.For example, in an optical disc, a CRC error detection code is attached to an address consisting of a track address and a sector address. One unit (1 unit) of identification information to which is added is recorded in multiple writing (for example, 3ffil).

D0 Problems to be Solved by the Invention Incidentally, in such conventional identification signal recording formats, error detection codes such as CRC have been used as error codes. It has also been proposed to add an error correction code to cope with the situation. When accessing a predetermined sector on the disk due to signal recording and reproduction, an operation is always performed to control the movement of the Rad to the pickup while reproducing the identification signal and confirming the current address. When reproducing this address, decoding processing such as error detection or error correction is always executed. For this reason, signal processing during address reproduction becomes complicated, and especially when multiple writing is performed such as the triple fortune telling described above, error checking or error correction is performed for all parts, and then majority logic is applied. Address determination processing must be performed, and what algorithm or hardware is required for decoding processing? ! It becomes complicated and the time required for arithmetic processing becomes longer, and there is a spread that becomes an impediment to high-speed access.

In addition, there is a fundamental difference between recording and reproducing signals, and when reproducing (when data continues to flow), it is important to read out data that has already been written, and the address must be set with high reliability. There are many cases where you want to access even if you cannot read the address (on the other hand, when recording (writing data), data is stored in a recording area whose address cannot be read completely (with high reliability). It is better not to make the address obsolete, that is, it is better not to access it.Therefore, it is practical to make the conditions for making the playback address valid or the access conditions different when playing back (when repeating) and when recording (when writing). I will do it.

Furthermore, depending on system requirements, it may be necessary to change the conditions for determining whether a reproduced address is valid or the access conditions. In particular, when addresses and error detection or correction codes are multiplexed, this multiplexed writing may be necessary. It is conceivable that the above judgment conditions can be freely changed by combining the above.

The present invention has been made in view of the above circumstances, and is capable of confirming the target address without performing decoding processing such as error detection or error correction when accessing a block (sector, etc.) of a desired target address. This not only simplifies the hardware configuration required for decoding, but also enables the decoding to be performed in accordance with system requirements, such as during recording (data writing) and playback (when data continues to flow). The purpose is to provide a practical block access method that allows the conditions for determining address validity and access conditions to be freely varied.

Means for Solving the E6 Problem In order to solve the above-mentioned problem, the block access method according to the present invention provides a method for solving the problem described above, in which a recording medium is divided into blocks such as a plurality of sectors, and each block is placed at a predetermined position.
In a method of accessing a block at a predetermined address such as a desired target address by sequentially reproducing a recorded unit in which an error detection or correction code is added to the address of the block in n-multiple writing, the above-mentioned predetermined address is The encoded block with the error detection or correction code added thereto is sequentially compared with n units consisting of the n-overwritten address of the reproduced block and the error detection or correction code, and as a result of this comparison, Predetermined value a
The present invention is characterized in that when the number of units with a difference within k≦n is obtained, the block currently being reproduced is accessed as a block at a predetermined address.

By changing the values a and k of the F1 effect, it is possible to arbitrarily set the conditions for allowing coincidence during the comparison, and the smaller the value a and the larger the value k, the stricter the conditions and the higher the reliability.

G. Embodiment FIG. 1 is a diagram for explaining an embodiment of the block access method of the present invention. In FIG. 1, an optical pickup head 2 records and reproduces signals on an optical disk 1 as an example of a recording medium. The signal from the optical pinocanophendo 2 is sent to an address reading circuit 3 to read the address of the block (sector) currently being reproduced, and this read address signal is sent to a comparison circuit 5. There is.

By the way, as a specific example of a signal recording format in a sector that is one block on the optical disk 1, the one shown in the second table has been proposed. In FIG. 2, one track on the optical disk 1 is stretched out linearly, and the identification part (so-called ID part) of one sector is schematically shown enlarged, and one trunk is made up of multiple sectors. , l sector includes, for example, a preformatted identification section IDR and a data section DTR as an area in which sector data of -i is recorded. At the head position of the identification part IDR, a recording part of a synchronization signal (PLO sink) PLO3 for stabilizing the operation of a clock generation PLL circuit etc. when reading data is arranged at the head,
The unit tJT, which is one recording unit of sector identification address information, is arranged in triple writing (n=3) consecutively to the recording portion of the synchronization signal P8. That is,
3 with the same content, which is the recording unit of sector identification address information
The three units UTI, tJT2, and UT3 use the synchronization signal PL.
They are arranged sequentially following O3, and each recording unit or unit UT has a sync pattern address mark SPA at the beginning, an address AD consisting of a track address TA and a sector address SA, and then a CRC.
An error correction code ECC consisting of an error detection code or, for example, a BCH code is arranged. Here, as an example of the number of bits in each part, the address AD has a total of 24 bits, including 16 bits for the trunk address TA and 8 bits for the sector address SA, and the length of the error detection or correction code ECC is It is equal to AD and has 24 bits.

For example, when a host computer or the like records or reproduces a data signal on the optical disc 1 that has sectors (blocks) in such a recording format, the block (sector) at the target address for recording or reproduction is performed. access is required. In order to access the sector of this target address, conventionally, when reading the identification part (CID part) of each sector and reproducing the address signal, each address error of each unit UTI to UT3 is detected as an error or Those detected or corrected using the correction code ECC are compared with each other, and if these address values are different, the majority logic determines the address value that most often fails (in the case of triple writing, two of the three address values A matching address) is adopted as the effective address of the current location, and this effective address is compared with the above-mentioned target address, and one node is hyperactively controlled to be sent to the pinokufubu so that it approaches the block of the target address. . However, with this method, the current address cannot be determined until all of the multiplex-written addresses of each unit have been decoded, and decoding processing is required continuously, which places a heavy burden on the hardware.

Therefore, in this embodiment, as shown in FIG. 1, the object (target) address A
t is encoded (encoded) in advance in the ECC encoder 7 to add an error correction (or error detection) code ECCL, and the set of the target address ADL and the error correction code ECCt is sent to the comparison circuit 5, and the above-mentioned It sequentially compares the set of multiplexed addresses and error correction codes in the reproduced signal obtained from the address reading circuit 3, and determines whether or not they match within a predetermined tolerance value a (1<k≦n) or more times. For example, it is determined that the address is the target address, and the one-defeat output is sent to the output terminal 9.

Here, FIG. 3 is a diagram for explaining the above comparison operation, and similarly to the recording formant of FIG. 2, for example, a 24-bit address and a 24-bit error correction code are triple-written (n=3 ) shows an example of a reproduction signal obtained by reproducing a disc etc. (however, synchronization signals etc. are omitted). In FIG. 3, the sets of addresses and error correction codes constituting the triple-written units UT1, UT2, and UT3, respectively, change over time to eight Dl, E
CC1, AC3, ECC2, AC3, and ECC3 are reproduced in this order, and first, the ancestors of ADI and ECCl are compared with the set of the target address AD and error correction code ECCL. The comparison operation at this time is a simple comparison of each bit, and if the number of different bits is within a (for example, 4) out of a total of 48 bits (24 bits of address and 24 bits of error correction code), In other words, the number of bits a is considered to be a so-called permissible range or ta (a (threshold)) to determine whether or not there is a failure. The reproduced signals AD2 and ECC2 of the next unit UT2 are compared, and if necessary, the reproduced signals AD3 and ECC5 of the next unit UT3 are compared.
When the above-mentioned "-defeat" is detected for k (for example, 2) units 7, it is determined that the block (sector) currently being reproduced is the block with the above-mentioned target address AD. At this time, [1-kissed Unino) UT
Regenerate all of I-UT3 and use the above target address A D
It may be compared with the set of L and error correction code ECC, but
The reproduced units (UTI to UT3) are successively compared, and when the above "matching" units (2 units) are detected, the block currently being played is immediately transferred to the above target address A.
It may be determined that the block is Dt. In other words, when the comparison results of UNI) tJTI UT2 are all within the above a, then UNI) UT3
This means that the destination address is determined to be the above-mentioned target address without any comparison.

In this case, if a 24-bit BCH code is used as the error correction code ECC, the inter-code distance is 12 and the error correction capability is 5, so errors within, for example, a=4 bits can be almost completely corrected. The corrected result will match the above target address. Therefore, without performing decoding processing, which generally requires complex algorithms and imposes a large burden on hardware, the playback address can be confirmed with the same degree of reliability as when decoding is performed, and it is possible to confirm the playback address with the same degree of reliability as decoding. Therefore, extremely reliable address 611 verification and access to a desired target sector (block) can be performed.

Next, the movement control operation of the gutter 2 to the optical pick amplifier until reaching the target address can be performed in the same manner as in the past. For example, in the comparator circuit 5, the address value read from the address reading circuit 3 and the above The head movement control circuit 1 calculates the difference between the target address value and the head movement control circuit 1 according to this difference.
By driving the drive motor 12 for moving the blade through the head support plate 13 and controlling the movement of the blade 2 in the disk radial direction (in the direction of the arrow) to the optical pickup through the head support plate 13, etc., the playback address and the target address are determined. In this case, the address reading circuit 3 may have the same configuration as the conventional one, but the reference address determined by reading from the preceding sector of the optical disc 1 first. Based on this, the address of the sector currently being reproduced following the preceding sector is determined by calculation (for example, by adding 1), and this determined address is compared with the address obtained by actually reproducing. The circuit may be configured to output the reproduced address or the estimated address as a correct and determined address when the address fails. In addition, the pre-encoded address of the above estimated address is compared with a set of reproduced address and error detection or correction code, and if they match within a predetermined tolerance range, the predetermined address is output as the correct address. A reading circuit 3 may also be used.

By the way, by combining the above values of a and k, it is possible to reverse the above-mentioned -defeat tolerance condition or access tolerance condition and set it under a high degree of freedom.

For example, if a=Q, k=n (3 in the case of 3ffi writing), all n-overwritten units match the set of the above target address and error detection or correction code without a 1-bit difference. This is the most severe condition and has the highest reliability. With respect to this condition, as a is made larger and k is made smaller, the conditional force becomes less than 11, and the access becomes easier, but the reliability decreases. By making these various conditions variable depending on the requirements of the system, the operating mode, the importance of data, etc., block access can be made in accordance with the actual situation.

Here, playback of No. 13 on the disk (data continues)
An example of making the above match permission conditions or access permission conditions different depending on the time of recording (data writing) is as follows:
The case where n=3) will be explained. For example, when the above-mentioned dark value (slenjord) a□ when reproducing the signal (sequential occurrence) is 4, and the number of matches kil+ is 2, the threshold value allF when recording (writing) the signal is 1, and - the number of losses is □. 3, which narrows the allowable range during recording and makes the matching conditions stricter than during playback.

This is because, as mentioned above, when a signal is played back, the data has already been written, so it is difficult to read the address (and there is a request to read the data), whereas when the signal is recorded, it is difficult to read the data later. This is because it is better to avoid writing data to blocks (sectors) whose addresses are difficult to read in order to ensure security.

It should be noted that the present invention is not limited to the above-mentioned embodiments. For example, the present invention can be applied not only when accessing a target address from a host computer, etc.
The present invention may be applied during normal address reproduction. In this case, when sequentially reproducing addresses from blocks with consecutive addresses, such as consecutive sectors on an optical disk,
Determining the address of the block currently being played following the preceding block by calculation (for example, by adding °1゛ to the base address) based on a reference address read and determined in advance from the preceding block; This predetermined address is encoded and an error detection or correction code is added, and this predetermined address and code set is multiplexed with the address obtained by actual reproduction and the error detection or correction code. The above-mentioned address validity judgment condition at the time of this comparison is set by the combination of the number of bits of difference a and the number of matches, and this condition (recovered balls within a) is satisfied at the same time. The address at that time is output as a correct and valid playback address.

Furthermore, the present invention can be applied to card-shaped recording media such as optical cards in addition to disc-shaped recording media, and the recording format of the identification part (ID part) of a block such as a sector of a disc is also applicable to the illustrated example. is not limited.

H9 Effects of the Invention According to the block access method of the present invention, address confirmation can be performed with the same degree of reliability as in the case involving conventional decoding processing by means of node Iα signal processing, which simplifies processing and Not only can you easily simplify the hardware, but by combining the number of differences in the comparison with the number of times, you can adjust the operating modes such as recording and playback modes and data changes according to system requirements. Depending on the importance etc.
The reliability of block access can be freely set in detail, and block access can be realized in accordance with the actual situation.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a circuit configuration for explaining a block access method according to an embodiment of the present invention, and FIG. 2 shows an example of a signal recording format on an optical disk used in the embodiment. 3 is a diagram for explaining a comparison operation between a reproduction signal obtained by reproducing an optical disc having the recording format shown in FIG. 2 and a signal obtained by encoding a target address. 1... Optical disc 2... Optical pickup head 3... Address reading circuit 5... Comparison circuit 6... Target address input terminal 7... ECC encoder 9... Match signal output terminal

Claims (1)

[Claims] A recording medium in which a recording area is divided into a plurality of blocks, and each block is recorded with n overwriting units each having a corresponding address and an error detection or correction code for the address. In contrast, in a method of accessing a block at a predetermined address, the predetermined address is encoded and the error detection or correction code is added, and a unit consisting of the address and the error detection or correction code of the reproduced block is n. The overwritten blocks are sequentially compared, and when k or more units (1<k≦n) with differences within a certain value a are obtained as a result of this comparison, the block currently being played is moved to the above-mentioned predetermined address. A block access method characterized by determining that a block is a block.