JPS62283471A - Reproducing method for address signal - Google Patents

Abstract

PURPOSE:To realize the reproduction of an address signal without deteriorating the reliability and to simplify a hardware constitution by comparing an estimated address based on a determined reference address with a reproducing address. CONSTITUTION:The reproducing signal of an optical pickup head 2 is fed to a reader 3 to have a digital signal and the address part of this signal is fed to a comparison circuit 5. The estimated address is supplied to the circuit 5 according to the arithmetic processing of a present address arithmetic circuit 8 based on the determined reference address previously read from an optical disk 1, this estimated address is compared with the reproducing address and when they coincide, the address is defined to be effective. According to a simple signal processing only by the comparison in this manner, the reproduction of the address of high reliability can be performed in a short time.

Description

Detailed description of the invention 3. Detailed description of the invention The present invention relates to a method for reproducing address signals such as sector addresses recorded at the beginning of blocks, etc.

B1 Summary of the Invention The present invention provides a method for reproducing an address signal written in each block of a recording medium divided into a plurality of blocks, in which the address of the current block is calculated based on a previously read reference address. This estimated address is compared with the actually read address of the current block, and the address signal is made valid according to the comparison result, thereby eliminating unnecessary signal processing, such as error correction processing. Even if omitted, highly reliable address reproduction is possible, and the hardware configuration required for encoding and decoding is simplified.

C1 Prior Art In general, concentric or spiral tracks are formed on disk-shaped optical recording media such as optical disks and magneto-optical disks, and one track is divided into a plurality of sectors. .

Further, in a card-shaped recording medium such as an optical card, for example, a strip-shaped recording area is divided into a plurality of recording tracks. Each predetermined position of each recording block such as each sector or each recording trunk, for example, each start position, is used for so-called formatting processing prior to the start of use of a new disc, or for so-called pre-printing on the disc or card supplier's side. By formatting processing etc., synchronization pattern, address, C
A so-called identification signal including an RC error detection code and the like is recorded. The address information of such an identification signal allows random access to recorded data.

The identification part of each block (sector, etc.) in which this identification signal is recorded is also called the ID part or address part in a broad sense.For example, in optical discs, a CRC error detection code is added to the trunk address and sector address. Unit information (one unit) is recorded in multiple writing (for example, triple writing).

D0 Problems to be Solved by the Invention Incidentally, in such conventional identification signal recording formats, error detection codes such as CRC have been used as error codes. It has also been proposed to add an error correction code to cope with the situation. When accessing the disk due to signal recording and playback, etc., the above-mentioned identification signal is reproduced and the current address is recognized as 611, while an operation is always performed to control the hyperactivity of the 7D 1 to the bifkuab. During playback, decoding processing such as error detection or error correction is always performed. For this reason, signal processing during address reproduction becomes complicated, and especially when multiple writing such as the above-mentioned triple writing is performed, the address is processed using majority logic after error checking or error correction is performed for all parts. Determination processing must be performed, the decoding algorithm and hardware become complicated, and the time required for arithmetic processing becomes longer, which may impede high-speed access.

The present invention has been made in view of these circumstances, and enables address reproduction to be achieved with high reliability without performing decoding processing such as error detection or error correction, and simplifies the hardware configuration required for decoding. The purpose of the present invention is to provide a method for reproducing address signals that can be used as an address signal.

Means for Solving the E0 Problem In order to solve the above-mentioned problem, the address signal reproducing method according to the present invention has a recording medium divided into blocks such as a plurality of sectors, at a predetermined position of each block.
In a method of reproducing an address signal recorded in a redundant form with an error detection or correction code added, a certain positional relationship with respect to a block of a reference block address previously read from the recording medium and determined. When reproducing the address of the current position block in , compare the estimated address of the current position block calculated based on the reference block address and the fixed positional relationship with the address obtained by reading the current position block. death,
When these addresses match within certain conditions,
The present invention is characterized in that the address signal is output without performing at least the signal processing of error detection or correction.

F1 effect A highly reliable address can be reproduced in a short time by simple signal processing that simply compares the estimated address of the block currently being reproduced with the actually reproduced address.

G. Embodiment FIG. 1 is a diagram for explaining an embodiment of the address signal reproducing method of the present invention. In FIG. 1, at least a signal is reproduced by an optical pickup head 2 on an optical disc l as an example of a recording medium. The signal from the optical pink-up head 2 is sent to a signal reading circuit, a so-called reader 3, and converted into a digital signal, and at least the address part (playback address ADrs) of this read digital signal is sent to a comparison circuit 5. It will be done. The comparator circuit 5 first receives the disk 1.
The block currently being played is estimated by arithmetic processing based on the reference address AD, which is read from and confirmed (
The address (estimated address) AD of the sector) is supplied. In the comparator circuit 5, these playback addresses AD
The PI and the estimated address AD□ are compared, and if they match, the address is considered valid.

By the way, as a specific example of a signal recording format in a sector that is one block on the optical disk l, the one shown in FIG. 2 has been proposed. In FIG. 2, one track on the optical disk 1 is stretched linearly, and the identification part (so-called ID part) of the l sector is schematically shown enlarged, and the l track is made up of multiple sectors. , l sector consists of, for example, a preformatted identification part IDR and a data part DTP as an area in which general sector data is recorded. At the head position of the identification part IDR, a recording part of a synchronization signal (PLO sink) PLO3 for stabilizing the operation of the clock generation PLL circuit etc. when data is continued is arranged at the head,
Continuing from the recording portion of this synchronization signal PLO3, units LIT, which are one recording unit of sector identification address information, are arranged in a triple-eight array. That is, three units IJTIUT2 and IJT3, which are recording units of sector identification address information with the same content, are sequentially arranged following the synchronization signal PLO5, and each recording unit UT has a sock pattern address mark SPA at the beginning. are arranged,
An address AD consisting of a track address TA and a sector address SA is arranged, followed by an error correction code ECC consisting of a CRC error detection code or, for example, a BCH code. Here, as an example of the number of bits in each part, the address AD has a total of 24 bits, including 16 bits for the trunk address TA and 8 bits for the sector address SA, and the length of the error detection or correction code ECC is as follows.
It has 24 bits, which is equal to the total address data.

Conventionally, when reading the identification part (ID part) of each sector in such a recording format and reproducing the address signal, each address AD of each unit UTI to UT3 is detected or detected by error detection or correction code ECC, respectively. After the correction processing, valid ones of these processed address values are compared with each other, and if these valid address values are different, the address value that matches the most (in the case of triple writing, the address value that matches the most) is selected by majority logic. (two of the two address values match) are used. However, with this method, the current address cannot be determined until all addresses of each multiplexed unit are decoded and compared, and decoding processing is required continuously for each multiplexed unit. The burden on hardware is also large.

Therefore, in this embodiment, the optical pink-up head 2 is currently playing data based on the reference sector address AD, which has been previously read from the optical disc 1 and whose reliability has been ensured through decoding processing, etc. The address of the sector is estimated by calculation, and the estimated address ΔD of the current sector is
as is sent to the comparator circuit 5 and compared with the reproduction address ADr@ obtained by actual reproduction.

This will be explained in more detail with reference to FIGS. 1 and 3. Here, FIG. 3 shows, for example, a plurality of sectors S E C+ , S E
C2, S E Cs . . . and the addresses of these sectors SEC, 5EC2, 5EC3, . . . are bound as AD, , ADZ, AD, . , E CC2-E
CCz... In Fig. 3, the address and error correction code of each sector are shown written in a single layer to simplify the explanation, but it is also possible to write them in multiple layers, or instead of the error correction code A detection code may also be used.

First, regarding the reference address AD□, the reader 3 in FIG. 1 selects an arbitrary sector, for example 'i? By reading the address AD of sector SEC, shown in Figure J3 and decoding it using the error correction code ECC1 in the ECC decoder 6, a highly reliable reference address AD is obtained, and this is applied to the selector switch 7. The 0th sector SEC! is sent to the current address arithmetic circuit (or current address estimation circuit) 8 via the selection terminal S, and the sector SEC! When reproducing the address, the current address arithmetic circuit 8 calculates (estimates) the address of the sector 5EC2 currently being reproduced based on the reference address AD, , for example, by calculating AD, e+1.
, in the comparison circuit 5, this estimated current address A
Dos (= A Dre" t) is compared with the current address A D z" obtained by actual reproduction.

When these addresses match, the comparison circuit 5
sends out a coincidence output from the output terminal 11, and in response to this coincidence output, outputs the address output from the reader 3 through the terminal 12 as a valid address. The effective address output from the output terminal 12 is sent to the selected terminal a of the changeover switch 7 via the input terminal 16, for example, and is used as the reference address for reproducing the address of the next sector by the current address/ii calculating circuit 8. sent to. Note that the estimated address AD, . . . from the current address arithmetic circuit 8 may be taken out from the output terminal 13 and used as the effective address.

Here, to explain the arithmetic processing for estimating the current address in the current address calculation circuit 8, when reproducing the address signal from successive sectors one by one as described above, sector synchronization from the optical pinochue hub is performed. Every time a sector count signal based on a pulse, a disk rotation detection pulse, etc. is supplied to the input terminal 17, the addition data "l" from the input terminal 18 is sent to the reference address AD,
.

The estimated address AD□ may be calculated by adding the address AD□. In addition, when reproducing address signals for every two or more sectors, for example every n sectors, the addition data of the input terminal 18 should be
'', an addition operation may be performed every time n sectors are counted, and the estimated address may be sent to the comparator circuit 5.

Furthermore, in the case where multiple M addresses and error correction (or detection) codes are written in the identification section of one sector, the address of each multiple-written unit is simply compared with the estimated address in sequence, As soon as the above-mentioned match is detected, the address is output as a valid address without the need for decoding or majority voting as described above. That is, even in the case of multiple-written addresses, if the reproduced address of the first unit matches the estimated address, the current address is determined without reproducing the addresses of the remaining units.

According to the address signal reproducing method as described above, there is no need for decoding processing and majority voting processing for the reproduced address data, thereby simplifying the hardware configuration and shortening the processing time.

By the way, in the above embodiment, the address AD□ in the reproduced signal is taken out as is and the estimated address AD, .
However, the above error correction code EC in the reproduced signal
The reproduced address may be decoded p (error correction decoding) using C□, and this error-corrected address may be simply compared with the estimated address AD, . Here, 24-bit BC is used as the error correction code ECC.
When using the H code, the inter-code distance is 12 and the error correction ability is 5, which is strong, so the reproduced address ADP
Even if there is an error of several bits (within 5 bits) in I and the error correction code ECC□, it can be corrected, and address reproduction that is resistant to errors is possible.

Note that the present invention is not limited to the above-mentioned embodiments. For example, the present invention is not limited to the above-mentioned embodiments.
≦n) A comparison process may be performed to output the valid address when the above reproduction addresses match the estimated address. In this case as well, there is no need to wait until all of the n overwritten addresses are reproduced, and it is sufficient to immediately determine that the address is a valid address and output the address when the k reproduced addresses match the estimated address.

H6 Effects of the Invention According to the address signal reproducing method of the present invention, the address of the block (sector, etc.) currently being reproduced is estimated based on the reference address that has been read and determined in advance, and this estimated address is actually used. By simply comparing the address with the reproduced address, address signal reproduction can be realized by simple signal processing without deteriorating the reliability, and the hardware configuration can also be simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a circuit configuration for explaining an embodiment of the present invention, FIG. 2 is a diagram showing a signal recording format on an optical disk reproduced by the embodiment, and FIG. Schematic % formula showing each address and error correction code of consecutive sectors on an optical disk % 2...Optical pickup head 3...League 5...Comparison circuit 6...ECC decoder

Claims (1)

[Claims] A method for reproducing an address signal recorded in a form having redundancy for error detection or correction at a predetermined position in each block of a recording medium in which a recording area is divided into a plurality of blocks. , when reproducing the address of the current position block that is in a certain positional relationship with respect to the block with the reference block address that was previously read and determined from the recording medium, based on the reference block address and the certain positional relationship. Compare the estimated address of the calculated current position block with the address obtained by reading the current position block, and when these addresses match within a certain condition,
An address signal reproducing method characterized by determining that an address signal is valid.