JPS6228269U - - Google Patents
Info
- Publication number
- JPS6228269U JPS6228269U JP11410986U JP11410986U JPS6228269U JP S6228269 U JPS6228269 U JP S6228269U JP 11410986 U JP11410986 U JP 11410986U JP 11410986 U JP11410986 U JP 11410986U JP S6228269 U JPS6228269 U JP S6228269U
- Authority
- JP
- Japan
- Prior art keywords
- clock signal
- system clock
- generating
- control means
- arithmetic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 230000010355 oscillation Effects 0.000 description 1
Description
第１図は本考案に係るＬＳＩに使用される論理
単位回路のブロツク図、第２図はクロツク信号の
波形図、第３図は本考案ＬＳＩの構成を示すブロ
ツク図、第５図はその要部のブロツク図、第４図
は第３図の動作説明に供するフローチヤートであ
る。
符号の説明、ＬＯ：ＬＳＩ、ＬＣ：ＣＰＵ、６
：分周部、９：発振回路、１０：クロツクコント
ロール部。
Fig. 1 is a block diagram of a logic unit circuit used in the LSI according to the present invention, Fig. 2 is a waveform diagram of a clock signal, Fig. 3 is a block diagram showing the configuration of the LSI of the present invention, and Fig. 5 is its outline. FIG. 4 is a flowchart for explaining the operation of FIG. Explanation of symbols, LO: LSI, LC: CPU, 6
: Frequency division section, 9: Oscillation circuit, 10: Clock control section.
Claims (1)
と、 上記信号発生手段から発生する基本クロツク信
号に基づいて、演算動作に使用されるシステムク
ロツク信号を発生する手段と、 上記システムクロツク信号の供給によつて、演
算動作を成す演算制御手段と、 演算動作開始指示信号に基づいて上記システム
クロツク信号を上記演算制御手段に供給すると共
に該演算制御手段における演算動作の終了に伴つ
て上記システムクロツク信号の上記演算制御手段
への供給を停止するクロツクコントロール手段と
を具備したことを特徴とする集積回路装置。[Claims for Utility Model Registration] Signal generating means for constantly generating a basic clock signal; means for generating a system clock signal used for arithmetic operations based on the basic clock signal generated from the signal generating means; The system clock signal is supplied to the arithmetic control means for performing arithmetic operation by supplying the system clock signal; An integrated circuit device comprising clock control means for stopping supply of the system clock signal to the arithmetic control means upon termination of the system clock signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11410986U JPS6228269U (en) | 1986-07-24 | 1986-07-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11410986U JPS6228269U (en) | 1986-07-24 | 1986-07-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6228269U true JPS6228269U (en) | 1987-02-20 |
Family
ID=30996541
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11410986U Pending JPS6228269U (en) | 1986-07-24 | 1986-07-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6228269U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4842364A (en) * | 1971-09-30 | 1973-06-20 | ||
| JPS499169A (en) * | 1972-03-25 | 1974-01-26 |
-
1986
- 1986-07-24 JP JP11410986U patent/JPS6228269U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4842364A (en) * | 1971-09-30 | 1973-06-20 | ||
| JPS499169A (en) * | 1972-03-25 | 1974-01-26 |
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