JPS62280952A - System for supplying clock to timer - Google Patents

Abstract

PURPOSE:To insure a DMA against affecting the accuracy that a timer counts clocks by taking an AND between a DMA response signal and a clock with a phase the same as a system clock and supplying a clock taking an OR between the system clock and the output to a timer. CONSTITUTION:An alternative clock generator 7 generating the clock with the phase the same as the system clock being the output of a system clock generator 1, a coincidence output circuit 5 and a selection output circuit 6 are provided. The coincidence output circuit 5 ANDs the output clock of the alternative clock generator 7 and the DMA response signal, and the selection output circuit 6 supplies the clock signal taking the OR between the AND signal and the system clock to the timer 3. If the clock is expanded by the DMA, the clock with the phase the same as the system clock and the DMA response signal are ANDed, and the clock signal taking the OR between the AND signal and the system clock is supplied. Consequently the expanded clock is corrected, and the reading of the timer never has errors.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] In a processor system that performs direct memory access using a bus method and a cycle stealing method, a logical product of a clock that is in phase with the system clock and a DMA response signal is calculated. A clock obtained by logically ORing this output with the system clock is supplied to the timer.

[Industrial application field]

The present invention relates to an improvement in the method of supplying a clock to a timer in a processor system that performs direct memory access using a bus method and a cycle steal method.

[Conventional technology]

FIG. 4 is a diagram showing an example of a conventional clock supply method to a timer.

FIG. 5 is a time chart inside the timer.

In the figure, ■ is the system clock generator, 2 is the processor,
3 is a timer, 4 is a clock generator for timer counting, 8
9 is a sampling circuit, and 9 is an internal counter.

In a processor system that uses a bus method and performs cycle-stealing direct memory access (hereinafter referred to as DMA), the system clock generator 1 outputs a clock to the processor as shown in FIG. 2
, and timer 3.

A timer count clock generator 4 generates a timer count clock (hereinafter simply referred to as a count clock) and inputs it to the timer 3.

In the timer 3, this counting clock is sampled by the sampling circuit 8 using the supplied system clock to become a clock synchronized with the system clock 7, which is used for decrementing by the internal counter 9.

[Problem that the invention seeks to solve]

However, when cycle-stealing DMA is performed, the system clock is extended by the DMA control circuit, as shown in (■) in FIG.

As described above, in the timer 3, the counting clock is synchronized by being sampled by the system clock, and then counted by the internal counter to set a predetermined time.

■ in Figure 5 is a pulse created by counter 9 of timer 3 when the system clock is not extended, but when the system clock is extended by performing DMA, the original counting clock and the system clock are synchronized. A difference occurs between the counted clocks.

As a result, highly accurate counting cannot be performed, and a problem arises in that the timer value created as shown in (2) in FIG. 5 is different from the regular timer value shown in (2) in FIG.

The problem with this is that the higher the frequency of the counting clock and the smaller the counted value, the larger the error becomes.

[Means for solving problems]

As shown in the principle diagram in Figure 1, the above problem arises in a processor system that performs bus-based and cycle-stealing DMA using an alternative clock that generates a clock that is in phase with the system clock output from the system clock generator 1. A generator 7, a -default output circuit 5, and a selection output circuit 6 are provided,
The coincidence output circuit 5 performs the logical product of the output clock of the alternative clock generator 7 and the DMA response signal, and outputs the logical product to the selection output circuit 6.
This can be solved by supplying the timer 3 with a clock signal obtained by taking the logical sum of the AND signal and the system clock.

[Effect]

According to the present invention, even if the clock is extended by DMA, a clock signal having the same phase as the system clock and the DMA response signal is logically ANDed, and a clock signal obtained by logically ORing the logical product signal and the system clock is supplied. Therefore, since the extended system clock is corrected, there will be no error in the timer value.

〔Example〕

In the present invention, the clock and D
The MA response signal is logically ANDed, the logical product signal and the system clock are logically summed, and this logical sum signal is supplied to the timer 3 as a clock.

Therefore, since a clock is generated even when the system clock is extended by DMA, the counting accuracy of the timer 3 will not deteriorate.

FIG. 2 is a diagram showing an embodiment of a clock supply method to a timer according to the present invention.

FIG. 3 is an explanatory diagram of the operation.

In the figure, 5 is a coincidence output circuit (AND circuit), and 6 is a selection output circuit (OR circuit).

The output of system clock generator 1 is clocked by DMA.
This is the system clock that increases the clock speed, and is indicated by ■ in Figure 3.

The output of the alternative clock generator 7 is substantially in phase with the output of the system crosshair generator 1, and is a clock that is not affected by DMA, and is indicated by ■ in FIG.

The DMA response signal is a signal that becomes "H" while the system clock (2) is extended by DMA, and is shown in (2) in FIG.

Since the clock ■ and the DMA response signal ■ are applied to the AND circuit 5, the clock ■ shown in FIG. 3 is obtained as its output.
Since this clock (2) and the system clock (2) are applied to the OR circuit 6, a timer enable clock (2) as shown in FIG. 3 is obtained.

Of this timer enable clock ■, only the pulses marked with * are in phase with the clock ■.

Since such a timer enable clock ■ is applied to timer 3, even if the system clock ■ is extended due to DMA, counting is performed within timer 3 without being affected in any way, thereby improving the accuracy of counting. Therefore, the timer value created by timer 3 is almost the same as the timer value (■) when the clock is not extended, as shown in (■) in FIG.

〔Effect of the invention〕

As described above in detail, the present invention has the great effect that the accuracy of timer counting is not affected by DMA.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention. FIG. 2 is a diagram showing an embodiment of a clock supply method to a timer according to the present invention. FIG. 3 is an explanatory diagram of the operation. FIG. 4 is a diagram showing an example of a conventional clock supply method to a timer. FIG. 5 is a time chart inside the timer. In the figure, 1 is a system clock generator, 2 is a processor,
3 is a timer, 4 is a timer count clock generator, 5
6 is a coincidence output circuit (AND circuit), 6 is a selection output circuit (OR circuit), 7 is an alternative clock generator, 8 is a sampling circuit, and 9 is an internal counter. Fig. 1 shows an example of a clock supply method to a timer according to the present invention Fig. 4 shows an example of a conventional clock supply method to a timer

Claims (1)

[Scope of Claims] A clock supply method to a timer in a processor system that performs direct memory access using a bus method and a cycle steal method in which data is transferred by extending the clock, the system clock generator (1) An alternative clock generator (7) that generates a clock in phase with the output system clock, a coincidence output circuit (5), and a selection output circuit (6) are provided, and the coincidence output circuit (5) generates the alternative clock. Generator (7
), and the selection output circuit (6) supplies the timer (3) with a clock signal obtained by ORing the signal of the coincidence output and the system clock. Clock supply method to the timer.