JPS62280665A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To easily specify a LSI where trouble occurs by providing a means which can control the output of an output buffer circuit irrespective of a logic input. CONSTITUTION:A control voltage is applied to a terminal 11 to control the output of an output terminal 4 to logic 0 or a high-impedance state regardless of the logical state of an input terminal 5. In this case, the control voltage of the terminal is passed through a voltage clamping means 24 to control the states of a logic circuit 20 and the output buffer circuit 22.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] The output of an output buffer circuit connected to a logic circuit is controlled by a voltage clamping means to detect defective locations in a plurality of logic circuits connected to a common bus. It is easy to distinguish between

[Industrial application field]

The present invention relates to a FET logic circuit, and more particularly to a FET logic circuit having an output buffer circuit.More specifically, the present invention relates to a FET logic circuit, and more particularly, the logic output of the output buffer circuit can be controlled to a logic 0 or high impedance state regardless of the logic input. This invention relates to an output buffer circuit.

Logic circuits using FETs, especially inverter circuits, are the most widely used among semiconductor circuits.

Such circuits are often equipped with an output buffer and connected to a common bus. However, if a fault occurs in which any output element is fixed at a high level in a commonly connected circuit, it is difficult to discover the faulty element or circuit.

Therefore, there is a demand for an output buffer circuit that can be easily diagnosed.

[Conventional technology]

An example of an inverter configured using a depletion type FET and an enhancement type FET is shown in FIG. In this circuit, a depletion type buffer FE73 (output buffer circuit) receives the output of an enhancement type FETI (inverter) whose load is a depletion type FET2 based on a signal input to an input terminal 5, and supplies the output to a terminal 4. It is something to do.

Figure 7 shows depression type FET9,2 and depression type FET! In this example, a logic circuit is configured by F, T3, and T6, and an output is obtained via an enhancement type FET7 (output buffer circuit).

These circuits are implemented as an LSI, and the output terminals 4 are commonly connected to a bus 8, as shown in FIG. Therefore, in order to identify the LSI that is causing the failure, it is necessary to remove each LSI, which is a waste of time and effort.

[Problem that the invention seeks to solve]

In this conventional method, if any LSI or output buffer circuit produces an output that is fixed at a high level due to a failure, it is difficult to identify the circuit causing the failure.

The present invention was created in view of these points, and by providing a simple means that can control the output of the output buffer circuit regardless of the logic input, it is possible to control the LS that is causing the failure.
It is an object of the present invention to provide an output buffer circuit in which I can be easily specified.

[Means for solving problems]

FIG. 1 shows a diagram of the principle of the present invention.

In the figure, 22 is an output buffer circuit connected to the logic circuit 20 such as an inverter circuit, and 5 is an output buffer circuit connected to the logic circuit 20 such as an inverter circuit.
4 is an input terminal of the logic circuit 20, and 4 is an output terminal of the logic circuit 20. Reference numeral 11 is a control terminal of a voltage clamping means 24 that controls the state of the output buffer circuit within the logic circuit 10.

[For production]

By applying a control voltage to the control terminal 11, the output of the output terminal 4 can be controlled to a logic 0 or high impedance state regardless of the logic state of the input terminal 5. In general,
By setting the control terminal 11 to logic O, the logic circuit 20
The output of the output terminal 4 of the output buffer circuit 22 becomes logic 0 regardless of the operation of the output buffer circuit 22. Normally, the control terminal 11 is pulled up by being connected to a power supply, and operates so as not to interfere with the operations of the logic circuit 20 and the output buffer circuit 22.

〔Example〕

FIG. 2 shows an embodiment of the present invention, in which a diode 12 and a resistor 13 (corresponding to the voltage clamping means 24 in FIG. ) and a control terminal 11 for controlling the gate potential of the FET 3. That is, the gate potential of the FET 3 can be controlled depending on the voltage level state of the control terminal 11, and the output of the output terminal 4 can be controlled to logic O regardless of the state of the input terminal 5.

FIG. 3 shows another embodiment of the present invention, which is different from the conventional example shown in FIG. It consists of:

FIG. 4 shows an example in which an enhancement type FET 15 is used in place of the diode 12, 12'' shown in FIG. , by applying a voltage to the control terminal 11 so that the potential between the gate and source of the FET of the output buffer circuit becomes below the threshold voltage, the FET of the output buffer circuit is turned off and the input logic of the input terminal 5 is turned off. The level of the output terminal 4 can be forcibly set to 0 regardless of how it is done.In general, the control terminal 11 is pulled up to a high potential by connecting it to a power supply, etc. (as shown in Fig. 4). In this case, by connecting the control terminal 11 to the power supply on the low potential side)
, the functions of the logic circuit and the output buffer circuit can be prevented from being affected equally.

FIG. 5 shows still another embodiment of the present invention, which is an example in which enhancement type FEs 716 and 17 are connected in series in a buffer stage. In this circuit, as in the above-mentioned circuit, the control terminal 11 is set to logic 0 or connected to a low voltage source by grounding, etc., so that the state of the output terminal 4 is determined in combination with the state of the input terminal 5. can be controlled to a logic 0 or high impedance state (also referred to as a tri-state state).

Although the above describes a one-man operated logic circuit, the present invention can be applied regardless of the number of logic inputs, the type of voltage clamp circuit elements, the polarity of the voltage used, or the type of FET used. It is not limited to particular embodiments.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to control the output of the output buffer circuit to a logic 0 or high impedance state regardless of the logic input, and to
An output buffer circuit in which I can be easily specified can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a circuit diagram of an embodiment of the invention, Fig. 3 is a circuit diagram of another embodiment of the invention, and Fig. 4 is a modification of Fig. 3. 5 is a circuit diagram of another embodiment of the present invention, FIGS. 6 and 7 are circuit diagrams of a conventional example, and FIG. 8 is a circuit diagram suitable for use with the circuit according to the present invention. FIG. 2 is a block diagram showing an example of the configuration of a bus. In FIGS. 1 and 2, l is an enhancement type FET. 2 is a depression type FET. 3 is a depletion type FET in the output buffer circuit
. 4 is an output terminal, 5 is an input terminal, 11 is a control terminal, 12 is a diode, 13 is a resistor, 20 is a logic circuit, 22 is an output buffer circuit, and 24 is a voltage clamp means. Block diagram of the principle of the present invention Figure 1 Figure 2 Figure 11 Other embodiments of the present invention IK 3 Figure Other embodiments of the present invention Figure 4 Figure 5 Circuit diagram of conventional example Figure 6 Configuration example of bus No. 8 figure

Claims (7)

[Claims] (1) Logic circuit consisting of field effect transistors (20
), the voltage clamping means (22) being connected to the connection between the logic circuit and the output buffer circuit;
4), and the voltage clamping means includes a control terminal (11) for controlling the output of the output buffer circuit (22).
) is provided. (2) By supplying a signal indicating logic 0 (1) to the control terminal, the output of the output buffer circuit becomes logic 0 or a high impedance state, and logic 1 (0) is supplied to the control terminal.
2. The output buffer circuit according to claim 1, wherein the output of the output buffer circuit becomes a logic determined by the output logic of the logic circuit by being supplied with a signal indicating . (3) The output buffer circuit consists of one field effect transistor whose drain is connected to a power supply line, and the voltage between the gate and source of the field effect transistor is determined by the voltage applied to the control terminal of the field effect transistor. 2. The output buffer circuit according to claim 1, wherein the output buffer circuit is controlled to be below a threshold voltage. (4) 2 where the output buffer circuit is connected between the power lines
The gate-source voltage of the high-potential side field-effect transistor of the two field-effect transistors is lowered below the threshold voltage of the field-effect transistor by the voltage applied to the control terminal. 2. The output buffer circuit according to claim 1, wherein the output buffer circuit is controlled. (5) The output buffer circuit according to claims 3 and 4, wherein the output buffer circuit is not affected in any way by the voltage clamping means when a voltage is applied to the control terminal. (6) The output buffer circuit according to claim 1, wherein the field effect transistor is a MESFET (Schottky junction field effect transistor). (7) The output buffer circuit according to claim 1, wherein the field effect transistor is a MISFET (metal-insulator-semiconductor field-effect transistor).