JPS62279742A - Bit string comparison circuit - Google Patents

Abstract

PURPOSE:To enhance an output information amount by inputting the first decision result of sequentially inputted signals in the second decision circuit in two bit strings which are two sets of bit strings group arranged in the same order and converting in parallel and series the output signal in the third decision circuit to obtain output. CONSTITUTION:A data signal D1 consisting of bit strings D1-1-D1-16 and a data signal D2 consisting of bit strings D2-1-D2-16 are equal signals except the difference of the array order of each string. And an exclusive OR circuit 1-j inputs the bit strings D1-j and D2-j, and decides whether they are equal or not equal every bit and outputs a signal Sj which becomes '0' when bits are equal each other and becomes '1' when not equal. Next OR circuits 2-1, 2-2, 2-3 and 2-4 generates signals S21, S22, S23 and S24. On the other hand a clock distribution part 5 generates clock signals CL1-CL4 from a clock signal CLin and the leading of one of these clock signals coincides with the leading of the clock signal CLin. After the signals S21-S24 are punched by the signals CL1-CL4 in AND circuits 3-1-3-4, they are composed in an OR circuit 4 so as to output a signal SO.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Industrial Field of Application] The present invention relates to a bit string comparison circuit, and in particular, to a bit string comparison circuit, in particular, each column (each consisting of a plurality of bit strings) is compatible except for differences in the arrangement order. The present invention relates to a bit string comparison circuit for determining whether or not the arrangement order of two data signals equal to .

[Conventional technology]

Such bit string comparison circuits are often required in electronic devices that handle data signals. A conventional bit string comparison circuit will be briefly explained, taking as an example the case where it is used for line switching in a digital wireless communication system that has a working line and a protection line and uses a 16-value quadrature frequency @KWA system.

The data signal input as a single bit string from the transmitting carrier terminal station is divided into two parts by the hybrid, and - ten thousand is the working line.
The other is transmitted over the protection line. Since the 16-value orthogonal amplitude-variable P wave is created from 4 columns of data signals, the hybrid 2
The outputs are serial-parallel converted from each column to four columns. The arrangement order of the four columns is not determined due to the phase uncertainty of the branch stations. In other words, it is uncertain in which column a certain bit in one column of data signals is placed among the four columns of converted data signals. Therefore, the arrangement order of the four columns of data signals input to the working transmitter and the standby transmitter is not necessarily the same. On the receiving side, the working receiver outputs the data signal input to the working transmitter, and the standby receiver outputs the data signal input to the standby transmitter, so each of these two sets of 4-column data signals on the receiving side However, the order of the arrays does not necessarily match.

The propagation delay time in the wireless transmission path fluctuates due to fading, etc., and this fluctuation does not necessarily match between the working line and the protection line, so the two sets of data signals on the receiving side are not only different in the arrangement order mentioned above, but also in timing. They do not necessarily match within one time slot. These binary data signals are serial-parallel converted from 1 column to (for example) 4 columns for each column, and are converted from 4 columns to 16 columns, respectively. This conversion increases the time slot length by four times, so that the difference in propagation delay between the working line and the protection line can be absorbed. However, the arrangement order of these two sets of 16 columns of data signals does not necessarily match.

By comparing two sets of 16 columns of data signals with a bit string comparison circuit, it is determined whether or not the arrangement order matches. For example, when switching from the working line to the protection line, if the arrangement order does not match, the arrangement order of the 16 columns of data signals on the protection line side is switched and the working line &! Match the arrangement order of data signals in the 16 columns on the side. The arrangement order of the 16 columns of data signals created by serial-to-parallel conversion of one column of data signals is one of 16 arrangement orders that are cyclically different from each other. Therefore, each of the two sets of 16 If the arrangement order of the data signals in one column is changed cyclically for each column up to 15 times, the arrangement order of the data signals in one column will always match the other arrangement order. By switching from one of the two sets of data signals arranged in the same order to the other at the timing when the respective bits match, line switching can be performed without code errors.

FIG. 2 is a block diagram showing one of the conventional examples of the above-mentioned bit string comparison circuit.

The exclusive OR (hereinafter referred to as EX-OR) circuit 1-1 is
The bit strings D1-] and D2-1, which are the first columns of each of the 16 columns of data signals DJ-D2, are input, and the signal S
Outputs 1. If the bits of the bit string D]-1 and D2-1 match each other, the signal S1 becomes V"0#, and if they do not match, the signal S1 becomes 11". EX-OR circuit 1-2 to 1-
16 is the bit string D1-2~]6 and D2-2~1
6 and outputs similar signals 82-816. 08
The circuit 6 inputs the signals 81 to 816 and calculates the logical sum as the signal 81.
Output as 7. The signal 817 is output once for each time slot of the data signals DJ and D2.

The arrangement order of data signals D1 and D2 is the same,
Moreover, if there is no transmission code error, the bit string DI-j-0
The bits of 2-j (j is an integer from 1 to 16) always match each other, and all signals 8j are continuous %O1.
17 is also a continuation of 10'. However, in reality, the signal S17 may become '1' due to a transmission code error, although the probability is small. If the arrangement order of the data signals D1 and D2 does not match each other, there is usually a high probability that the signal 817
becomes 1'. By counting the signal 817 for a predetermined period of time to find the probability that the signal 817 becomes ``I'', it is determined whether the arrangement order of the data signals Di and D2 matches or does not match.

However, when the data signal input from the transmitting carrier terminal station has a light load and has almost no bit change components, the conventional example shown in Fig. 2 determines whether the arrangement order of the data signal D/D2 matches or does not match. It becomes very difficult to do so. This will be further explained below.

The data signal input from the transmitting carrier terminal station is 140Mbp.
Suppose that s. For example, a 14QMbps data signal constitutes one superframe with 2928 bits, and each superframe has 1.1.1.1.1.0.1.
Contains frame synchronization bits in a pattern of 0, 0, 0, O-O. Consider a case where all bits other than this frame synchronization bit become '0' (or 11'). At this time, all frame synchronization bits are data signal D.
]・Assuming that they are placed in the same time slot of D2,
If the arrangement order of the data signals D1 and D2 does not match each other, the conventional example shown in FIG. 2 changes the signal S17 to '1#' once for each super frame, that is, for every 2928 bits. If the frequency of occurrence of %1# is small in this way, it becomes impossible to distinguish it from the occurrence of 111 due to a transmission code error9, and the conventional example shown in FIG. 2 cannot determine whether the arrangement order matches or does not match.

[Problem that the invention seeks to solve]

As explained above, the conventional bit string comparison circuit outputs a comparison result only once for each time slot of two input data signals, and therefore has the disadvantage that the amount of information output is small.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bit string comparison circuit which solves the above drawbacks and outputs a large amount of information.

[Means for solving problems]

The bit string comparison circuit of the present invention comprises two sets of bit string groups in which m×n bit strings (m and n are integers #1 of 2 or more) are arranged in orders that are not necessarily equal to each other. m×n coincidence determining means for inputting the two bit strings in each of the orders, determining whether the bits match or do not match, and outputting the result of the determination as a first determination signal; It inputs m determination signals of the same type and determines whether all of them indicate a match, or whether at least one of them indicates a mismatch.

n logical means for outputting a determination result as a second determination signal; and parallel-to-serial conversion means for inputting the n second determination signals, converting them from parallel to serial, and outputting them as a third determination signal. Prepared and configured.

〔Example〕

The present invention will be described in detail below with reference to drawings showing embodiments.

FIG. 1 is a block diagram showing an embodiment of a bit string comparison circuit according to the present invention.

In the embodiment shown in FIG. 1, bit strings D1-1 to D1-16
and bit strings D2-1 to D2-16 are input, and signals 81 to 81 are input.
EX-OR circuits 1-1 to 1-16 that output 816;
Signal S] An OR circuit 2-1 inputs ~S4 and outputs signal 821; OR circuit 2-2 inputs signals 85~S8 and outputs signal 822; and OR circuit 2-2 inputs signals 89~S12 and outputs signal 821;
OR circuit 2-3 outputting 23 and signal S]3 to 816
OR circuit 2-4 which inputs and outputs signal 824.

AND circuit 3-1 inputting signals 821 to S24 and clock signals CL1 to CL4 and outputting signals 831 to 834
-3-4, an OR circuit 4 which inputs signals 831-S34 and outputs a signal SO, and a clock distribution section 5 which inputs a clock signal CLin and outputs clock signals CLI-CL4.

The clock distribution section 5 includes a flip-flop circuit (hereinafter referred to as FB).
') 51 to 54 and a NAND circuit 55. Clock input terminal C of FF51-54
Input the link signal CLin. FF51~53
The output of the non-inverting output terminal Q is inputted to the data input terminals of the FFs 52 to 54 and the NAND circuit 55. The output of the NAND circuit 55 is input to the data input terminal of the FF 51.

The outputs of the inverted output terminals Q of the FFs 51 to 54 become the clock signals CL1 to CL4.

FIG. 3 is a time chart for explaining the operation of the embodiment shown in FIG.

Data signal D1 consisting of bit string DI-1 to Di-16
are the same signals as the data signal D2 consisting of bit strings D2-1 to D2-16 except for the difference in the arrangement order of each column.

EX-OR circuit 1-j is bit string D】-j and bit string D
2-j, determines whether the bits match or do not match, and outputs the signal Sj, which is O1 if the bits match, and %11 if they do not match. This is the same as in the conventional example shown in the figure. Since the OR circuit 2-1 outputs the logical sum of the signals 81 to S4 as the signal 82], the signal 821 is not 10', but only in the time slot in which all of the signals S] to 84 indicate a match. But if there is something that shows a discrepancy, it becomes %11. OR circuits 2-2, 2-3, and 2-4 output signals S5 to S8 in four ways.
- Signals 822 and 82 from S9 to 812 and 813 to 816
Make 3.824.

The clock signal CLin is a clock for the data signals D1 and D2, and the bit string Di −j (i digit 1 or 2).
The signal 8j and the signals 821 to 824 have a timing relationship as shown in FIG.

The R02 distribution section 5 generates the clock signals CLI to CL4 shown in FIG. 3 from the clock signal CL in .

The clock signals CL1 to CL4 have a period 11' of ]/4 and a period "'O' of 3/4 of the period T of the clock signal CLi.
K, and the phases are sequentially shifted by T/4. The rising edge of any one of the clock signals CLI-CL4 coincides with the rising edge of the clock signal CLin. Which one of them will be depends on the initial conditions of the FFs 51 to 54, and in FIG. 3, it is the clock signal CLI.

The signals 821 to 824 are extracted by the pulse waveforms of the clock signals CL1 to CL4 by the AND circuits 3-1 to 3-4, and then synthesized by the OR circuit 4 to become the signal SO. In other words, AND circuits 3-1 to 3-4 and 01 (and circuit 4 combine signals 821 to 82 using clock signals CLI to CL4).
4 is parallel-serial converted to generate signal SO.

As explained above, the embodiment shown in FIG. 1 has a large amount of information because the signal SO, which is the comparison result, is output four times for each time slot of the data signals D1 and D2. This will be further explained using, as an example, the case where the embodiment shown in FIG. 1 is applied to line switching in the digital wireless communication system described in the [Prior Art] section.

The bits of one column of data signals input from the transmitting carrier terminal station are: ・1・1 ・1 ・1・0・1 ・0・0・0
・Everything becomes '0' (or 11') except for the frame synchronization bit with a pattern of 0 and 0, and the receiving side uses array I1.
Two data signals DJ with 16 columns each to compare the first order
・The array order of D2 is cyclically shifted by one column (
This is when comparing the order of arrays is most difficult.

At this time, signal 5OII:1'', data signal D]・D2
11' at least twice in the time slots in which the frame synchronization bit is prefixed (one or two consecutive), in other words at least twice in each superframe. If there is a shift of two or more columns, the signal SO becomes %11 three or more times in each superframe.

The above is the implementation example 11 shown in Figure 1. and its applications were explained.

Even if the number of columns m×n of two data signals whose arrangement order is to be compared is given, there is generally a degree of freedom in setting m and n.

For example, in the embodiment shown in FIG. 1, m=4 for 16 columns.
, n = 4, but n can also be 2 or 8. If nf is increased, the amount of information to be output will be greater than f, but as a trade-off, it is necessary to make the operation speed of the logic means and the row converting means faster.

〔Effect of the invention〕

As explained in detail above, the bit string comparison circuit of the present invention has n data signal names for each time slot of two input data signals.
Since the comparison results are outputted (n minus an integer greater than or equal to 2) times, there is an effect that the amount of information to be outputted is large.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a bit string comparison circuit of the present invention, FIG. 2 is a block diagram showing an example of a conventional bit string comparison circuit, and FIG. 3 is a block diagram showing an example of a conventional bit string comparison circuit. This is a time chart to disguise the operation. ]-1 to 1-16...EX-OR circuit, 2-1
~2-4...OR circuit% 3-3~3-4...
・・・AND circuit, 4...OR times ″18.5
・・・・・・Clock distribution section.

Claims (1)

[Claims] Two sets of bit string groups in which m×n bit strings (m and n are integers of 2 or more) are arranged in orders that are not necessarily equal to each other, each of which has two bit strings arranged in the same order. m×n matching determining means for inputting data in each of the above orders, determining whether each bit matches or not, and outputting the determination result as a first determining signal; n logical means for inputting the signals one by one, determining whether all of them indicate a match or at least one indicating a mismatch, and outputting the determination result as a second determination signal; 1. A bit string comparison circuit comprising: a parallel-to-serial conversion means for inputting a judgment signal, converting it from parallel to serial, and outputting it as a third judgment signal.